1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include "amdgpu.h" 30 #include <drm/amdgpu_drm.h> 31 #include <drm/drm_drv.h> 32 #include <drm/drm_fb_helper.h> 33 #include "amdgpu_uvd.h" 34 #include "amdgpu_vce.h" 35 #include "atom.h" 36 37 #include <linux/vga_switcheroo.h> 38 #include <linux/slab.h> 39 #include <linux/uaccess.h> 40 #include <linux/pci.h> 41 #include <linux/pm_runtime.h> 42 #include "amdgpu_amdkfd.h" 43 #include "amdgpu_gem.h" 44 #include "amdgpu_display.h" 45 #include "amdgpu_ras.h" 46 #include "amd_pcie.h" 47 48 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev) 49 { 50 struct amdgpu_gpu_instance *gpu_instance; 51 int i; 52 53 mutex_lock(&mgpu_info.mutex); 54 55 for (i = 0; i < mgpu_info.num_gpu; i++) { 56 gpu_instance = &(mgpu_info.gpu_ins[i]); 57 if (gpu_instance->adev == adev) { 58 mgpu_info.gpu_ins[i] = 59 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1]; 60 mgpu_info.num_gpu--; 61 if (adev->flags & AMD_IS_APU) 62 mgpu_info.num_apu--; 63 else 64 mgpu_info.num_dgpu--; 65 break; 66 } 67 } 68 69 mutex_unlock(&mgpu_info.mutex); 70 } 71 72 /** 73 * amdgpu_driver_unload_kms - Main unload function for KMS. 74 * 75 * @dev: drm dev pointer 76 * 77 * This is the main unload function for KMS (all asics). 78 * Returns 0 on success. 79 */ 80 void amdgpu_driver_unload_kms(struct drm_device *dev) 81 { 82 struct amdgpu_device *adev = drm_to_adev(dev); 83 84 if (adev == NULL) 85 return; 86 87 amdgpu_unregister_gpu_instance(adev); 88 89 if (adev->rmmio == NULL) 90 return; 91 92 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_UNLOAD)) 93 DRM_WARN("smart shift update failed\n"); 94 95 amdgpu_acpi_fini(adev); 96 amdgpu_device_fini_hw(adev); 97 } 98 99 void amdgpu_register_gpu_instance(struct amdgpu_device *adev) 100 { 101 struct amdgpu_gpu_instance *gpu_instance; 102 103 mutex_lock(&mgpu_info.mutex); 104 105 if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) { 106 DRM_ERROR("Cannot register more gpu instance\n"); 107 mutex_unlock(&mgpu_info.mutex); 108 return; 109 } 110 111 gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]); 112 gpu_instance->adev = adev; 113 gpu_instance->mgpu_fan_enabled = 0; 114 115 mgpu_info.num_gpu++; 116 if (adev->flags & AMD_IS_APU) 117 mgpu_info.num_apu++; 118 else 119 mgpu_info.num_dgpu++; 120 121 mutex_unlock(&mgpu_info.mutex); 122 } 123 124 /** 125 * amdgpu_driver_load_kms - Main load function for KMS. 126 * 127 * @adev: pointer to struct amdgpu_device 128 * @flags: device flags 129 * 130 * This is the main load function for KMS (all asics). 131 * Returns 0 on success, error on failure. 132 */ 133 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags) 134 { 135 struct drm_device *dev; 136 int r, acpi_status; 137 138 dev = adev_to_drm(adev); 139 140 /* amdgpu_device_init should report only fatal error 141 * like memory allocation failure or iomapping failure, 142 * or memory manager initialization failure, it must 143 * properly initialize the GPU MC controller and permit 144 * VRAM allocation 145 */ 146 r = amdgpu_device_init(adev, flags); 147 if (r) { 148 dev_err(dev->dev, "Fatal error during GPU init\n"); 149 goto out; 150 } 151 152 adev->pm.rpm_mode = AMDGPU_RUNPM_NONE; 153 if (amdgpu_device_supports_px(dev) && 154 (amdgpu_runtime_pm != 0)) { /* enable PX as runtime mode */ 155 adev->pm.rpm_mode = AMDGPU_RUNPM_PX; 156 dev_info(adev->dev, "Using ATPX for runtime pm\n"); 157 } else if (amdgpu_device_supports_boco(dev) && 158 (amdgpu_runtime_pm != 0)) { /* enable boco as runtime mode */ 159 adev->pm.rpm_mode = AMDGPU_RUNPM_BOCO; 160 dev_info(adev->dev, "Using BOCO for runtime pm\n"); 161 } else if (amdgpu_device_supports_baco(dev) && 162 (amdgpu_runtime_pm != 0)) { 163 switch (adev->asic_type) { 164 case CHIP_VEGA20: 165 case CHIP_ARCTURUS: 166 /* enable BACO as runpm mode if runpm=1 */ 167 if (amdgpu_runtime_pm > 0) 168 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO; 169 break; 170 case CHIP_VEGA10: 171 /* enable BACO as runpm mode if noretry=0 */ 172 if (!adev->gmc.noretry) 173 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO; 174 break; 175 default: 176 /* enable BACO as runpm mode on CI+ */ 177 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO; 178 break; 179 } 180 181 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) 182 dev_info(adev->dev, "Using BACO for runtime pm\n"); 183 } 184 185 /* Call ACPI methods: require modeset init 186 * but failure is not fatal 187 */ 188 189 acpi_status = amdgpu_acpi_init(adev); 190 if (acpi_status) 191 dev_dbg(dev->dev, "Error during ACPI methods call\n"); 192 193 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_LOAD)) 194 DRM_WARN("smart shift update failed\n"); 195 196 out: 197 if (r) 198 amdgpu_driver_unload_kms(dev); 199 200 return r; 201 } 202 203 static enum amd_ip_block_type 204 amdgpu_ip_get_block_type(struct amdgpu_device *adev, uint32_t ip) 205 { 206 enum amd_ip_block_type type; 207 208 switch (ip) { 209 case AMDGPU_HW_IP_GFX: 210 type = AMD_IP_BLOCK_TYPE_GFX; 211 break; 212 case AMDGPU_HW_IP_COMPUTE: 213 type = AMD_IP_BLOCK_TYPE_GFX; 214 break; 215 case AMDGPU_HW_IP_DMA: 216 type = AMD_IP_BLOCK_TYPE_SDMA; 217 break; 218 case AMDGPU_HW_IP_UVD: 219 case AMDGPU_HW_IP_UVD_ENC: 220 type = AMD_IP_BLOCK_TYPE_UVD; 221 break; 222 case AMDGPU_HW_IP_VCE: 223 type = AMD_IP_BLOCK_TYPE_VCE; 224 break; 225 case AMDGPU_HW_IP_VCN_DEC: 226 case AMDGPU_HW_IP_VCN_ENC: 227 type = AMD_IP_BLOCK_TYPE_VCN; 228 break; 229 case AMDGPU_HW_IP_VCN_JPEG: 230 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 231 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 232 break; 233 default: 234 type = AMD_IP_BLOCK_TYPE_NUM; 235 break; 236 } 237 238 return type; 239 } 240 241 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, 242 struct drm_amdgpu_query_fw *query_fw, 243 struct amdgpu_device *adev) 244 { 245 switch (query_fw->fw_type) { 246 case AMDGPU_INFO_FW_VCE: 247 fw_info->ver = adev->vce.fw_version; 248 fw_info->feature = adev->vce.fb_version; 249 break; 250 case AMDGPU_INFO_FW_UVD: 251 fw_info->ver = adev->uvd.fw_version; 252 fw_info->feature = 0; 253 break; 254 case AMDGPU_INFO_FW_VCN: 255 fw_info->ver = adev->vcn.fw_version; 256 fw_info->feature = 0; 257 break; 258 case AMDGPU_INFO_FW_GMC: 259 fw_info->ver = adev->gmc.fw_version; 260 fw_info->feature = 0; 261 break; 262 case AMDGPU_INFO_FW_GFX_ME: 263 fw_info->ver = adev->gfx.me_fw_version; 264 fw_info->feature = adev->gfx.me_feature_version; 265 break; 266 case AMDGPU_INFO_FW_GFX_PFP: 267 fw_info->ver = adev->gfx.pfp_fw_version; 268 fw_info->feature = adev->gfx.pfp_feature_version; 269 break; 270 case AMDGPU_INFO_FW_GFX_CE: 271 fw_info->ver = adev->gfx.ce_fw_version; 272 fw_info->feature = adev->gfx.ce_feature_version; 273 break; 274 case AMDGPU_INFO_FW_GFX_RLC: 275 fw_info->ver = adev->gfx.rlc_fw_version; 276 fw_info->feature = adev->gfx.rlc_feature_version; 277 break; 278 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL: 279 fw_info->ver = adev->gfx.rlc_srlc_fw_version; 280 fw_info->feature = adev->gfx.rlc_srlc_feature_version; 281 break; 282 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM: 283 fw_info->ver = adev->gfx.rlc_srlg_fw_version; 284 fw_info->feature = adev->gfx.rlc_srlg_feature_version; 285 break; 286 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM: 287 fw_info->ver = adev->gfx.rlc_srls_fw_version; 288 fw_info->feature = adev->gfx.rlc_srls_feature_version; 289 break; 290 case AMDGPU_INFO_FW_GFX_RLCP: 291 fw_info->ver = adev->gfx.rlcp_ucode_version; 292 fw_info->feature = adev->gfx.rlcp_ucode_feature_version; 293 break; 294 case AMDGPU_INFO_FW_GFX_RLCV: 295 fw_info->ver = adev->gfx.rlcv_ucode_version; 296 fw_info->feature = adev->gfx.rlcv_ucode_feature_version; 297 break; 298 case AMDGPU_INFO_FW_GFX_MEC: 299 if (query_fw->index == 0) { 300 fw_info->ver = adev->gfx.mec_fw_version; 301 fw_info->feature = adev->gfx.mec_feature_version; 302 } else if (query_fw->index == 1) { 303 fw_info->ver = adev->gfx.mec2_fw_version; 304 fw_info->feature = adev->gfx.mec2_feature_version; 305 } else 306 return -EINVAL; 307 break; 308 case AMDGPU_INFO_FW_SMC: 309 fw_info->ver = adev->pm.fw_version; 310 fw_info->feature = 0; 311 break; 312 case AMDGPU_INFO_FW_TA: 313 switch (query_fw->index) { 314 case TA_FW_TYPE_PSP_XGMI: 315 fw_info->ver = adev->psp.xgmi_context.context.bin_desc.fw_version; 316 fw_info->feature = adev->psp.xgmi_context.context 317 .bin_desc.feature_version; 318 break; 319 case TA_FW_TYPE_PSP_RAS: 320 fw_info->ver = adev->psp.ras_context.context.bin_desc.fw_version; 321 fw_info->feature = adev->psp.ras_context.context 322 .bin_desc.feature_version; 323 break; 324 case TA_FW_TYPE_PSP_HDCP: 325 fw_info->ver = adev->psp.hdcp_context.context.bin_desc.fw_version; 326 fw_info->feature = adev->psp.hdcp_context.context 327 .bin_desc.feature_version; 328 break; 329 case TA_FW_TYPE_PSP_DTM: 330 fw_info->ver = adev->psp.dtm_context.context.bin_desc.fw_version; 331 fw_info->feature = adev->psp.dtm_context.context 332 .bin_desc.feature_version; 333 break; 334 case TA_FW_TYPE_PSP_RAP: 335 fw_info->ver = adev->psp.rap_context.context.bin_desc.fw_version; 336 fw_info->feature = adev->psp.rap_context.context 337 .bin_desc.feature_version; 338 break; 339 case TA_FW_TYPE_PSP_SECUREDISPLAY: 340 fw_info->ver = adev->psp.securedisplay_context.context.bin_desc.fw_version; 341 fw_info->feature = 342 adev->psp.securedisplay_context.context.bin_desc 343 .feature_version; 344 break; 345 default: 346 return -EINVAL; 347 } 348 break; 349 case AMDGPU_INFO_FW_SDMA: 350 if (query_fw->index >= adev->sdma.num_instances) 351 return -EINVAL; 352 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version; 353 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version; 354 break; 355 case AMDGPU_INFO_FW_SOS: 356 fw_info->ver = adev->psp.sos.fw_version; 357 fw_info->feature = adev->psp.sos.feature_version; 358 break; 359 case AMDGPU_INFO_FW_ASD: 360 fw_info->ver = adev->psp.asd_context.bin_desc.fw_version; 361 fw_info->feature = adev->psp.asd_context.bin_desc.feature_version; 362 break; 363 case AMDGPU_INFO_FW_DMCU: 364 fw_info->ver = adev->dm.dmcu_fw_version; 365 fw_info->feature = 0; 366 break; 367 case AMDGPU_INFO_FW_DMCUB: 368 fw_info->ver = adev->dm.dmcub_fw_version; 369 fw_info->feature = 0; 370 break; 371 case AMDGPU_INFO_FW_TOC: 372 fw_info->ver = adev->psp.toc.fw_version; 373 fw_info->feature = adev->psp.toc.feature_version; 374 break; 375 case AMDGPU_INFO_FW_CAP: 376 fw_info->ver = adev->psp.cap_fw_version; 377 fw_info->feature = adev->psp.cap_feature_version; 378 break; 379 case AMDGPU_INFO_FW_MES_KIQ: 380 fw_info->ver = adev->mes.kiq_version & AMDGPU_MES_VERSION_MASK; 381 fw_info->feature = (adev->mes.kiq_version & AMDGPU_MES_FEAT_VERSION_MASK) 382 >> AMDGPU_MES_FEAT_VERSION_SHIFT; 383 break; 384 case AMDGPU_INFO_FW_MES: 385 fw_info->ver = adev->mes.sched_version & AMDGPU_MES_VERSION_MASK; 386 fw_info->feature = (adev->mes.sched_version & AMDGPU_MES_FEAT_VERSION_MASK) 387 >> AMDGPU_MES_FEAT_VERSION_SHIFT; 388 break; 389 case AMDGPU_INFO_FW_IMU: 390 fw_info->ver = adev->gfx.imu_fw_version; 391 fw_info->feature = 0; 392 break; 393 case AMDGPU_INFO_FW_VPE: 394 fw_info->ver = adev->vpe.fw_version; 395 fw_info->feature = adev->vpe.feature_version; 396 break; 397 default: 398 return -EINVAL; 399 } 400 return 0; 401 } 402 403 static int amdgpu_hw_ip_info(struct amdgpu_device *adev, 404 struct drm_amdgpu_info *info, 405 struct drm_amdgpu_info_hw_ip *result) 406 { 407 uint32_t ib_start_alignment = 0; 408 uint32_t ib_size_alignment = 0; 409 enum amd_ip_block_type type; 410 unsigned int num_rings = 0; 411 unsigned int i, j; 412 413 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 414 return -EINVAL; 415 416 switch (info->query_hw_ip.type) { 417 case AMDGPU_HW_IP_GFX: 418 type = AMD_IP_BLOCK_TYPE_GFX; 419 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 420 if (adev->gfx.gfx_ring[i].sched.ready) 421 ++num_rings; 422 ib_start_alignment = 32; 423 ib_size_alignment = 32; 424 break; 425 case AMDGPU_HW_IP_COMPUTE: 426 type = AMD_IP_BLOCK_TYPE_GFX; 427 for (i = 0; i < adev->gfx.num_compute_rings; i++) 428 if (adev->gfx.compute_ring[i].sched.ready) 429 ++num_rings; 430 ib_start_alignment = 32; 431 ib_size_alignment = 32; 432 break; 433 case AMDGPU_HW_IP_DMA: 434 type = AMD_IP_BLOCK_TYPE_SDMA; 435 for (i = 0; i < adev->sdma.num_instances; i++) 436 if (adev->sdma.instance[i].ring.sched.ready) 437 ++num_rings; 438 ib_start_alignment = 256; 439 ib_size_alignment = 4; 440 break; 441 case AMDGPU_HW_IP_UVD: 442 type = AMD_IP_BLOCK_TYPE_UVD; 443 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 444 if (adev->uvd.harvest_config & (1 << i)) 445 continue; 446 447 if (adev->uvd.inst[i].ring.sched.ready) 448 ++num_rings; 449 } 450 ib_start_alignment = 64; 451 ib_size_alignment = 64; 452 break; 453 case AMDGPU_HW_IP_VCE: 454 type = AMD_IP_BLOCK_TYPE_VCE; 455 for (i = 0; i < adev->vce.num_rings; i++) 456 if (adev->vce.ring[i].sched.ready) 457 ++num_rings; 458 ib_start_alignment = 4; 459 ib_size_alignment = 1; 460 break; 461 case AMDGPU_HW_IP_UVD_ENC: 462 type = AMD_IP_BLOCK_TYPE_UVD; 463 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 464 if (adev->uvd.harvest_config & (1 << i)) 465 continue; 466 467 for (j = 0; j < adev->uvd.num_enc_rings; j++) 468 if (adev->uvd.inst[i].ring_enc[j].sched.ready) 469 ++num_rings; 470 } 471 ib_start_alignment = 64; 472 ib_size_alignment = 64; 473 break; 474 case AMDGPU_HW_IP_VCN_DEC: 475 type = AMD_IP_BLOCK_TYPE_VCN; 476 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 477 if (adev->vcn.harvest_config & (1 << i)) 478 continue; 479 480 if (adev->vcn.inst[i].ring_dec.sched.ready) 481 ++num_rings; 482 } 483 ib_start_alignment = 16; 484 ib_size_alignment = 16; 485 break; 486 case AMDGPU_HW_IP_VCN_ENC: 487 type = AMD_IP_BLOCK_TYPE_VCN; 488 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 489 if (adev->vcn.harvest_config & (1 << i)) 490 continue; 491 492 for (j = 0; j < adev->vcn.num_enc_rings; j++) 493 if (adev->vcn.inst[i].ring_enc[j].sched.ready) 494 ++num_rings; 495 } 496 ib_start_alignment = 64; 497 ib_size_alignment = 1; 498 break; 499 case AMDGPU_HW_IP_VCN_JPEG: 500 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 501 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 502 503 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { 504 if (adev->jpeg.harvest_config & (1 << i)) 505 continue; 506 507 for (j = 0; j < adev->jpeg.num_jpeg_rings; j++) 508 if (adev->jpeg.inst[i].ring_dec[j].sched.ready) 509 ++num_rings; 510 } 511 ib_start_alignment = 16; 512 ib_size_alignment = 16; 513 break; 514 case AMDGPU_HW_IP_VPE: 515 type = AMD_IP_BLOCK_TYPE_VPE; 516 if (adev->vpe.ring.sched.ready) 517 ++num_rings; 518 ib_start_alignment = 256; 519 ib_size_alignment = 4; 520 break; 521 default: 522 return -EINVAL; 523 } 524 525 for (i = 0; i < adev->num_ip_blocks; i++) 526 if (adev->ip_blocks[i].version->type == type && 527 adev->ip_blocks[i].status.valid) 528 break; 529 530 if (i == adev->num_ip_blocks) 531 return 0; 532 533 num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type], 534 num_rings); 535 536 result->hw_ip_version_major = adev->ip_blocks[i].version->major; 537 result->hw_ip_version_minor = adev->ip_blocks[i].version->minor; 538 539 if (adev->asic_type >= CHIP_VEGA10) { 540 switch (type) { 541 case AMD_IP_BLOCK_TYPE_GFX: 542 result->ip_discovery_version = 543 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, GC_HWIP, 0)); 544 break; 545 case AMD_IP_BLOCK_TYPE_SDMA: 546 result->ip_discovery_version = 547 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, SDMA0_HWIP, 0)); 548 break; 549 case AMD_IP_BLOCK_TYPE_UVD: 550 case AMD_IP_BLOCK_TYPE_VCN: 551 case AMD_IP_BLOCK_TYPE_JPEG: 552 result->ip_discovery_version = 553 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, UVD_HWIP, 0)); 554 break; 555 case AMD_IP_BLOCK_TYPE_VCE: 556 result->ip_discovery_version = 557 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, VCE_HWIP, 0)); 558 break; 559 case AMD_IP_BLOCK_TYPE_VPE: 560 result->ip_discovery_version = 561 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, VPE_HWIP, 0)); 562 break; 563 default: 564 result->ip_discovery_version = 0; 565 break; 566 } 567 } else { 568 result->ip_discovery_version = 0; 569 } 570 result->capabilities_flags = 0; 571 result->available_rings = (1 << num_rings) - 1; 572 result->ib_start_alignment = ib_start_alignment; 573 result->ib_size_alignment = ib_size_alignment; 574 return 0; 575 } 576 577 /* 578 * Userspace get information ioctl 579 */ 580 /** 581 * amdgpu_info_ioctl - answer a device specific request. 582 * 583 * @dev: drm device pointer 584 * @data: request object 585 * @filp: drm filp 586 * 587 * This function is used to pass device specific parameters to the userspace 588 * drivers. Examples include: pci device id, pipeline parms, tiling params, 589 * etc. (all asics). 590 * Returns 0 on success, -EINVAL on failure. 591 */ 592 int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 593 { 594 struct amdgpu_device *adev = drm_to_adev(dev); 595 struct drm_amdgpu_info *info = data; 596 struct amdgpu_mode_info *minfo = &adev->mode_info; 597 void __user *out = (void __user *)(uintptr_t)info->return_pointer; 598 uint32_t size = info->return_size; 599 struct drm_crtc *crtc; 600 uint32_t ui32 = 0; 601 uint64_t ui64 = 0; 602 int i, found; 603 int ui32_size = sizeof(ui32); 604 605 if (!info->return_size || !info->return_pointer) 606 return -EINVAL; 607 608 switch (info->query) { 609 case AMDGPU_INFO_ACCEL_WORKING: 610 ui32 = adev->accel_working; 611 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 612 case AMDGPU_INFO_CRTC_FROM_ID: 613 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { 614 crtc = (struct drm_crtc *)minfo->crtcs[i]; 615 if (crtc && crtc->base.id == info->mode_crtc.id) { 616 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 617 618 ui32 = amdgpu_crtc->crtc_id; 619 found = 1; 620 break; 621 } 622 } 623 if (!found) { 624 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); 625 return -EINVAL; 626 } 627 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 628 case AMDGPU_INFO_HW_IP_INFO: { 629 struct drm_amdgpu_info_hw_ip ip = {}; 630 int ret; 631 632 ret = amdgpu_hw_ip_info(adev, info, &ip); 633 if (ret) 634 return ret; 635 636 ret = copy_to_user(out, &ip, min_t(size_t, size, sizeof(ip))); 637 return ret ? -EFAULT : 0; 638 } 639 case AMDGPU_INFO_HW_IP_COUNT: { 640 enum amd_ip_block_type type; 641 struct amdgpu_ip_block *ip_block = NULL; 642 uint32_t count = 0; 643 644 type = amdgpu_ip_get_block_type(adev, info->query_hw_ip.type); 645 ip_block = amdgpu_device_ip_get_ip_block(adev, type); 646 if (!ip_block || !ip_block->status.valid) 647 return -EINVAL; 648 649 switch (type) { 650 case AMD_IP_BLOCK_TYPE_GFX: 651 case AMD_IP_BLOCK_TYPE_VCE: 652 count = 1; 653 break; 654 case AMD_IP_BLOCK_TYPE_SDMA: 655 count = adev->sdma.num_instances; 656 break; 657 case AMD_IP_BLOCK_TYPE_JPEG: 658 count = adev->jpeg.num_jpeg_inst * adev->jpeg.num_jpeg_rings; 659 break; 660 case AMD_IP_BLOCK_TYPE_VCN: 661 count = adev->vcn.num_vcn_inst; 662 break; 663 case AMD_IP_BLOCK_TYPE_UVD: 664 count = adev->uvd.num_uvd_inst; 665 break; 666 /* For all other IP block types not listed in the switch statement 667 * the ip status is valid here and the instance count is one. 668 */ 669 default: 670 count = 1; 671 break; 672 } 673 674 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; 675 } 676 case AMDGPU_INFO_TIMESTAMP: 677 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev); 678 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 679 case AMDGPU_INFO_FW_VERSION: { 680 struct drm_amdgpu_info_firmware fw_info; 681 int ret; 682 683 /* We only support one instance of each IP block right now. */ 684 if (info->query_fw.ip_instance != 0) 685 return -EINVAL; 686 687 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev); 688 if (ret) 689 return ret; 690 691 return copy_to_user(out, &fw_info, 692 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0; 693 } 694 case AMDGPU_INFO_NUM_BYTES_MOVED: 695 ui64 = atomic64_read(&adev->num_bytes_moved); 696 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 697 case AMDGPU_INFO_NUM_EVICTIONS: 698 ui64 = atomic64_read(&adev->num_evictions); 699 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 700 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS: 701 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults); 702 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 703 case AMDGPU_INFO_VRAM_USAGE: 704 ui64 = ttm_resource_manager_usage(&adev->mman.vram_mgr.manager); 705 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 706 case AMDGPU_INFO_VIS_VRAM_USAGE: 707 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr); 708 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 709 case AMDGPU_INFO_GTT_USAGE: 710 ui64 = ttm_resource_manager_usage(&adev->mman.gtt_mgr.manager); 711 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 712 case AMDGPU_INFO_GDS_CONFIG: { 713 struct drm_amdgpu_info_gds gds_info; 714 715 memset(&gds_info, 0, sizeof(gds_info)); 716 gds_info.compute_partition_size = adev->gds.gds_size; 717 gds_info.gds_total_size = adev->gds.gds_size; 718 gds_info.gws_per_compute_partition = adev->gds.gws_size; 719 gds_info.oa_per_compute_partition = adev->gds.oa_size; 720 return copy_to_user(out, &gds_info, 721 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0; 722 } 723 case AMDGPU_INFO_VRAM_GTT: { 724 struct drm_amdgpu_info_vram_gtt vram_gtt; 725 726 vram_gtt.vram_size = adev->gmc.real_vram_size - 727 atomic64_read(&adev->vram_pin_size) - 728 AMDGPU_VM_RESERVED_VRAM; 729 vram_gtt.vram_cpu_accessible_size = 730 min(adev->gmc.visible_vram_size - 731 atomic64_read(&adev->visible_pin_size), 732 vram_gtt.vram_size); 733 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size; 734 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size); 735 return copy_to_user(out, &vram_gtt, 736 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; 737 } 738 case AMDGPU_INFO_MEMORY: { 739 struct drm_amdgpu_memory_info mem; 740 struct ttm_resource_manager *gtt_man = 741 &adev->mman.gtt_mgr.manager; 742 struct ttm_resource_manager *vram_man = 743 &adev->mman.vram_mgr.manager; 744 745 memset(&mem, 0, sizeof(mem)); 746 mem.vram.total_heap_size = adev->gmc.real_vram_size; 747 mem.vram.usable_heap_size = adev->gmc.real_vram_size - 748 atomic64_read(&adev->vram_pin_size) - 749 AMDGPU_VM_RESERVED_VRAM; 750 mem.vram.heap_usage = 751 ttm_resource_manager_usage(vram_man); 752 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4; 753 754 mem.cpu_accessible_vram.total_heap_size = 755 adev->gmc.visible_vram_size; 756 mem.cpu_accessible_vram.usable_heap_size = 757 min(adev->gmc.visible_vram_size - 758 atomic64_read(&adev->visible_pin_size), 759 mem.vram.usable_heap_size); 760 mem.cpu_accessible_vram.heap_usage = 761 amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr); 762 mem.cpu_accessible_vram.max_allocation = 763 mem.cpu_accessible_vram.usable_heap_size * 3 / 4; 764 765 mem.gtt.total_heap_size = gtt_man->size; 766 mem.gtt.usable_heap_size = mem.gtt.total_heap_size - 767 atomic64_read(&adev->gart_pin_size); 768 mem.gtt.heap_usage = ttm_resource_manager_usage(gtt_man); 769 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4; 770 771 return copy_to_user(out, &mem, 772 min((size_t)size, sizeof(mem))) 773 ? -EFAULT : 0; 774 } 775 case AMDGPU_INFO_READ_MMR_REG: { 776 unsigned int n, alloc_size; 777 uint32_t *regs; 778 unsigned int se_num = (info->read_mmr_reg.instance >> 779 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & 780 AMDGPU_INFO_MMR_SE_INDEX_MASK; 781 unsigned int sh_num = (info->read_mmr_reg.instance >> 782 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & 783 AMDGPU_INFO_MMR_SH_INDEX_MASK; 784 785 /* set full masks if the userspace set all bits 786 * in the bitfields 787 */ 788 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) 789 se_num = 0xffffffff; 790 else if (se_num >= AMDGPU_GFX_MAX_SE) 791 return -EINVAL; 792 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) 793 sh_num = 0xffffffff; 794 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE) 795 return -EINVAL; 796 797 if (info->read_mmr_reg.count > 128) 798 return -EINVAL; 799 800 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL); 801 if (!regs) 802 return -ENOMEM; 803 alloc_size = info->read_mmr_reg.count * sizeof(*regs); 804 805 amdgpu_gfx_off_ctrl(adev, false); 806 for (i = 0; i < info->read_mmr_reg.count; i++) { 807 if (amdgpu_asic_read_register(adev, se_num, sh_num, 808 info->read_mmr_reg.dword_offset + i, 809 ®s[i])) { 810 DRM_DEBUG_KMS("unallowed offset %#x\n", 811 info->read_mmr_reg.dword_offset + i); 812 kfree(regs); 813 amdgpu_gfx_off_ctrl(adev, true); 814 return -EFAULT; 815 } 816 } 817 amdgpu_gfx_off_ctrl(adev, true); 818 n = copy_to_user(out, regs, min(size, alloc_size)); 819 kfree(regs); 820 return n ? -EFAULT : 0; 821 } 822 case AMDGPU_INFO_DEV_INFO: { 823 struct drm_amdgpu_info_device *dev_info; 824 uint64_t vm_size; 825 uint32_t pcie_gen_mask; 826 int ret; 827 828 dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL); 829 if (!dev_info) 830 return -ENOMEM; 831 832 dev_info->device_id = adev->pdev->device; 833 dev_info->chip_rev = adev->rev_id; 834 dev_info->external_rev = adev->external_rev_id; 835 dev_info->pci_rev = adev->pdev->revision; 836 dev_info->family = adev->family; 837 dev_info->num_shader_engines = adev->gfx.config.max_shader_engines; 838 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 839 /* return all clocks in KHz */ 840 dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; 841 if (adev->pm.dpm_enabled) { 842 dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10; 843 dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10; 844 dev_info->min_engine_clock = amdgpu_dpm_get_sclk(adev, true) * 10; 845 dev_info->min_memory_clock = amdgpu_dpm_get_mclk(adev, true) * 10; 846 } else { 847 dev_info->max_engine_clock = 848 dev_info->min_engine_clock = 849 adev->clock.default_sclk * 10; 850 dev_info->max_memory_clock = 851 dev_info->min_memory_clock = 852 adev->clock.default_mclk * 10; 853 } 854 dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; 855 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se * 856 adev->gfx.config.max_shader_engines; 857 dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; 858 dev_info->ids_flags = 0; 859 if (adev->flags & AMD_IS_APU) 860 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION; 861 if (adev->gfx.mcbp) 862 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION; 863 if (amdgpu_is_tmz(adev)) 864 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ; 865 if (adev->gfx.config.ta_cntl2_truncate_coord_mode) 866 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD; 867 868 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 869 vm_size -= AMDGPU_VA_RESERVED_SIZE; 870 871 /* Older VCE FW versions are buggy and can handle only 40bits */ 872 if (adev->vce.fw_version && 873 adev->vce.fw_version < AMDGPU_VCE_FW_53_45) 874 vm_size = min(vm_size, 1ULL << 40); 875 876 dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_SIZE; 877 dev_info->virtual_address_max = 878 min(vm_size, AMDGPU_GMC_HOLE_START); 879 880 if (vm_size > AMDGPU_GMC_HOLE_START) { 881 dev_info->high_va_offset = AMDGPU_GMC_HOLE_END; 882 dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size; 883 } 884 dev_info->virtual_address_alignment = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 885 dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE; 886 dev_info->gart_page_size = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 887 dev_info->cu_active_number = adev->gfx.cu_info.number; 888 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; 889 dev_info->ce_ram_size = adev->gfx.ce_ram_size; 890 memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0], 891 sizeof(adev->gfx.cu_info.ao_cu_bitmap)); 892 memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], 893 sizeof(dev_info->cu_bitmap)); 894 dev_info->vram_type = adev->gmc.vram_type; 895 dev_info->vram_bit_width = adev->gmc.vram_width; 896 dev_info->vce_harvest_config = adev->vce.harvest_config; 897 dev_info->gc_double_offchip_lds_buf = 898 adev->gfx.config.double_offchip_lds_buf; 899 dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size; 900 dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs; 901 dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh; 902 dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches; 903 dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth; 904 dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth; 905 dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads; 906 907 if (adev->family >= AMDGPU_FAMILY_NV) 908 dev_info->pa_sc_tile_steering_override = 909 adev->gfx.config.pa_sc_tile_steering_override; 910 911 dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask; 912 913 /* Combine the chip gen mask with the platform (CPU/mobo) mask. */ 914 pcie_gen_mask = adev->pm.pcie_gen_mask & (adev->pm.pcie_gen_mask >> 16); 915 dev_info->pcie_gen = fls(pcie_gen_mask); 916 dev_info->pcie_num_lanes = 917 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 ? 32 : 918 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 ? 16 : 919 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 ? 12 : 920 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 ? 8 : 921 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 ? 4 : 922 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 ? 2 : 1; 923 924 dev_info->tcp_cache_size = adev->gfx.config.gc_tcp_l1_size; 925 dev_info->num_sqc_per_wgp = adev->gfx.config.gc_num_sqc_per_wgp; 926 dev_info->sqc_data_cache_size = adev->gfx.config.gc_l1_data_cache_size_per_sqc; 927 dev_info->sqc_inst_cache_size = adev->gfx.config.gc_l1_instruction_cache_size_per_sqc; 928 dev_info->gl1c_cache_size = adev->gfx.config.gc_gl1c_size_per_instance * 929 adev->gfx.config.gc_gl1c_per_sa; 930 dev_info->gl2c_cache_size = adev->gfx.config.gc_gl2c_per_gpu; 931 dev_info->mall_size = adev->gmc.mall_size; 932 933 934 if (adev->gfx.funcs->get_gfx_shadow_info) { 935 struct amdgpu_gfx_shadow_info shadow_info; 936 937 ret = amdgpu_gfx_get_gfx_shadow_info(adev, &shadow_info); 938 if (!ret) { 939 dev_info->shadow_size = shadow_info.shadow_size; 940 dev_info->shadow_alignment = shadow_info.shadow_alignment; 941 dev_info->csa_size = shadow_info.csa_size; 942 dev_info->csa_alignment = shadow_info.csa_alignment; 943 } 944 } 945 946 ret = copy_to_user(out, dev_info, 947 min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0; 948 kfree(dev_info); 949 return ret; 950 } 951 case AMDGPU_INFO_VCE_CLOCK_TABLE: { 952 unsigned int i; 953 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {}; 954 struct amd_vce_state *vce_state; 955 956 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) { 957 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i); 958 if (vce_state) { 959 vce_clk_table.entries[i].sclk = vce_state->sclk; 960 vce_clk_table.entries[i].mclk = vce_state->mclk; 961 vce_clk_table.entries[i].eclk = vce_state->evclk; 962 vce_clk_table.num_valid_entries++; 963 } 964 } 965 966 return copy_to_user(out, &vce_clk_table, 967 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0; 968 } 969 case AMDGPU_INFO_VBIOS: { 970 uint32_t bios_size = adev->bios_size; 971 972 switch (info->vbios_info.type) { 973 case AMDGPU_INFO_VBIOS_SIZE: 974 return copy_to_user(out, &bios_size, 975 min((size_t)size, sizeof(bios_size))) 976 ? -EFAULT : 0; 977 case AMDGPU_INFO_VBIOS_IMAGE: { 978 uint8_t *bios; 979 uint32_t bios_offset = info->vbios_info.offset; 980 981 if (bios_offset >= bios_size) 982 return -EINVAL; 983 984 bios = adev->bios + bios_offset; 985 return copy_to_user(out, bios, 986 min((size_t)size, (size_t)(bios_size - bios_offset))) 987 ? -EFAULT : 0; 988 } 989 case AMDGPU_INFO_VBIOS_INFO: { 990 struct drm_amdgpu_info_vbios vbios_info = {}; 991 struct atom_context *atom_context; 992 993 atom_context = adev->mode_info.atom_context; 994 if (atom_context) { 995 memcpy(vbios_info.name, atom_context->name, 996 sizeof(atom_context->name)); 997 memcpy(vbios_info.vbios_pn, atom_context->vbios_pn, 998 sizeof(atom_context->vbios_pn)); 999 vbios_info.version = atom_context->version; 1000 memcpy(vbios_info.vbios_ver_str, atom_context->vbios_ver_str, 1001 sizeof(atom_context->vbios_ver_str)); 1002 memcpy(vbios_info.date, atom_context->date, 1003 sizeof(atom_context->date)); 1004 } 1005 1006 return copy_to_user(out, &vbios_info, 1007 min((size_t)size, sizeof(vbios_info))) ? -EFAULT : 0; 1008 } 1009 default: 1010 DRM_DEBUG_KMS("Invalid request %d\n", 1011 info->vbios_info.type); 1012 return -EINVAL; 1013 } 1014 } 1015 case AMDGPU_INFO_NUM_HANDLES: { 1016 struct drm_amdgpu_info_num_handles handle; 1017 1018 switch (info->query_hw_ip.type) { 1019 case AMDGPU_HW_IP_UVD: 1020 /* Starting Polaris, we support unlimited UVD handles */ 1021 if (adev->asic_type < CHIP_POLARIS10) { 1022 handle.uvd_max_handles = adev->uvd.max_handles; 1023 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev); 1024 1025 return copy_to_user(out, &handle, 1026 min((size_t)size, sizeof(handle))) ? -EFAULT : 0; 1027 } else { 1028 return -ENODATA; 1029 } 1030 1031 break; 1032 default: 1033 return -EINVAL; 1034 } 1035 } 1036 case AMDGPU_INFO_SENSOR: { 1037 if (!adev->pm.dpm_enabled) 1038 return -ENOENT; 1039 1040 switch (info->sensor_info.type) { 1041 case AMDGPU_INFO_SENSOR_GFX_SCLK: 1042 /* get sclk in Mhz */ 1043 if (amdgpu_dpm_read_sensor(adev, 1044 AMDGPU_PP_SENSOR_GFX_SCLK, 1045 (void *)&ui32, &ui32_size)) { 1046 return -EINVAL; 1047 } 1048 ui32 /= 100; 1049 break; 1050 case AMDGPU_INFO_SENSOR_GFX_MCLK: 1051 /* get mclk in Mhz */ 1052 if (amdgpu_dpm_read_sensor(adev, 1053 AMDGPU_PP_SENSOR_GFX_MCLK, 1054 (void *)&ui32, &ui32_size)) { 1055 return -EINVAL; 1056 } 1057 ui32 /= 100; 1058 break; 1059 case AMDGPU_INFO_SENSOR_GPU_TEMP: 1060 /* get temperature in millidegrees C */ 1061 if (amdgpu_dpm_read_sensor(adev, 1062 AMDGPU_PP_SENSOR_GPU_TEMP, 1063 (void *)&ui32, &ui32_size)) { 1064 return -EINVAL; 1065 } 1066 break; 1067 case AMDGPU_INFO_SENSOR_GPU_LOAD: 1068 /* get GPU load */ 1069 if (amdgpu_dpm_read_sensor(adev, 1070 AMDGPU_PP_SENSOR_GPU_LOAD, 1071 (void *)&ui32, &ui32_size)) { 1072 return -EINVAL; 1073 } 1074 break; 1075 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER: 1076 /* get average GPU power */ 1077 if (amdgpu_dpm_read_sensor(adev, 1078 AMDGPU_PP_SENSOR_GPU_AVG_POWER, 1079 (void *)&ui32, &ui32_size)) { 1080 return -EINVAL; 1081 } 1082 ui32 >>= 8; 1083 break; 1084 case AMDGPU_INFO_SENSOR_VDDNB: 1085 /* get VDDNB in millivolts */ 1086 if (amdgpu_dpm_read_sensor(adev, 1087 AMDGPU_PP_SENSOR_VDDNB, 1088 (void *)&ui32, &ui32_size)) { 1089 return -EINVAL; 1090 } 1091 break; 1092 case AMDGPU_INFO_SENSOR_VDDGFX: 1093 /* get VDDGFX in millivolts */ 1094 if (amdgpu_dpm_read_sensor(adev, 1095 AMDGPU_PP_SENSOR_VDDGFX, 1096 (void *)&ui32, &ui32_size)) { 1097 return -EINVAL; 1098 } 1099 break; 1100 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK: 1101 /* get stable pstate sclk in Mhz */ 1102 if (amdgpu_dpm_read_sensor(adev, 1103 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 1104 (void *)&ui32, &ui32_size)) { 1105 return -EINVAL; 1106 } 1107 ui32 /= 100; 1108 break; 1109 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK: 1110 /* get stable pstate mclk in Mhz */ 1111 if (amdgpu_dpm_read_sensor(adev, 1112 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 1113 (void *)&ui32, &ui32_size)) { 1114 return -EINVAL; 1115 } 1116 ui32 /= 100; 1117 break; 1118 case AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK: 1119 /* get peak pstate sclk in Mhz */ 1120 if (amdgpu_dpm_read_sensor(adev, 1121 AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK, 1122 (void *)&ui32, &ui32_size)) { 1123 return -EINVAL; 1124 } 1125 ui32 /= 100; 1126 break; 1127 case AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK: 1128 /* get peak pstate mclk in Mhz */ 1129 if (amdgpu_dpm_read_sensor(adev, 1130 AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK, 1131 (void *)&ui32, &ui32_size)) { 1132 return -EINVAL; 1133 } 1134 ui32 /= 100; 1135 break; 1136 default: 1137 DRM_DEBUG_KMS("Invalid request %d\n", 1138 info->sensor_info.type); 1139 return -EINVAL; 1140 } 1141 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 1142 } 1143 case AMDGPU_INFO_VRAM_LOST_COUNTER: 1144 ui32 = atomic_read(&adev->vram_lost_counter); 1145 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 1146 case AMDGPU_INFO_RAS_ENABLED_FEATURES: { 1147 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1148 uint64_t ras_mask; 1149 1150 if (!ras) 1151 return -EINVAL; 1152 ras_mask = (uint64_t)adev->ras_enabled << 32 | ras->features; 1153 1154 return copy_to_user(out, &ras_mask, 1155 min_t(u64, size, sizeof(ras_mask))) ? 1156 -EFAULT : 0; 1157 } 1158 case AMDGPU_INFO_VIDEO_CAPS: { 1159 const struct amdgpu_video_codecs *codecs; 1160 struct drm_amdgpu_info_video_caps *caps; 1161 int r; 1162 1163 if (!adev->asic_funcs->query_video_codecs) 1164 return -EINVAL; 1165 1166 switch (info->video_cap.type) { 1167 case AMDGPU_INFO_VIDEO_CAPS_DECODE: 1168 r = amdgpu_asic_query_video_codecs(adev, false, &codecs); 1169 if (r) 1170 return -EINVAL; 1171 break; 1172 case AMDGPU_INFO_VIDEO_CAPS_ENCODE: 1173 r = amdgpu_asic_query_video_codecs(adev, true, &codecs); 1174 if (r) 1175 return -EINVAL; 1176 break; 1177 default: 1178 DRM_DEBUG_KMS("Invalid request %d\n", 1179 info->video_cap.type); 1180 return -EINVAL; 1181 } 1182 1183 caps = kzalloc(sizeof(*caps), GFP_KERNEL); 1184 if (!caps) 1185 return -ENOMEM; 1186 1187 for (i = 0; i < codecs->codec_count; i++) { 1188 int idx = codecs->codec_array[i].codec_type; 1189 1190 switch (idx) { 1191 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2: 1192 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4: 1193 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1: 1194 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC: 1195 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC: 1196 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG: 1197 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9: 1198 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1: 1199 caps->codec_info[idx].valid = 1; 1200 caps->codec_info[idx].max_width = 1201 codecs->codec_array[i].max_width; 1202 caps->codec_info[idx].max_height = 1203 codecs->codec_array[i].max_height; 1204 caps->codec_info[idx].max_pixels_per_frame = 1205 codecs->codec_array[i].max_pixels_per_frame; 1206 caps->codec_info[idx].max_level = 1207 codecs->codec_array[i].max_level; 1208 break; 1209 default: 1210 break; 1211 } 1212 } 1213 r = copy_to_user(out, caps, 1214 min((size_t)size, sizeof(*caps))) ? -EFAULT : 0; 1215 kfree(caps); 1216 return r; 1217 } 1218 case AMDGPU_INFO_MAX_IBS: { 1219 uint32_t max_ibs[AMDGPU_HW_IP_NUM]; 1220 1221 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) 1222 max_ibs[i] = amdgpu_ring_max_ibs(i); 1223 1224 return copy_to_user(out, max_ibs, 1225 min((size_t)size, sizeof(max_ibs))) ? -EFAULT : 0; 1226 } 1227 default: 1228 DRM_DEBUG_KMS("Invalid request %d\n", info->query); 1229 return -EINVAL; 1230 } 1231 return 0; 1232 } 1233 1234 1235 /* 1236 * Outdated mess for old drm with Xorg being in charge (void function now). 1237 */ 1238 /** 1239 * amdgpu_driver_lastclose_kms - drm callback for last close 1240 * 1241 * @dev: drm dev pointer 1242 * 1243 * Switch vga_switcheroo state after last close (all asics). 1244 */ 1245 void amdgpu_driver_lastclose_kms(struct drm_device *dev) 1246 { 1247 drm_fb_helper_lastclose(dev); 1248 vga_switcheroo_process_delayed_switch(); 1249 } 1250 1251 /** 1252 * amdgpu_driver_open_kms - drm callback for open 1253 * 1254 * @dev: drm dev pointer 1255 * @file_priv: drm file 1256 * 1257 * On device open, init vm on cayman+ (all asics). 1258 * Returns 0 on success, error on failure. 1259 */ 1260 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 1261 { 1262 struct amdgpu_device *adev = drm_to_adev(dev); 1263 struct amdgpu_fpriv *fpriv; 1264 int r, pasid; 1265 1266 /* Ensure IB tests are run on ring */ 1267 flush_delayed_work(&adev->delayed_init_work); 1268 1269 1270 if (amdgpu_ras_intr_triggered()) { 1271 DRM_ERROR("RAS Intr triggered, device disabled!!"); 1272 return -EHWPOISON; 1273 } 1274 1275 file_priv->driver_priv = NULL; 1276 1277 r = pm_runtime_get_sync(dev->dev); 1278 if (r < 0) 1279 goto pm_put; 1280 1281 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 1282 if (unlikely(!fpriv)) { 1283 r = -ENOMEM; 1284 goto out_suspend; 1285 } 1286 1287 pasid = amdgpu_pasid_alloc(16); 1288 if (pasid < 0) { 1289 dev_warn(adev->dev, "No more PASIDs available!"); 1290 pasid = 0; 1291 } 1292 1293 r = amdgpu_xcp_open_device(adev, fpriv, file_priv); 1294 if (r) 1295 goto error_pasid; 1296 1297 r = amdgpu_vm_init(adev, &fpriv->vm, fpriv->xcp_id); 1298 if (r) 1299 goto error_pasid; 1300 1301 r = amdgpu_vm_set_pasid(adev, &fpriv->vm, pasid); 1302 if (r) 1303 goto error_vm; 1304 1305 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL); 1306 if (!fpriv->prt_va) { 1307 r = -ENOMEM; 1308 goto error_vm; 1309 } 1310 1311 if (adev->gfx.mcbp) { 1312 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK; 1313 1314 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj, 1315 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE); 1316 if (r) 1317 goto error_vm; 1318 } 1319 1320 mutex_init(&fpriv->bo_list_lock); 1321 idr_init_base(&fpriv->bo_list_handles, 1); 1322 1323 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr, adev); 1324 1325 file_priv->driver_priv = fpriv; 1326 goto out_suspend; 1327 1328 error_vm: 1329 amdgpu_vm_fini(adev, &fpriv->vm); 1330 1331 error_pasid: 1332 if (pasid) { 1333 amdgpu_pasid_free(pasid); 1334 amdgpu_vm_set_pasid(adev, &fpriv->vm, 0); 1335 } 1336 1337 kfree(fpriv); 1338 1339 out_suspend: 1340 pm_runtime_mark_last_busy(dev->dev); 1341 pm_put: 1342 pm_runtime_put_autosuspend(dev->dev); 1343 1344 return r; 1345 } 1346 1347 /** 1348 * amdgpu_driver_postclose_kms - drm callback for post close 1349 * 1350 * @dev: drm dev pointer 1351 * @file_priv: drm file 1352 * 1353 * On device post close, tear down vm on cayman+ (all asics). 1354 */ 1355 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1356 struct drm_file *file_priv) 1357 { 1358 struct amdgpu_device *adev = drm_to_adev(dev); 1359 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1360 struct amdgpu_bo_list *list; 1361 struct amdgpu_bo *pd; 1362 u32 pasid; 1363 int handle; 1364 1365 if (!fpriv) 1366 return; 1367 1368 pm_runtime_get_sync(dev->dev); 1369 1370 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL) 1371 amdgpu_uvd_free_handles(adev, file_priv); 1372 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL) 1373 amdgpu_vce_free_handles(adev, file_priv); 1374 1375 if (fpriv->csa_va) { 1376 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK; 1377 1378 WARN_ON(amdgpu_unmap_static_csa(adev, &fpriv->vm, adev->virt.csa_obj, 1379 fpriv->csa_va, csa_addr)); 1380 fpriv->csa_va = NULL; 1381 } 1382 1383 pasid = fpriv->vm.pasid; 1384 pd = amdgpu_bo_ref(fpriv->vm.root.bo); 1385 if (!WARN_ON(amdgpu_bo_reserve(pd, true))) { 1386 amdgpu_vm_bo_del(adev, fpriv->prt_va); 1387 amdgpu_bo_unreserve(pd); 1388 } 1389 1390 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); 1391 amdgpu_vm_fini(adev, &fpriv->vm); 1392 1393 if (pasid) 1394 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid); 1395 amdgpu_bo_unref(&pd); 1396 1397 idr_for_each_entry(&fpriv->bo_list_handles, list, handle) 1398 amdgpu_bo_list_put(list); 1399 1400 idr_destroy(&fpriv->bo_list_handles); 1401 mutex_destroy(&fpriv->bo_list_lock); 1402 1403 kfree(fpriv); 1404 file_priv->driver_priv = NULL; 1405 1406 pm_runtime_mark_last_busy(dev->dev); 1407 pm_runtime_put_autosuspend(dev->dev); 1408 } 1409 1410 1411 void amdgpu_driver_release_kms(struct drm_device *dev) 1412 { 1413 struct amdgpu_device *adev = drm_to_adev(dev); 1414 1415 amdgpu_device_fini_sw(adev); 1416 pci_set_drvdata(adev->pdev, NULL); 1417 } 1418 1419 /* 1420 * VBlank related functions. 1421 */ 1422 /** 1423 * amdgpu_get_vblank_counter_kms - get frame count 1424 * 1425 * @crtc: crtc to get the frame count from 1426 * 1427 * Gets the frame count on the requested crtc (all asics). 1428 * Returns frame count on success, -EINVAL on failure. 1429 */ 1430 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc) 1431 { 1432 struct drm_device *dev = crtc->dev; 1433 unsigned int pipe = crtc->index; 1434 struct amdgpu_device *adev = drm_to_adev(dev); 1435 int vpos, hpos, stat; 1436 u32 count; 1437 1438 if (pipe >= adev->mode_info.num_crtc) { 1439 DRM_ERROR("Invalid crtc %u\n", pipe); 1440 return -EINVAL; 1441 } 1442 1443 /* The hw increments its frame counter at start of vsync, not at start 1444 * of vblank, as is required by DRM core vblank counter handling. 1445 * Cook the hw count here to make it appear to the caller as if it 1446 * incremented at start of vblank. We measure distance to start of 1447 * vblank in vpos. vpos therefore will be >= 0 between start of vblank 1448 * and start of vsync, so vpos >= 0 means to bump the hw frame counter 1449 * result by 1 to give the proper appearance to caller. 1450 */ 1451 if (adev->mode_info.crtcs[pipe]) { 1452 /* Repeat readout if needed to provide stable result if 1453 * we cross start of vsync during the queries. 1454 */ 1455 do { 1456 count = amdgpu_display_vblank_get_counter(adev, pipe); 1457 /* Ask amdgpu_display_get_crtc_scanoutpos to return 1458 * vpos as distance to start of vblank, instead of 1459 * regular vertical scanout pos. 1460 */ 1461 stat = amdgpu_display_get_crtc_scanoutpos( 1462 dev, pipe, GET_DISTANCE_TO_VBLANKSTART, 1463 &vpos, &hpos, NULL, NULL, 1464 &adev->mode_info.crtcs[pipe]->base.hwmode); 1465 } while (count != amdgpu_display_vblank_get_counter(adev, pipe)); 1466 1467 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 1468 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 1469 DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 1470 } else { 1471 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", 1472 pipe, vpos); 1473 1474 /* Bump counter if we are at >= leading edge of vblank, 1475 * but before vsync where vpos would turn negative and 1476 * the hw counter really increments. 1477 */ 1478 if (vpos >= 0) 1479 count++; 1480 } 1481 } else { 1482 /* Fallback to use value as is. */ 1483 count = amdgpu_display_vblank_get_counter(adev, pipe); 1484 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 1485 } 1486 1487 return count; 1488 } 1489 1490 /** 1491 * amdgpu_enable_vblank_kms - enable vblank interrupt 1492 * 1493 * @crtc: crtc to enable vblank interrupt for 1494 * 1495 * Enable the interrupt on the requested crtc (all asics). 1496 * Returns 0 on success, -EINVAL on failure. 1497 */ 1498 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc) 1499 { 1500 struct drm_device *dev = crtc->dev; 1501 unsigned int pipe = crtc->index; 1502 struct amdgpu_device *adev = drm_to_adev(dev); 1503 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1504 1505 return amdgpu_irq_get(adev, &adev->crtc_irq, idx); 1506 } 1507 1508 /** 1509 * amdgpu_disable_vblank_kms - disable vblank interrupt 1510 * 1511 * @crtc: crtc to disable vblank interrupt for 1512 * 1513 * Disable the interrupt on the requested crtc (all asics). 1514 */ 1515 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc) 1516 { 1517 struct drm_device *dev = crtc->dev; 1518 unsigned int pipe = crtc->index; 1519 struct amdgpu_device *adev = drm_to_adev(dev); 1520 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1521 1522 amdgpu_irq_put(adev, &adev->crtc_irq, idx); 1523 } 1524 1525 /* 1526 * Debugfs info 1527 */ 1528 #if defined(CONFIG_DEBUG_FS) 1529 1530 static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused) 1531 { 1532 struct amdgpu_device *adev = m->private; 1533 struct drm_amdgpu_info_firmware fw_info; 1534 struct drm_amdgpu_query_fw query_fw; 1535 struct atom_context *ctx = adev->mode_info.atom_context; 1536 uint8_t smu_program, smu_major, smu_minor, smu_debug; 1537 int ret, i; 1538 1539 static const char *ta_fw_name[TA_FW_TYPE_MAX_INDEX] = { 1540 #define TA_FW_NAME(type)[TA_FW_TYPE_PSP_##type] = #type 1541 TA_FW_NAME(XGMI), 1542 TA_FW_NAME(RAS), 1543 TA_FW_NAME(HDCP), 1544 TA_FW_NAME(DTM), 1545 TA_FW_NAME(RAP), 1546 TA_FW_NAME(SECUREDISPLAY), 1547 #undef TA_FW_NAME 1548 }; 1549 1550 /* VCE */ 1551 query_fw.fw_type = AMDGPU_INFO_FW_VCE; 1552 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1553 if (ret) 1554 return ret; 1555 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n", 1556 fw_info.feature, fw_info.ver); 1557 1558 /* UVD */ 1559 query_fw.fw_type = AMDGPU_INFO_FW_UVD; 1560 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1561 if (ret) 1562 return ret; 1563 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n", 1564 fw_info.feature, fw_info.ver); 1565 1566 /* GMC */ 1567 query_fw.fw_type = AMDGPU_INFO_FW_GMC; 1568 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1569 if (ret) 1570 return ret; 1571 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n", 1572 fw_info.feature, fw_info.ver); 1573 1574 /* ME */ 1575 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME; 1576 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1577 if (ret) 1578 return ret; 1579 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n", 1580 fw_info.feature, fw_info.ver); 1581 1582 /* PFP */ 1583 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP; 1584 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1585 if (ret) 1586 return ret; 1587 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n", 1588 fw_info.feature, fw_info.ver); 1589 1590 /* CE */ 1591 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE; 1592 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1593 if (ret) 1594 return ret; 1595 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n", 1596 fw_info.feature, fw_info.ver); 1597 1598 /* RLC */ 1599 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC; 1600 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1601 if (ret) 1602 return ret; 1603 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n", 1604 fw_info.feature, fw_info.ver); 1605 1606 /* RLC SAVE RESTORE LIST CNTL */ 1607 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL; 1608 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1609 if (ret) 1610 return ret; 1611 seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n", 1612 fw_info.feature, fw_info.ver); 1613 1614 /* RLC SAVE RESTORE LIST GPM MEM */ 1615 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM; 1616 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1617 if (ret) 1618 return ret; 1619 seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n", 1620 fw_info.feature, fw_info.ver); 1621 1622 /* RLC SAVE RESTORE LIST SRM MEM */ 1623 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM; 1624 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1625 if (ret) 1626 return ret; 1627 seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n", 1628 fw_info.feature, fw_info.ver); 1629 1630 /* RLCP */ 1631 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCP; 1632 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1633 if (ret) 1634 return ret; 1635 seq_printf(m, "RLCP feature version: %u, firmware version: 0x%08x\n", 1636 fw_info.feature, fw_info.ver); 1637 1638 /* RLCV */ 1639 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCV; 1640 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1641 if (ret) 1642 return ret; 1643 seq_printf(m, "RLCV feature version: %u, firmware version: 0x%08x\n", 1644 fw_info.feature, fw_info.ver); 1645 1646 /* MEC */ 1647 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC; 1648 query_fw.index = 0; 1649 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1650 if (ret) 1651 return ret; 1652 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n", 1653 fw_info.feature, fw_info.ver); 1654 1655 /* MEC2 */ 1656 if (adev->gfx.mec2_fw) { 1657 query_fw.index = 1; 1658 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1659 if (ret) 1660 return ret; 1661 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n", 1662 fw_info.feature, fw_info.ver); 1663 } 1664 1665 /* IMU */ 1666 query_fw.fw_type = AMDGPU_INFO_FW_IMU; 1667 query_fw.index = 0; 1668 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1669 if (ret) 1670 return ret; 1671 seq_printf(m, "IMU feature version: %u, firmware version: 0x%08x\n", 1672 fw_info.feature, fw_info.ver); 1673 1674 /* PSP SOS */ 1675 query_fw.fw_type = AMDGPU_INFO_FW_SOS; 1676 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1677 if (ret) 1678 return ret; 1679 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n", 1680 fw_info.feature, fw_info.ver); 1681 1682 1683 /* PSP ASD */ 1684 query_fw.fw_type = AMDGPU_INFO_FW_ASD; 1685 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1686 if (ret) 1687 return ret; 1688 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n", 1689 fw_info.feature, fw_info.ver); 1690 1691 query_fw.fw_type = AMDGPU_INFO_FW_TA; 1692 for (i = TA_FW_TYPE_PSP_XGMI; i < TA_FW_TYPE_MAX_INDEX; i++) { 1693 query_fw.index = i; 1694 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1695 if (ret) 1696 continue; 1697 1698 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n", 1699 ta_fw_name[i], fw_info.feature, fw_info.ver); 1700 } 1701 1702 /* SMC */ 1703 query_fw.fw_type = AMDGPU_INFO_FW_SMC; 1704 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1705 if (ret) 1706 return ret; 1707 smu_program = (fw_info.ver >> 24) & 0xff; 1708 smu_major = (fw_info.ver >> 16) & 0xff; 1709 smu_minor = (fw_info.ver >> 8) & 0xff; 1710 smu_debug = (fw_info.ver >> 0) & 0xff; 1711 seq_printf(m, "SMC feature version: %u, program: %d, firmware version: 0x%08x (%d.%d.%d)\n", 1712 fw_info.feature, smu_program, fw_info.ver, smu_major, smu_minor, smu_debug); 1713 1714 /* SDMA */ 1715 query_fw.fw_type = AMDGPU_INFO_FW_SDMA; 1716 for (i = 0; i < adev->sdma.num_instances; i++) { 1717 query_fw.index = i; 1718 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1719 if (ret) 1720 return ret; 1721 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n", 1722 i, fw_info.feature, fw_info.ver); 1723 } 1724 1725 /* VCN */ 1726 query_fw.fw_type = AMDGPU_INFO_FW_VCN; 1727 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1728 if (ret) 1729 return ret; 1730 seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n", 1731 fw_info.feature, fw_info.ver); 1732 1733 /* DMCU */ 1734 query_fw.fw_type = AMDGPU_INFO_FW_DMCU; 1735 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1736 if (ret) 1737 return ret; 1738 seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n", 1739 fw_info.feature, fw_info.ver); 1740 1741 /* DMCUB */ 1742 query_fw.fw_type = AMDGPU_INFO_FW_DMCUB; 1743 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1744 if (ret) 1745 return ret; 1746 seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n", 1747 fw_info.feature, fw_info.ver); 1748 1749 /* TOC */ 1750 query_fw.fw_type = AMDGPU_INFO_FW_TOC; 1751 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1752 if (ret) 1753 return ret; 1754 seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n", 1755 fw_info.feature, fw_info.ver); 1756 1757 /* CAP */ 1758 if (adev->psp.cap_fw) { 1759 query_fw.fw_type = AMDGPU_INFO_FW_CAP; 1760 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1761 if (ret) 1762 return ret; 1763 seq_printf(m, "CAP feature version: %u, firmware version: 0x%08x\n", 1764 fw_info.feature, fw_info.ver); 1765 } 1766 1767 /* MES_KIQ */ 1768 query_fw.fw_type = AMDGPU_INFO_FW_MES_KIQ; 1769 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1770 if (ret) 1771 return ret; 1772 seq_printf(m, "MES_KIQ feature version: %u, firmware version: 0x%08x\n", 1773 fw_info.feature, fw_info.ver); 1774 1775 /* MES */ 1776 query_fw.fw_type = AMDGPU_INFO_FW_MES; 1777 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1778 if (ret) 1779 return ret; 1780 seq_printf(m, "MES feature version: %u, firmware version: 0x%08x\n", 1781 fw_info.feature, fw_info.ver); 1782 1783 /* VPE */ 1784 query_fw.fw_type = AMDGPU_INFO_FW_VPE; 1785 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1786 if (ret) 1787 return ret; 1788 seq_printf(m, "VPE feature version: %u, firmware version: 0x%08x\n", 1789 fw_info.feature, fw_info.ver); 1790 1791 seq_printf(m, "VBIOS version: %s\n", ctx->vbios_pn); 1792 1793 return 0; 1794 } 1795 1796 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_firmware_info); 1797 1798 #endif 1799 1800 void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev) 1801 { 1802 #if defined(CONFIG_DEBUG_FS) 1803 struct drm_minor *minor = adev_to_drm(adev)->primary; 1804 struct dentry *root = minor->debugfs_root; 1805 1806 debugfs_create_file("amdgpu_firmware_info", 0444, root, 1807 adev, &amdgpu_debugfs_firmware_info_fops); 1808 1809 #endif 1810 } 1811