1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include "amdgpu.h" 30 #include <drm/drm_debugfs.h> 31 #include <drm/amdgpu_drm.h> 32 #include "amdgpu_uvd.h" 33 #include "amdgpu_vce.h" 34 #include "atom.h" 35 36 #include <linux/vga_switcheroo.h> 37 #include <linux/slab.h> 38 #include <linux/uaccess.h> 39 #include <linux/pci.h> 40 #include <linux/pm_runtime.h> 41 #include "amdgpu_amdkfd.h" 42 #include "amdgpu_gem.h" 43 #include "amdgpu_display.h" 44 #include "amdgpu_ras.h" 45 46 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev) 47 { 48 struct amdgpu_gpu_instance *gpu_instance; 49 int i; 50 51 mutex_lock(&mgpu_info.mutex); 52 53 for (i = 0; i < mgpu_info.num_gpu; i++) { 54 gpu_instance = &(mgpu_info.gpu_ins[i]); 55 if (gpu_instance->adev == adev) { 56 mgpu_info.gpu_ins[i] = 57 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1]; 58 mgpu_info.num_gpu--; 59 if (adev->flags & AMD_IS_APU) 60 mgpu_info.num_apu--; 61 else 62 mgpu_info.num_dgpu--; 63 break; 64 } 65 } 66 67 mutex_unlock(&mgpu_info.mutex); 68 } 69 70 /** 71 * amdgpu_driver_unload_kms - Main unload function for KMS. 72 * 73 * @dev: drm dev pointer 74 * 75 * This is the main unload function for KMS (all asics). 76 * Returns 0 on success. 77 */ 78 void amdgpu_driver_unload_kms(struct drm_device *dev) 79 { 80 struct amdgpu_device *adev = drm_to_adev(dev); 81 82 if (adev == NULL) 83 return; 84 85 amdgpu_unregister_gpu_instance(adev); 86 87 if (adev->rmmio == NULL) 88 return; 89 90 if (adev->runpm) { 91 pm_runtime_get_sync(dev->dev); 92 pm_runtime_forbid(dev->dev); 93 } 94 95 amdgpu_acpi_fini(adev); 96 amdgpu_device_fini(adev); 97 } 98 99 void amdgpu_register_gpu_instance(struct amdgpu_device *adev) 100 { 101 struct amdgpu_gpu_instance *gpu_instance; 102 103 mutex_lock(&mgpu_info.mutex); 104 105 if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) { 106 DRM_ERROR("Cannot register more gpu instance\n"); 107 mutex_unlock(&mgpu_info.mutex); 108 return; 109 } 110 111 gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]); 112 gpu_instance->adev = adev; 113 gpu_instance->mgpu_fan_enabled = 0; 114 115 mgpu_info.num_gpu++; 116 if (adev->flags & AMD_IS_APU) 117 mgpu_info.num_apu++; 118 else 119 mgpu_info.num_dgpu++; 120 121 mutex_unlock(&mgpu_info.mutex); 122 } 123 124 /** 125 * amdgpu_driver_load_kms - Main load function for KMS. 126 * 127 * @adev: pointer to struct amdgpu_device 128 * @flags: device flags 129 * 130 * This is the main load function for KMS (all asics). 131 * Returns 0 on success, error on failure. 132 */ 133 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags) 134 { 135 struct drm_device *dev; 136 struct pci_dev *parent; 137 int r, acpi_status; 138 139 dev = adev_to_drm(adev); 140 141 if (amdgpu_has_atpx() && 142 (amdgpu_is_atpx_hybrid() || 143 amdgpu_has_atpx_dgpu_power_cntl()) && 144 ((flags & AMD_IS_APU) == 0) && 145 !pci_is_thunderbolt_attached(dev->pdev)) 146 flags |= AMD_IS_PX; 147 148 parent = pci_upstream_bridge(adev->pdev); 149 adev->has_pr3 = parent ? pci_pr3_present(parent) : false; 150 151 /* amdgpu_device_init should report only fatal error 152 * like memory allocation failure or iomapping failure, 153 * or memory manager initialization failure, it must 154 * properly initialize the GPU MC controller and permit 155 * VRAM allocation 156 */ 157 r = amdgpu_device_init(adev, flags); 158 if (r) { 159 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); 160 goto out; 161 } 162 163 if (amdgpu_device_supports_atpx(dev) && 164 (amdgpu_runtime_pm != 0)) { /* enable runpm by default for atpx */ 165 adev->runpm = true; 166 dev_info(adev->dev, "Using ATPX for runtime pm\n"); 167 } else if (amdgpu_device_supports_boco(dev) && 168 (amdgpu_runtime_pm != 0)) { /* enable runpm by default for boco */ 169 adev->runpm = true; 170 dev_info(adev->dev, "Using BOCO for runtime pm\n"); 171 } else if (amdgpu_device_supports_baco(dev) && 172 (amdgpu_runtime_pm != 0)) { 173 switch (adev->asic_type) { 174 case CHIP_VEGA20: 175 case CHIP_ARCTURUS: 176 case CHIP_SIENNA_CICHLID: 177 case CHIP_NAVY_FLOUNDER: 178 /* enable runpm if runpm=1 */ 179 if (amdgpu_runtime_pm > 0) 180 adev->runpm = true; 181 break; 182 case CHIP_VEGA10: 183 /* turn runpm on if noretry=0 */ 184 if (!adev->gmc.noretry) 185 adev->runpm = true; 186 break; 187 default: 188 /* enable runpm on CI+ */ 189 adev->runpm = true; 190 break; 191 } 192 if (adev->runpm) 193 dev_info(adev->dev, "Using BACO for runtime pm\n"); 194 } 195 196 /* Call ACPI methods: require modeset init 197 * but failure is not fatal 198 */ 199 200 acpi_status = amdgpu_acpi_init(adev); 201 if (acpi_status) 202 dev_dbg(&dev->pdev->dev, "Error during ACPI methods call\n"); 203 204 if (adev->runpm) { 205 /* only need to skip on ATPX */ 206 if (amdgpu_device_supports_atpx(dev) && 207 !amdgpu_is_atpx_hybrid()) 208 dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 209 pm_runtime_use_autosuspend(dev->dev); 210 pm_runtime_set_autosuspend_delay(dev->dev, 5000); 211 pm_runtime_allow(dev->dev); 212 pm_runtime_mark_last_busy(dev->dev); 213 pm_runtime_put_autosuspend(dev->dev); 214 } 215 216 out: 217 if (r) { 218 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */ 219 if (adev->rmmio && adev->runpm) 220 pm_runtime_put_noidle(dev->dev); 221 amdgpu_driver_unload_kms(dev); 222 } 223 224 return r; 225 } 226 227 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, 228 struct drm_amdgpu_query_fw *query_fw, 229 struct amdgpu_device *adev) 230 { 231 switch (query_fw->fw_type) { 232 case AMDGPU_INFO_FW_VCE: 233 fw_info->ver = adev->vce.fw_version; 234 fw_info->feature = adev->vce.fb_version; 235 break; 236 case AMDGPU_INFO_FW_UVD: 237 fw_info->ver = adev->uvd.fw_version; 238 fw_info->feature = 0; 239 break; 240 case AMDGPU_INFO_FW_VCN: 241 fw_info->ver = adev->vcn.fw_version; 242 fw_info->feature = 0; 243 break; 244 case AMDGPU_INFO_FW_GMC: 245 fw_info->ver = adev->gmc.fw_version; 246 fw_info->feature = 0; 247 break; 248 case AMDGPU_INFO_FW_GFX_ME: 249 fw_info->ver = adev->gfx.me_fw_version; 250 fw_info->feature = adev->gfx.me_feature_version; 251 break; 252 case AMDGPU_INFO_FW_GFX_PFP: 253 fw_info->ver = adev->gfx.pfp_fw_version; 254 fw_info->feature = adev->gfx.pfp_feature_version; 255 break; 256 case AMDGPU_INFO_FW_GFX_CE: 257 fw_info->ver = adev->gfx.ce_fw_version; 258 fw_info->feature = adev->gfx.ce_feature_version; 259 break; 260 case AMDGPU_INFO_FW_GFX_RLC: 261 fw_info->ver = adev->gfx.rlc_fw_version; 262 fw_info->feature = adev->gfx.rlc_feature_version; 263 break; 264 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL: 265 fw_info->ver = adev->gfx.rlc_srlc_fw_version; 266 fw_info->feature = adev->gfx.rlc_srlc_feature_version; 267 break; 268 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM: 269 fw_info->ver = adev->gfx.rlc_srlg_fw_version; 270 fw_info->feature = adev->gfx.rlc_srlg_feature_version; 271 break; 272 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM: 273 fw_info->ver = adev->gfx.rlc_srls_fw_version; 274 fw_info->feature = adev->gfx.rlc_srls_feature_version; 275 break; 276 case AMDGPU_INFO_FW_GFX_MEC: 277 if (query_fw->index == 0) { 278 fw_info->ver = adev->gfx.mec_fw_version; 279 fw_info->feature = adev->gfx.mec_feature_version; 280 } else if (query_fw->index == 1) { 281 fw_info->ver = adev->gfx.mec2_fw_version; 282 fw_info->feature = adev->gfx.mec2_feature_version; 283 } else 284 return -EINVAL; 285 break; 286 case AMDGPU_INFO_FW_SMC: 287 fw_info->ver = adev->pm.fw_version; 288 fw_info->feature = 0; 289 break; 290 case AMDGPU_INFO_FW_TA: 291 switch (query_fw->index) { 292 case 0: 293 fw_info->ver = adev->psp.ta_fw_version; 294 fw_info->feature = adev->psp.ta_xgmi_ucode_version; 295 break; 296 case 1: 297 fw_info->ver = adev->psp.ta_fw_version; 298 fw_info->feature = adev->psp.ta_ras_ucode_version; 299 break; 300 case 2: 301 fw_info->ver = adev->psp.ta_fw_version; 302 fw_info->feature = adev->psp.ta_hdcp_ucode_version; 303 break; 304 case 3: 305 fw_info->ver = adev->psp.ta_fw_version; 306 fw_info->feature = adev->psp.ta_dtm_ucode_version; 307 break; 308 default: 309 return -EINVAL; 310 } 311 break; 312 case AMDGPU_INFO_FW_SDMA: 313 if (query_fw->index >= adev->sdma.num_instances) 314 return -EINVAL; 315 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version; 316 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version; 317 break; 318 case AMDGPU_INFO_FW_SOS: 319 fw_info->ver = adev->psp.sos_fw_version; 320 fw_info->feature = adev->psp.sos_feature_version; 321 break; 322 case AMDGPU_INFO_FW_ASD: 323 fw_info->ver = adev->psp.asd_fw_version; 324 fw_info->feature = adev->psp.asd_feature_version; 325 break; 326 case AMDGPU_INFO_FW_DMCU: 327 fw_info->ver = adev->dm.dmcu_fw_version; 328 fw_info->feature = 0; 329 break; 330 case AMDGPU_INFO_FW_DMCUB: 331 fw_info->ver = adev->dm.dmcub_fw_version; 332 fw_info->feature = 0; 333 break; 334 case AMDGPU_INFO_FW_TOC: 335 fw_info->ver = adev->psp.toc_fw_version; 336 fw_info->feature = adev->psp.toc_feature_version; 337 break; 338 default: 339 return -EINVAL; 340 } 341 return 0; 342 } 343 344 static int amdgpu_hw_ip_info(struct amdgpu_device *adev, 345 struct drm_amdgpu_info *info, 346 struct drm_amdgpu_info_hw_ip *result) 347 { 348 uint32_t ib_start_alignment = 0; 349 uint32_t ib_size_alignment = 0; 350 enum amd_ip_block_type type; 351 unsigned int num_rings = 0; 352 unsigned int i, j; 353 354 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 355 return -EINVAL; 356 357 switch (info->query_hw_ip.type) { 358 case AMDGPU_HW_IP_GFX: 359 type = AMD_IP_BLOCK_TYPE_GFX; 360 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 361 if (adev->gfx.gfx_ring[i].sched.ready) 362 ++num_rings; 363 ib_start_alignment = 32; 364 ib_size_alignment = 32; 365 break; 366 case AMDGPU_HW_IP_COMPUTE: 367 type = AMD_IP_BLOCK_TYPE_GFX; 368 for (i = 0; i < adev->gfx.num_compute_rings; i++) 369 if (adev->gfx.compute_ring[i].sched.ready) 370 ++num_rings; 371 ib_start_alignment = 32; 372 ib_size_alignment = 32; 373 break; 374 case AMDGPU_HW_IP_DMA: 375 type = AMD_IP_BLOCK_TYPE_SDMA; 376 for (i = 0; i < adev->sdma.num_instances; i++) 377 if (adev->sdma.instance[i].ring.sched.ready) 378 ++num_rings; 379 ib_start_alignment = 256; 380 ib_size_alignment = 4; 381 break; 382 case AMDGPU_HW_IP_UVD: 383 type = AMD_IP_BLOCK_TYPE_UVD; 384 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 385 if (adev->uvd.harvest_config & (1 << i)) 386 continue; 387 388 if (adev->uvd.inst[i].ring.sched.ready) 389 ++num_rings; 390 } 391 ib_start_alignment = 64; 392 ib_size_alignment = 64; 393 break; 394 case AMDGPU_HW_IP_VCE: 395 type = AMD_IP_BLOCK_TYPE_VCE; 396 for (i = 0; i < adev->vce.num_rings; i++) 397 if (adev->vce.ring[i].sched.ready) 398 ++num_rings; 399 ib_start_alignment = 4; 400 ib_size_alignment = 1; 401 break; 402 case AMDGPU_HW_IP_UVD_ENC: 403 type = AMD_IP_BLOCK_TYPE_UVD; 404 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 405 if (adev->uvd.harvest_config & (1 << i)) 406 continue; 407 408 for (j = 0; j < adev->uvd.num_enc_rings; j++) 409 if (adev->uvd.inst[i].ring_enc[j].sched.ready) 410 ++num_rings; 411 } 412 ib_start_alignment = 64; 413 ib_size_alignment = 64; 414 break; 415 case AMDGPU_HW_IP_VCN_DEC: 416 type = AMD_IP_BLOCK_TYPE_VCN; 417 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 418 if (adev->uvd.harvest_config & (1 << i)) 419 continue; 420 421 if (adev->vcn.inst[i].ring_dec.sched.ready) 422 ++num_rings; 423 } 424 ib_start_alignment = 16; 425 ib_size_alignment = 16; 426 break; 427 case AMDGPU_HW_IP_VCN_ENC: 428 type = AMD_IP_BLOCK_TYPE_VCN; 429 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 430 if (adev->uvd.harvest_config & (1 << i)) 431 continue; 432 433 for (j = 0; j < adev->vcn.num_enc_rings; j++) 434 if (adev->vcn.inst[i].ring_enc[j].sched.ready) 435 ++num_rings; 436 } 437 ib_start_alignment = 64; 438 ib_size_alignment = 1; 439 break; 440 case AMDGPU_HW_IP_VCN_JPEG: 441 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 442 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 443 444 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { 445 if (adev->jpeg.harvest_config & (1 << i)) 446 continue; 447 448 if (adev->jpeg.inst[i].ring_dec.sched.ready) 449 ++num_rings; 450 } 451 ib_start_alignment = 16; 452 ib_size_alignment = 16; 453 break; 454 default: 455 return -EINVAL; 456 } 457 458 for (i = 0; i < adev->num_ip_blocks; i++) 459 if (adev->ip_blocks[i].version->type == type && 460 adev->ip_blocks[i].status.valid) 461 break; 462 463 if (i == adev->num_ip_blocks) 464 return 0; 465 466 num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type], 467 num_rings); 468 469 result->hw_ip_version_major = adev->ip_blocks[i].version->major; 470 result->hw_ip_version_minor = adev->ip_blocks[i].version->minor; 471 result->capabilities_flags = 0; 472 result->available_rings = (1 << num_rings) - 1; 473 result->ib_start_alignment = ib_start_alignment; 474 result->ib_size_alignment = ib_size_alignment; 475 return 0; 476 } 477 478 /* 479 * Userspace get information ioctl 480 */ 481 /** 482 * amdgpu_info_ioctl - answer a device specific request. 483 * 484 * @dev: drm device pointer 485 * @data: request object 486 * @filp: drm filp 487 * 488 * This function is used to pass device specific parameters to the userspace 489 * drivers. Examples include: pci device id, pipeline parms, tiling params, 490 * etc. (all asics). 491 * Returns 0 on success, -EINVAL on failure. 492 */ 493 int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 494 { 495 struct amdgpu_device *adev = drm_to_adev(dev); 496 struct drm_amdgpu_info *info = data; 497 struct amdgpu_mode_info *minfo = &adev->mode_info; 498 void __user *out = (void __user *)(uintptr_t)info->return_pointer; 499 uint32_t size = info->return_size; 500 struct drm_crtc *crtc; 501 uint32_t ui32 = 0; 502 uint64_t ui64 = 0; 503 int i, found; 504 int ui32_size = sizeof(ui32); 505 506 if (!info->return_size || !info->return_pointer) 507 return -EINVAL; 508 509 switch (info->query) { 510 case AMDGPU_INFO_ACCEL_WORKING: 511 ui32 = adev->accel_working; 512 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 513 case AMDGPU_INFO_CRTC_FROM_ID: 514 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { 515 crtc = (struct drm_crtc *)minfo->crtcs[i]; 516 if (crtc && crtc->base.id == info->mode_crtc.id) { 517 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 518 ui32 = amdgpu_crtc->crtc_id; 519 found = 1; 520 break; 521 } 522 } 523 if (!found) { 524 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); 525 return -EINVAL; 526 } 527 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 528 case AMDGPU_INFO_HW_IP_INFO: { 529 struct drm_amdgpu_info_hw_ip ip = {}; 530 int ret; 531 532 ret = amdgpu_hw_ip_info(adev, info, &ip); 533 if (ret) 534 return ret; 535 536 ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip))); 537 return ret ? -EFAULT : 0; 538 } 539 case AMDGPU_INFO_HW_IP_COUNT: { 540 enum amd_ip_block_type type; 541 uint32_t count = 0; 542 543 switch (info->query_hw_ip.type) { 544 case AMDGPU_HW_IP_GFX: 545 type = AMD_IP_BLOCK_TYPE_GFX; 546 break; 547 case AMDGPU_HW_IP_COMPUTE: 548 type = AMD_IP_BLOCK_TYPE_GFX; 549 break; 550 case AMDGPU_HW_IP_DMA: 551 type = AMD_IP_BLOCK_TYPE_SDMA; 552 break; 553 case AMDGPU_HW_IP_UVD: 554 type = AMD_IP_BLOCK_TYPE_UVD; 555 break; 556 case AMDGPU_HW_IP_VCE: 557 type = AMD_IP_BLOCK_TYPE_VCE; 558 break; 559 case AMDGPU_HW_IP_UVD_ENC: 560 type = AMD_IP_BLOCK_TYPE_UVD; 561 break; 562 case AMDGPU_HW_IP_VCN_DEC: 563 case AMDGPU_HW_IP_VCN_ENC: 564 type = AMD_IP_BLOCK_TYPE_VCN; 565 break; 566 case AMDGPU_HW_IP_VCN_JPEG: 567 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 568 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 569 break; 570 default: 571 return -EINVAL; 572 } 573 574 for (i = 0; i < adev->num_ip_blocks; i++) 575 if (adev->ip_blocks[i].version->type == type && 576 adev->ip_blocks[i].status.valid && 577 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 578 count++; 579 580 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; 581 } 582 case AMDGPU_INFO_TIMESTAMP: 583 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev); 584 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 585 case AMDGPU_INFO_FW_VERSION: { 586 struct drm_amdgpu_info_firmware fw_info; 587 int ret; 588 589 /* We only support one instance of each IP block right now. */ 590 if (info->query_fw.ip_instance != 0) 591 return -EINVAL; 592 593 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev); 594 if (ret) 595 return ret; 596 597 return copy_to_user(out, &fw_info, 598 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0; 599 } 600 case AMDGPU_INFO_NUM_BYTES_MOVED: 601 ui64 = atomic64_read(&adev->num_bytes_moved); 602 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 603 case AMDGPU_INFO_NUM_EVICTIONS: 604 ui64 = atomic64_read(&adev->num_evictions); 605 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 606 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS: 607 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults); 608 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 609 case AMDGPU_INFO_VRAM_USAGE: 610 ui64 = amdgpu_vram_mgr_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM)); 611 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 612 case AMDGPU_INFO_VIS_VRAM_USAGE: 613 ui64 = amdgpu_vram_mgr_vis_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM)); 614 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 615 case AMDGPU_INFO_GTT_USAGE: 616 ui64 = amdgpu_gtt_mgr_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)); 617 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 618 case AMDGPU_INFO_GDS_CONFIG: { 619 struct drm_amdgpu_info_gds gds_info; 620 621 memset(&gds_info, 0, sizeof(gds_info)); 622 gds_info.compute_partition_size = adev->gds.gds_size; 623 gds_info.gds_total_size = adev->gds.gds_size; 624 gds_info.gws_per_compute_partition = adev->gds.gws_size; 625 gds_info.oa_per_compute_partition = adev->gds.oa_size; 626 return copy_to_user(out, &gds_info, 627 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0; 628 } 629 case AMDGPU_INFO_VRAM_GTT: { 630 struct drm_amdgpu_info_vram_gtt vram_gtt; 631 632 vram_gtt.vram_size = adev->gmc.real_vram_size - 633 atomic64_read(&adev->vram_pin_size) - 634 AMDGPU_VM_RESERVED_VRAM; 635 vram_gtt.vram_cpu_accessible_size = 636 min(adev->gmc.visible_vram_size - 637 atomic64_read(&adev->visible_pin_size), 638 vram_gtt.vram_size); 639 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size; 640 vram_gtt.gtt_size *= PAGE_SIZE; 641 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size); 642 return copy_to_user(out, &vram_gtt, 643 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; 644 } 645 case AMDGPU_INFO_MEMORY: { 646 struct drm_amdgpu_memory_info mem; 647 struct ttm_resource_manager *vram_man = 648 ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); 649 struct ttm_resource_manager *gtt_man = 650 ttm_manager_type(&adev->mman.bdev, TTM_PL_TT); 651 memset(&mem, 0, sizeof(mem)); 652 mem.vram.total_heap_size = adev->gmc.real_vram_size; 653 mem.vram.usable_heap_size = adev->gmc.real_vram_size - 654 atomic64_read(&adev->vram_pin_size) - 655 AMDGPU_VM_RESERVED_VRAM; 656 mem.vram.heap_usage = 657 amdgpu_vram_mgr_usage(vram_man); 658 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4; 659 660 mem.cpu_accessible_vram.total_heap_size = 661 adev->gmc.visible_vram_size; 662 mem.cpu_accessible_vram.usable_heap_size = 663 min(adev->gmc.visible_vram_size - 664 atomic64_read(&adev->visible_pin_size), 665 mem.vram.usable_heap_size); 666 mem.cpu_accessible_vram.heap_usage = 667 amdgpu_vram_mgr_vis_usage(vram_man); 668 mem.cpu_accessible_vram.max_allocation = 669 mem.cpu_accessible_vram.usable_heap_size * 3 / 4; 670 671 mem.gtt.total_heap_size = gtt_man->size; 672 mem.gtt.total_heap_size *= PAGE_SIZE; 673 mem.gtt.usable_heap_size = mem.gtt.total_heap_size - 674 atomic64_read(&adev->gart_pin_size); 675 mem.gtt.heap_usage = 676 amdgpu_gtt_mgr_usage(gtt_man); 677 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4; 678 679 return copy_to_user(out, &mem, 680 min((size_t)size, sizeof(mem))) 681 ? -EFAULT : 0; 682 } 683 case AMDGPU_INFO_READ_MMR_REG: { 684 unsigned n, alloc_size; 685 uint32_t *regs; 686 unsigned se_num = (info->read_mmr_reg.instance >> 687 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & 688 AMDGPU_INFO_MMR_SE_INDEX_MASK; 689 unsigned sh_num = (info->read_mmr_reg.instance >> 690 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & 691 AMDGPU_INFO_MMR_SH_INDEX_MASK; 692 693 /* set full masks if the userspace set all bits 694 * in the bitfields */ 695 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) 696 se_num = 0xffffffff; 697 else if (se_num >= AMDGPU_GFX_MAX_SE) 698 return -EINVAL; 699 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) 700 sh_num = 0xffffffff; 701 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE) 702 return -EINVAL; 703 704 if (info->read_mmr_reg.count > 128) 705 return -EINVAL; 706 707 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL); 708 if (!regs) 709 return -ENOMEM; 710 alloc_size = info->read_mmr_reg.count * sizeof(*regs); 711 712 amdgpu_gfx_off_ctrl(adev, false); 713 for (i = 0; i < info->read_mmr_reg.count; i++) { 714 if (amdgpu_asic_read_register(adev, se_num, sh_num, 715 info->read_mmr_reg.dword_offset + i, 716 ®s[i])) { 717 DRM_DEBUG_KMS("unallowed offset %#x\n", 718 info->read_mmr_reg.dword_offset + i); 719 kfree(regs); 720 amdgpu_gfx_off_ctrl(adev, true); 721 return -EFAULT; 722 } 723 } 724 amdgpu_gfx_off_ctrl(adev, true); 725 n = copy_to_user(out, regs, min(size, alloc_size)); 726 kfree(regs); 727 return n ? -EFAULT : 0; 728 } 729 case AMDGPU_INFO_DEV_INFO: { 730 struct drm_amdgpu_info_device *dev_info; 731 uint64_t vm_size; 732 int ret; 733 734 dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL); 735 if (!dev_info) 736 return -ENOMEM; 737 738 dev_info->device_id = dev->pdev->device; 739 dev_info->chip_rev = adev->rev_id; 740 dev_info->external_rev = adev->external_rev_id; 741 dev_info->pci_rev = dev->pdev->revision; 742 dev_info->family = adev->family; 743 dev_info->num_shader_engines = adev->gfx.config.max_shader_engines; 744 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 745 /* return all clocks in KHz */ 746 dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; 747 if (adev->pm.dpm_enabled) { 748 dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10; 749 dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10; 750 } else { 751 dev_info->max_engine_clock = adev->clock.default_sclk * 10; 752 dev_info->max_memory_clock = adev->clock.default_mclk * 10; 753 } 754 dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; 755 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se * 756 adev->gfx.config.max_shader_engines; 757 dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; 758 dev_info->_pad = 0; 759 dev_info->ids_flags = 0; 760 if (adev->flags & AMD_IS_APU) 761 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION; 762 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) 763 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION; 764 if (amdgpu_is_tmz(adev)) 765 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ; 766 767 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 768 vm_size -= AMDGPU_VA_RESERVED_SIZE; 769 770 /* Older VCE FW versions are buggy and can handle only 40bits */ 771 if (adev->vce.fw_version && 772 adev->vce.fw_version < AMDGPU_VCE_FW_53_45) 773 vm_size = min(vm_size, 1ULL << 40); 774 775 dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_SIZE; 776 dev_info->virtual_address_max = 777 min(vm_size, AMDGPU_GMC_HOLE_START); 778 779 if (vm_size > AMDGPU_GMC_HOLE_START) { 780 dev_info->high_va_offset = AMDGPU_GMC_HOLE_END; 781 dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size; 782 } 783 dev_info->virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 784 dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE; 785 dev_info->gart_page_size = AMDGPU_GPU_PAGE_SIZE; 786 dev_info->cu_active_number = adev->gfx.cu_info.number; 787 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; 788 dev_info->ce_ram_size = adev->gfx.ce_ram_size; 789 memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0], 790 sizeof(adev->gfx.cu_info.ao_cu_bitmap)); 791 memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], 792 sizeof(adev->gfx.cu_info.bitmap)); 793 dev_info->vram_type = adev->gmc.vram_type; 794 dev_info->vram_bit_width = adev->gmc.vram_width; 795 dev_info->vce_harvest_config = adev->vce.harvest_config; 796 dev_info->gc_double_offchip_lds_buf = 797 adev->gfx.config.double_offchip_lds_buf; 798 dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size; 799 dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs; 800 dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh; 801 dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches; 802 dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth; 803 dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth; 804 dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads; 805 806 if (adev->family >= AMDGPU_FAMILY_NV) 807 dev_info->pa_sc_tile_steering_override = 808 adev->gfx.config.pa_sc_tile_steering_override; 809 810 dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask; 811 812 ret = copy_to_user(out, dev_info, 813 min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0; 814 kfree(dev_info); 815 return ret; 816 } 817 case AMDGPU_INFO_VCE_CLOCK_TABLE: { 818 unsigned i; 819 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {}; 820 struct amd_vce_state *vce_state; 821 822 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) { 823 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i); 824 if (vce_state) { 825 vce_clk_table.entries[i].sclk = vce_state->sclk; 826 vce_clk_table.entries[i].mclk = vce_state->mclk; 827 vce_clk_table.entries[i].eclk = vce_state->evclk; 828 vce_clk_table.num_valid_entries++; 829 } 830 } 831 832 return copy_to_user(out, &vce_clk_table, 833 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0; 834 } 835 case AMDGPU_INFO_VBIOS: { 836 uint32_t bios_size = adev->bios_size; 837 838 switch (info->vbios_info.type) { 839 case AMDGPU_INFO_VBIOS_SIZE: 840 return copy_to_user(out, &bios_size, 841 min((size_t)size, sizeof(bios_size))) 842 ? -EFAULT : 0; 843 case AMDGPU_INFO_VBIOS_IMAGE: { 844 uint8_t *bios; 845 uint32_t bios_offset = info->vbios_info.offset; 846 847 if (bios_offset >= bios_size) 848 return -EINVAL; 849 850 bios = adev->bios + bios_offset; 851 return copy_to_user(out, bios, 852 min((size_t)size, (size_t)(bios_size - bios_offset))) 853 ? -EFAULT : 0; 854 } 855 default: 856 DRM_DEBUG_KMS("Invalid request %d\n", 857 info->vbios_info.type); 858 return -EINVAL; 859 } 860 } 861 case AMDGPU_INFO_NUM_HANDLES: { 862 struct drm_amdgpu_info_num_handles handle; 863 864 switch (info->query_hw_ip.type) { 865 case AMDGPU_HW_IP_UVD: 866 /* Starting Polaris, we support unlimited UVD handles */ 867 if (adev->asic_type < CHIP_POLARIS10) { 868 handle.uvd_max_handles = adev->uvd.max_handles; 869 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev); 870 871 return copy_to_user(out, &handle, 872 min((size_t)size, sizeof(handle))) ? -EFAULT : 0; 873 } else { 874 return -ENODATA; 875 } 876 877 break; 878 default: 879 return -EINVAL; 880 } 881 } 882 case AMDGPU_INFO_SENSOR: { 883 if (!adev->pm.dpm_enabled) 884 return -ENOENT; 885 886 switch (info->sensor_info.type) { 887 case AMDGPU_INFO_SENSOR_GFX_SCLK: 888 /* get sclk in Mhz */ 889 if (amdgpu_dpm_read_sensor(adev, 890 AMDGPU_PP_SENSOR_GFX_SCLK, 891 (void *)&ui32, &ui32_size)) { 892 return -EINVAL; 893 } 894 ui32 /= 100; 895 break; 896 case AMDGPU_INFO_SENSOR_GFX_MCLK: 897 /* get mclk in Mhz */ 898 if (amdgpu_dpm_read_sensor(adev, 899 AMDGPU_PP_SENSOR_GFX_MCLK, 900 (void *)&ui32, &ui32_size)) { 901 return -EINVAL; 902 } 903 ui32 /= 100; 904 break; 905 case AMDGPU_INFO_SENSOR_GPU_TEMP: 906 /* get temperature in millidegrees C */ 907 if (amdgpu_dpm_read_sensor(adev, 908 AMDGPU_PP_SENSOR_GPU_TEMP, 909 (void *)&ui32, &ui32_size)) { 910 return -EINVAL; 911 } 912 break; 913 case AMDGPU_INFO_SENSOR_GPU_LOAD: 914 /* get GPU load */ 915 if (amdgpu_dpm_read_sensor(adev, 916 AMDGPU_PP_SENSOR_GPU_LOAD, 917 (void *)&ui32, &ui32_size)) { 918 return -EINVAL; 919 } 920 break; 921 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER: 922 /* get average GPU power */ 923 if (amdgpu_dpm_read_sensor(adev, 924 AMDGPU_PP_SENSOR_GPU_POWER, 925 (void *)&ui32, &ui32_size)) { 926 return -EINVAL; 927 } 928 ui32 >>= 8; 929 break; 930 case AMDGPU_INFO_SENSOR_VDDNB: 931 /* get VDDNB in millivolts */ 932 if (amdgpu_dpm_read_sensor(adev, 933 AMDGPU_PP_SENSOR_VDDNB, 934 (void *)&ui32, &ui32_size)) { 935 return -EINVAL; 936 } 937 break; 938 case AMDGPU_INFO_SENSOR_VDDGFX: 939 /* get VDDGFX in millivolts */ 940 if (amdgpu_dpm_read_sensor(adev, 941 AMDGPU_PP_SENSOR_VDDGFX, 942 (void *)&ui32, &ui32_size)) { 943 return -EINVAL; 944 } 945 break; 946 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK: 947 /* get stable pstate sclk in Mhz */ 948 if (amdgpu_dpm_read_sensor(adev, 949 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 950 (void *)&ui32, &ui32_size)) { 951 return -EINVAL; 952 } 953 ui32 /= 100; 954 break; 955 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK: 956 /* get stable pstate mclk in Mhz */ 957 if (amdgpu_dpm_read_sensor(adev, 958 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 959 (void *)&ui32, &ui32_size)) { 960 return -EINVAL; 961 } 962 ui32 /= 100; 963 break; 964 default: 965 DRM_DEBUG_KMS("Invalid request %d\n", 966 info->sensor_info.type); 967 return -EINVAL; 968 } 969 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 970 } 971 case AMDGPU_INFO_VRAM_LOST_COUNTER: 972 ui32 = atomic_read(&adev->vram_lost_counter); 973 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 974 case AMDGPU_INFO_RAS_ENABLED_FEATURES: { 975 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 976 uint64_t ras_mask; 977 978 if (!ras) 979 return -EINVAL; 980 ras_mask = (uint64_t)ras->supported << 32 | ras->features; 981 982 return copy_to_user(out, &ras_mask, 983 min_t(u64, size, sizeof(ras_mask))) ? 984 -EFAULT : 0; 985 } 986 default: 987 DRM_DEBUG_KMS("Invalid request %d\n", info->query); 988 return -EINVAL; 989 } 990 return 0; 991 } 992 993 994 /* 995 * Outdated mess for old drm with Xorg being in charge (void function now). 996 */ 997 /** 998 * amdgpu_driver_lastclose_kms - drm callback for last close 999 * 1000 * @dev: drm dev pointer 1001 * 1002 * Switch vga_switcheroo state after last close (all asics). 1003 */ 1004 void amdgpu_driver_lastclose_kms(struct drm_device *dev) 1005 { 1006 drm_fb_helper_lastclose(dev); 1007 vga_switcheroo_process_delayed_switch(); 1008 } 1009 1010 /** 1011 * amdgpu_driver_open_kms - drm callback for open 1012 * 1013 * @dev: drm dev pointer 1014 * @file_priv: drm file 1015 * 1016 * On device open, init vm on cayman+ (all asics). 1017 * Returns 0 on success, error on failure. 1018 */ 1019 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 1020 { 1021 struct amdgpu_device *adev = drm_to_adev(dev); 1022 struct amdgpu_fpriv *fpriv; 1023 int r, pasid; 1024 1025 /* Ensure IB tests are run on ring */ 1026 flush_delayed_work(&adev->delayed_init_work); 1027 1028 1029 if (amdgpu_ras_intr_triggered()) { 1030 DRM_ERROR("RAS Intr triggered, device disabled!!"); 1031 return -EHWPOISON; 1032 } 1033 1034 file_priv->driver_priv = NULL; 1035 1036 r = pm_runtime_get_sync(dev->dev); 1037 if (r < 0) 1038 goto pm_put; 1039 1040 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 1041 if (unlikely(!fpriv)) { 1042 r = -ENOMEM; 1043 goto out_suspend; 1044 } 1045 1046 pasid = amdgpu_pasid_alloc(16); 1047 if (pasid < 0) { 1048 dev_warn(adev->dev, "No more PASIDs available!"); 1049 pasid = 0; 1050 } 1051 r = amdgpu_vm_init(adev, &fpriv->vm, AMDGPU_VM_CONTEXT_GFX, pasid); 1052 if (r) 1053 goto error_pasid; 1054 1055 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL); 1056 if (!fpriv->prt_va) { 1057 r = -ENOMEM; 1058 goto error_vm; 1059 } 1060 1061 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { 1062 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK; 1063 1064 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj, 1065 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE); 1066 if (r) 1067 goto error_vm; 1068 } 1069 1070 mutex_init(&fpriv->bo_list_lock); 1071 idr_init(&fpriv->bo_list_handles); 1072 1073 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr); 1074 1075 file_priv->driver_priv = fpriv; 1076 goto out_suspend; 1077 1078 error_vm: 1079 amdgpu_vm_fini(adev, &fpriv->vm); 1080 1081 error_pasid: 1082 if (pasid) 1083 amdgpu_pasid_free(pasid); 1084 1085 kfree(fpriv); 1086 1087 out_suspend: 1088 pm_runtime_mark_last_busy(dev->dev); 1089 pm_put: 1090 pm_runtime_put_autosuspend(dev->dev); 1091 1092 return r; 1093 } 1094 1095 /** 1096 * amdgpu_driver_postclose_kms - drm callback for post close 1097 * 1098 * @dev: drm dev pointer 1099 * @file_priv: drm file 1100 * 1101 * On device post close, tear down vm on cayman+ (all asics). 1102 */ 1103 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1104 struct drm_file *file_priv) 1105 { 1106 struct amdgpu_device *adev = drm_to_adev(dev); 1107 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1108 struct amdgpu_bo_list *list; 1109 struct amdgpu_bo *pd; 1110 u32 pasid; 1111 int handle; 1112 1113 if (!fpriv) 1114 return; 1115 1116 pm_runtime_get_sync(dev->dev); 1117 1118 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL) 1119 amdgpu_uvd_free_handles(adev, file_priv); 1120 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL) 1121 amdgpu_vce_free_handles(adev, file_priv); 1122 1123 amdgpu_vm_bo_rmv(adev, fpriv->prt_va); 1124 1125 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { 1126 /* TODO: how to handle reserve failure */ 1127 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true)); 1128 amdgpu_vm_bo_rmv(adev, fpriv->csa_va); 1129 fpriv->csa_va = NULL; 1130 amdgpu_bo_unreserve(adev->virt.csa_obj); 1131 } 1132 1133 pasid = fpriv->vm.pasid; 1134 pd = amdgpu_bo_ref(fpriv->vm.root.base.bo); 1135 1136 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); 1137 amdgpu_vm_fini(adev, &fpriv->vm); 1138 1139 if (pasid) 1140 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid); 1141 amdgpu_bo_unref(&pd); 1142 1143 idr_for_each_entry(&fpriv->bo_list_handles, list, handle) 1144 amdgpu_bo_list_put(list); 1145 1146 idr_destroy(&fpriv->bo_list_handles); 1147 mutex_destroy(&fpriv->bo_list_lock); 1148 1149 kfree(fpriv); 1150 file_priv->driver_priv = NULL; 1151 1152 pm_runtime_mark_last_busy(dev->dev); 1153 pm_runtime_put_autosuspend(dev->dev); 1154 } 1155 1156 /* 1157 * VBlank related functions. 1158 */ 1159 /** 1160 * amdgpu_get_vblank_counter_kms - get frame count 1161 * 1162 * @crtc: crtc to get the frame count from 1163 * 1164 * Gets the frame count on the requested crtc (all asics). 1165 * Returns frame count on success, -EINVAL on failure. 1166 */ 1167 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc) 1168 { 1169 struct drm_device *dev = crtc->dev; 1170 unsigned int pipe = crtc->index; 1171 struct amdgpu_device *adev = drm_to_adev(dev); 1172 int vpos, hpos, stat; 1173 u32 count; 1174 1175 if (pipe >= adev->mode_info.num_crtc) { 1176 DRM_ERROR("Invalid crtc %u\n", pipe); 1177 return -EINVAL; 1178 } 1179 1180 /* The hw increments its frame counter at start of vsync, not at start 1181 * of vblank, as is required by DRM core vblank counter handling. 1182 * Cook the hw count here to make it appear to the caller as if it 1183 * incremented at start of vblank. We measure distance to start of 1184 * vblank in vpos. vpos therefore will be >= 0 between start of vblank 1185 * and start of vsync, so vpos >= 0 means to bump the hw frame counter 1186 * result by 1 to give the proper appearance to caller. 1187 */ 1188 if (adev->mode_info.crtcs[pipe]) { 1189 /* Repeat readout if needed to provide stable result if 1190 * we cross start of vsync during the queries. 1191 */ 1192 do { 1193 count = amdgpu_display_vblank_get_counter(adev, pipe); 1194 /* Ask amdgpu_display_get_crtc_scanoutpos to return 1195 * vpos as distance to start of vblank, instead of 1196 * regular vertical scanout pos. 1197 */ 1198 stat = amdgpu_display_get_crtc_scanoutpos( 1199 dev, pipe, GET_DISTANCE_TO_VBLANKSTART, 1200 &vpos, &hpos, NULL, NULL, 1201 &adev->mode_info.crtcs[pipe]->base.hwmode); 1202 } while (count != amdgpu_display_vblank_get_counter(adev, pipe)); 1203 1204 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 1205 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 1206 DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 1207 } else { 1208 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", 1209 pipe, vpos); 1210 1211 /* Bump counter if we are at >= leading edge of vblank, 1212 * but before vsync where vpos would turn negative and 1213 * the hw counter really increments. 1214 */ 1215 if (vpos >= 0) 1216 count++; 1217 } 1218 } else { 1219 /* Fallback to use value as is. */ 1220 count = amdgpu_display_vblank_get_counter(adev, pipe); 1221 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 1222 } 1223 1224 return count; 1225 } 1226 1227 /** 1228 * amdgpu_enable_vblank_kms - enable vblank interrupt 1229 * 1230 * @crtc: crtc to enable vblank interrupt for 1231 * 1232 * Enable the interrupt on the requested crtc (all asics). 1233 * Returns 0 on success, -EINVAL on failure. 1234 */ 1235 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc) 1236 { 1237 struct drm_device *dev = crtc->dev; 1238 unsigned int pipe = crtc->index; 1239 struct amdgpu_device *adev = drm_to_adev(dev); 1240 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1241 1242 return amdgpu_irq_get(adev, &adev->crtc_irq, idx); 1243 } 1244 1245 /** 1246 * amdgpu_disable_vblank_kms - disable vblank interrupt 1247 * 1248 * @crtc: crtc to disable vblank interrupt for 1249 * 1250 * Disable the interrupt on the requested crtc (all asics). 1251 */ 1252 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc) 1253 { 1254 struct drm_device *dev = crtc->dev; 1255 unsigned int pipe = crtc->index; 1256 struct amdgpu_device *adev = drm_to_adev(dev); 1257 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1258 1259 amdgpu_irq_put(adev, &adev->crtc_irq, idx); 1260 } 1261 1262 /* 1263 * Debugfs info 1264 */ 1265 #if defined(CONFIG_DEBUG_FS) 1266 1267 static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data) 1268 { 1269 struct drm_info_node *node = (struct drm_info_node *) m->private; 1270 struct drm_device *dev = node->minor->dev; 1271 struct amdgpu_device *adev = drm_to_adev(dev); 1272 struct drm_amdgpu_info_firmware fw_info; 1273 struct drm_amdgpu_query_fw query_fw; 1274 struct atom_context *ctx = adev->mode_info.atom_context; 1275 int ret, i; 1276 1277 /* VCE */ 1278 query_fw.fw_type = AMDGPU_INFO_FW_VCE; 1279 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1280 if (ret) 1281 return ret; 1282 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n", 1283 fw_info.feature, fw_info.ver); 1284 1285 /* UVD */ 1286 query_fw.fw_type = AMDGPU_INFO_FW_UVD; 1287 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1288 if (ret) 1289 return ret; 1290 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n", 1291 fw_info.feature, fw_info.ver); 1292 1293 /* GMC */ 1294 query_fw.fw_type = AMDGPU_INFO_FW_GMC; 1295 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1296 if (ret) 1297 return ret; 1298 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n", 1299 fw_info.feature, fw_info.ver); 1300 1301 /* ME */ 1302 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME; 1303 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1304 if (ret) 1305 return ret; 1306 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n", 1307 fw_info.feature, fw_info.ver); 1308 1309 /* PFP */ 1310 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP; 1311 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1312 if (ret) 1313 return ret; 1314 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n", 1315 fw_info.feature, fw_info.ver); 1316 1317 /* CE */ 1318 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE; 1319 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1320 if (ret) 1321 return ret; 1322 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n", 1323 fw_info.feature, fw_info.ver); 1324 1325 /* RLC */ 1326 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC; 1327 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1328 if (ret) 1329 return ret; 1330 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n", 1331 fw_info.feature, fw_info.ver); 1332 1333 /* RLC SAVE RESTORE LIST CNTL */ 1334 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL; 1335 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1336 if (ret) 1337 return ret; 1338 seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n", 1339 fw_info.feature, fw_info.ver); 1340 1341 /* RLC SAVE RESTORE LIST GPM MEM */ 1342 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM; 1343 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1344 if (ret) 1345 return ret; 1346 seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n", 1347 fw_info.feature, fw_info.ver); 1348 1349 /* RLC SAVE RESTORE LIST SRM MEM */ 1350 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM; 1351 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1352 if (ret) 1353 return ret; 1354 seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n", 1355 fw_info.feature, fw_info.ver); 1356 1357 /* MEC */ 1358 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC; 1359 query_fw.index = 0; 1360 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1361 if (ret) 1362 return ret; 1363 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n", 1364 fw_info.feature, fw_info.ver); 1365 1366 /* MEC2 */ 1367 if (adev->gfx.mec2_fw) { 1368 query_fw.index = 1; 1369 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1370 if (ret) 1371 return ret; 1372 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n", 1373 fw_info.feature, fw_info.ver); 1374 } 1375 1376 /* PSP SOS */ 1377 query_fw.fw_type = AMDGPU_INFO_FW_SOS; 1378 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1379 if (ret) 1380 return ret; 1381 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n", 1382 fw_info.feature, fw_info.ver); 1383 1384 1385 /* PSP ASD */ 1386 query_fw.fw_type = AMDGPU_INFO_FW_ASD; 1387 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1388 if (ret) 1389 return ret; 1390 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n", 1391 fw_info.feature, fw_info.ver); 1392 1393 query_fw.fw_type = AMDGPU_INFO_FW_TA; 1394 for (i = 0; i < 4; i++) { 1395 query_fw.index = i; 1396 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1397 if (ret) 1398 continue; 1399 switch (query_fw.index) { 1400 case 0: 1401 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n", 1402 "RAS", fw_info.feature, fw_info.ver); 1403 break; 1404 case 1: 1405 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n", 1406 "XGMI", fw_info.feature, fw_info.ver); 1407 break; 1408 case 2: 1409 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n", 1410 "HDCP", fw_info.feature, fw_info.ver); 1411 break; 1412 case 3: 1413 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n", 1414 "DTM", fw_info.feature, fw_info.ver); 1415 break; 1416 default: 1417 return -EINVAL; 1418 } 1419 } 1420 1421 /* SMC */ 1422 query_fw.fw_type = AMDGPU_INFO_FW_SMC; 1423 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1424 if (ret) 1425 return ret; 1426 seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n", 1427 fw_info.feature, fw_info.ver); 1428 1429 /* SDMA */ 1430 query_fw.fw_type = AMDGPU_INFO_FW_SDMA; 1431 for (i = 0; i < adev->sdma.num_instances; i++) { 1432 query_fw.index = i; 1433 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1434 if (ret) 1435 return ret; 1436 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n", 1437 i, fw_info.feature, fw_info.ver); 1438 } 1439 1440 /* VCN */ 1441 query_fw.fw_type = AMDGPU_INFO_FW_VCN; 1442 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1443 if (ret) 1444 return ret; 1445 seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n", 1446 fw_info.feature, fw_info.ver); 1447 1448 /* DMCU */ 1449 query_fw.fw_type = AMDGPU_INFO_FW_DMCU; 1450 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1451 if (ret) 1452 return ret; 1453 seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n", 1454 fw_info.feature, fw_info.ver); 1455 1456 /* DMCUB */ 1457 query_fw.fw_type = AMDGPU_INFO_FW_DMCUB; 1458 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1459 if (ret) 1460 return ret; 1461 seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n", 1462 fw_info.feature, fw_info.ver); 1463 1464 /* TOC */ 1465 query_fw.fw_type = AMDGPU_INFO_FW_TOC; 1466 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1467 if (ret) 1468 return ret; 1469 seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n", 1470 fw_info.feature, fw_info.ver); 1471 1472 seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version); 1473 1474 return 0; 1475 } 1476 1477 static const struct drm_info_list amdgpu_firmware_info_list[] = { 1478 {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL}, 1479 }; 1480 #endif 1481 1482 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev) 1483 { 1484 #if defined(CONFIG_DEBUG_FS) 1485 return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list, 1486 ARRAY_SIZE(amdgpu_firmware_info_list)); 1487 #else 1488 return 0; 1489 #endif 1490 } 1491