1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include "amdgpu.h" 30 #include <drm/amdgpu_drm.h> 31 #include <drm/drm_drv.h> 32 #include <drm/drm_fb_helper.h> 33 #include "amdgpu_uvd.h" 34 #include "amdgpu_vce.h" 35 #include "atom.h" 36 37 #include <linux/vga_switcheroo.h> 38 #include <linux/slab.h> 39 #include <linux/uaccess.h> 40 #include <linux/pci.h> 41 #include <linux/pm_runtime.h> 42 #include "amdgpu_amdkfd.h" 43 #include "amdgpu_gem.h" 44 #include "amdgpu_display.h" 45 #include "amdgpu_ras.h" 46 #include "amdgpu_reset.h" 47 #include "amd_pcie.h" 48 #include "amdgpu_userq.h" 49 50 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev) 51 { 52 struct amdgpu_gpu_instance *gpu_instance; 53 int i; 54 55 mutex_lock(&mgpu_info.mutex); 56 57 for (i = 0; i < mgpu_info.num_gpu; i++) { 58 gpu_instance = &(mgpu_info.gpu_ins[i]); 59 if (gpu_instance->adev == adev) { 60 mgpu_info.gpu_ins[i] = 61 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1]; 62 mgpu_info.num_gpu--; 63 if (adev->flags & AMD_IS_APU) 64 mgpu_info.num_apu--; 65 else 66 mgpu_info.num_dgpu--; 67 break; 68 } 69 } 70 71 mutex_unlock(&mgpu_info.mutex); 72 } 73 74 /** 75 * amdgpu_driver_unload_kms - Main unload function for KMS. 76 * 77 * @dev: drm dev pointer 78 * 79 * This is the main unload function for KMS (all asics). 80 * Returns 0 on success. 81 */ 82 void amdgpu_driver_unload_kms(struct drm_device *dev) 83 { 84 struct amdgpu_device *adev = drm_to_adev(dev); 85 86 if (adev == NULL) 87 return; 88 89 amdgpu_unregister_gpu_instance(adev); 90 91 if (adev->rmmio == NULL) 92 return; 93 94 if (amdgpu_acpi_smart_shift_update(adev, AMDGPU_SS_DRV_UNLOAD)) 95 DRM_WARN("smart shift update failed\n"); 96 97 amdgpu_acpi_fini(adev); 98 amdgpu_device_fini_hw(adev); 99 } 100 101 void amdgpu_register_gpu_instance(struct amdgpu_device *adev) 102 { 103 struct amdgpu_gpu_instance *gpu_instance; 104 105 mutex_lock(&mgpu_info.mutex); 106 107 if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) { 108 DRM_ERROR("Cannot register more gpu instance\n"); 109 mutex_unlock(&mgpu_info.mutex); 110 return; 111 } 112 113 gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]); 114 gpu_instance->adev = adev; 115 gpu_instance->mgpu_fan_enabled = 0; 116 117 mgpu_info.num_gpu++; 118 if (adev->flags & AMD_IS_APU) 119 mgpu_info.num_apu++; 120 else 121 mgpu_info.num_dgpu++; 122 123 mutex_unlock(&mgpu_info.mutex); 124 } 125 126 /** 127 * amdgpu_driver_load_kms - Main load function for KMS. 128 * 129 * @adev: pointer to struct amdgpu_device 130 * @flags: device flags 131 * 132 * This is the main load function for KMS (all asics). 133 * Returns 0 on success, error on failure. 134 */ 135 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags) 136 { 137 struct drm_device *dev; 138 int r, acpi_status; 139 140 dev = adev_to_drm(adev); 141 142 /* amdgpu_device_init should report only fatal error 143 * like memory allocation failure or iomapping failure, 144 * or memory manager initialization failure, it must 145 * properly initialize the GPU MC controller and permit 146 * VRAM allocation 147 */ 148 r = amdgpu_device_init(adev, flags); 149 if (r) { 150 dev_err(dev->dev, "Fatal error during GPU init\n"); 151 goto out; 152 } 153 154 amdgpu_device_detect_runtime_pm_mode(adev); 155 156 /* Call ACPI methods: require modeset init 157 * but failure is not fatal 158 */ 159 160 acpi_status = amdgpu_acpi_init(adev); 161 if (acpi_status) 162 dev_dbg(dev->dev, "Error during ACPI methods call\n"); 163 164 if (amdgpu_acpi_smart_shift_update(adev, AMDGPU_SS_DRV_LOAD)) 165 DRM_WARN("smart shift update failed\n"); 166 167 out: 168 if (r) 169 amdgpu_driver_unload_kms(dev); 170 171 return r; 172 } 173 174 static enum amd_ip_block_type 175 amdgpu_ip_get_block_type(struct amdgpu_device *adev, uint32_t ip) 176 { 177 enum amd_ip_block_type type; 178 179 switch (ip) { 180 case AMDGPU_HW_IP_GFX: 181 type = AMD_IP_BLOCK_TYPE_GFX; 182 break; 183 case AMDGPU_HW_IP_COMPUTE: 184 type = AMD_IP_BLOCK_TYPE_GFX; 185 break; 186 case AMDGPU_HW_IP_DMA: 187 type = AMD_IP_BLOCK_TYPE_SDMA; 188 break; 189 case AMDGPU_HW_IP_UVD: 190 case AMDGPU_HW_IP_UVD_ENC: 191 type = AMD_IP_BLOCK_TYPE_UVD; 192 break; 193 case AMDGPU_HW_IP_VCE: 194 type = AMD_IP_BLOCK_TYPE_VCE; 195 break; 196 case AMDGPU_HW_IP_VCN_DEC: 197 case AMDGPU_HW_IP_VCN_ENC: 198 type = AMD_IP_BLOCK_TYPE_VCN; 199 break; 200 case AMDGPU_HW_IP_VCN_JPEG: 201 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 202 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 203 break; 204 default: 205 type = AMD_IP_BLOCK_TYPE_NUM; 206 break; 207 } 208 209 return type; 210 } 211 212 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, 213 struct drm_amdgpu_query_fw *query_fw, 214 struct amdgpu_device *adev) 215 { 216 switch (query_fw->fw_type) { 217 case AMDGPU_INFO_FW_VCE: 218 fw_info->ver = adev->vce.fw_version; 219 fw_info->feature = adev->vce.fb_version; 220 break; 221 case AMDGPU_INFO_FW_UVD: 222 fw_info->ver = adev->uvd.fw_version; 223 fw_info->feature = 0; 224 break; 225 case AMDGPU_INFO_FW_VCN: 226 fw_info->ver = adev->vcn.fw_version; 227 fw_info->feature = 0; 228 break; 229 case AMDGPU_INFO_FW_GMC: 230 fw_info->ver = adev->gmc.fw_version; 231 fw_info->feature = 0; 232 break; 233 case AMDGPU_INFO_FW_GFX_ME: 234 fw_info->ver = adev->gfx.me_fw_version; 235 fw_info->feature = adev->gfx.me_feature_version; 236 break; 237 case AMDGPU_INFO_FW_GFX_PFP: 238 fw_info->ver = adev->gfx.pfp_fw_version; 239 fw_info->feature = adev->gfx.pfp_feature_version; 240 break; 241 case AMDGPU_INFO_FW_GFX_CE: 242 fw_info->ver = adev->gfx.ce_fw_version; 243 fw_info->feature = adev->gfx.ce_feature_version; 244 break; 245 case AMDGPU_INFO_FW_GFX_RLC: 246 fw_info->ver = adev->gfx.rlc_fw_version; 247 fw_info->feature = adev->gfx.rlc_feature_version; 248 break; 249 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL: 250 fw_info->ver = adev->gfx.rlc_srlc_fw_version; 251 fw_info->feature = adev->gfx.rlc_srlc_feature_version; 252 break; 253 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM: 254 fw_info->ver = adev->gfx.rlc_srlg_fw_version; 255 fw_info->feature = adev->gfx.rlc_srlg_feature_version; 256 break; 257 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM: 258 fw_info->ver = adev->gfx.rlc_srls_fw_version; 259 fw_info->feature = adev->gfx.rlc_srls_feature_version; 260 break; 261 case AMDGPU_INFO_FW_GFX_RLCP: 262 fw_info->ver = adev->gfx.rlcp_ucode_version; 263 fw_info->feature = adev->gfx.rlcp_ucode_feature_version; 264 break; 265 case AMDGPU_INFO_FW_GFX_RLCV: 266 fw_info->ver = adev->gfx.rlcv_ucode_version; 267 fw_info->feature = adev->gfx.rlcv_ucode_feature_version; 268 break; 269 case AMDGPU_INFO_FW_GFX_MEC: 270 if (query_fw->index == 0) { 271 fw_info->ver = adev->gfx.mec_fw_version; 272 fw_info->feature = adev->gfx.mec_feature_version; 273 } else if (query_fw->index == 1) { 274 fw_info->ver = adev->gfx.mec2_fw_version; 275 fw_info->feature = adev->gfx.mec2_feature_version; 276 } else 277 return -EINVAL; 278 break; 279 case AMDGPU_INFO_FW_SMC: 280 fw_info->ver = adev->pm.fw_version; 281 fw_info->feature = 0; 282 break; 283 case AMDGPU_INFO_FW_TA: 284 switch (query_fw->index) { 285 case TA_FW_TYPE_PSP_XGMI: 286 fw_info->ver = adev->psp.xgmi_context.context.bin_desc.fw_version; 287 fw_info->feature = adev->psp.xgmi_context.context 288 .bin_desc.feature_version; 289 break; 290 case TA_FW_TYPE_PSP_RAS: 291 fw_info->ver = adev->psp.ras_context.context.bin_desc.fw_version; 292 fw_info->feature = adev->psp.ras_context.context 293 .bin_desc.feature_version; 294 break; 295 case TA_FW_TYPE_PSP_HDCP: 296 fw_info->ver = adev->psp.hdcp_context.context.bin_desc.fw_version; 297 fw_info->feature = adev->psp.hdcp_context.context 298 .bin_desc.feature_version; 299 break; 300 case TA_FW_TYPE_PSP_DTM: 301 fw_info->ver = adev->psp.dtm_context.context.bin_desc.fw_version; 302 fw_info->feature = adev->psp.dtm_context.context 303 .bin_desc.feature_version; 304 break; 305 case TA_FW_TYPE_PSP_RAP: 306 fw_info->ver = adev->psp.rap_context.context.bin_desc.fw_version; 307 fw_info->feature = adev->psp.rap_context.context 308 .bin_desc.feature_version; 309 break; 310 case TA_FW_TYPE_PSP_SECUREDISPLAY: 311 fw_info->ver = adev->psp.securedisplay_context.context.bin_desc.fw_version; 312 fw_info->feature = 313 adev->psp.securedisplay_context.context.bin_desc 314 .feature_version; 315 break; 316 default: 317 return -EINVAL; 318 } 319 break; 320 case AMDGPU_INFO_FW_SDMA: 321 if (query_fw->index >= adev->sdma.num_instances) 322 return -EINVAL; 323 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version; 324 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version; 325 break; 326 case AMDGPU_INFO_FW_SOS: 327 fw_info->ver = adev->psp.sos.fw_version; 328 fw_info->feature = adev->psp.sos.feature_version; 329 break; 330 case AMDGPU_INFO_FW_ASD: 331 fw_info->ver = adev->psp.asd_context.bin_desc.fw_version; 332 fw_info->feature = adev->psp.asd_context.bin_desc.feature_version; 333 break; 334 case AMDGPU_INFO_FW_DMCU: 335 fw_info->ver = adev->dm.dmcu_fw_version; 336 fw_info->feature = 0; 337 break; 338 case AMDGPU_INFO_FW_DMCUB: 339 fw_info->ver = adev->dm.dmcub_fw_version; 340 fw_info->feature = 0; 341 break; 342 case AMDGPU_INFO_FW_TOC: 343 fw_info->ver = adev->psp.toc.fw_version; 344 fw_info->feature = adev->psp.toc.feature_version; 345 break; 346 case AMDGPU_INFO_FW_CAP: 347 fw_info->ver = adev->psp.cap_fw_version; 348 fw_info->feature = adev->psp.cap_feature_version; 349 break; 350 case AMDGPU_INFO_FW_MES_KIQ: 351 fw_info->ver = adev->mes.kiq_version & AMDGPU_MES_VERSION_MASK; 352 fw_info->feature = (adev->mes.kiq_version & AMDGPU_MES_FEAT_VERSION_MASK) 353 >> AMDGPU_MES_FEAT_VERSION_SHIFT; 354 break; 355 case AMDGPU_INFO_FW_MES: 356 fw_info->ver = adev->mes.sched_version & AMDGPU_MES_VERSION_MASK; 357 fw_info->feature = (adev->mes.sched_version & AMDGPU_MES_FEAT_VERSION_MASK) 358 >> AMDGPU_MES_FEAT_VERSION_SHIFT; 359 break; 360 case AMDGPU_INFO_FW_IMU: 361 fw_info->ver = adev->gfx.imu_fw_version; 362 fw_info->feature = 0; 363 break; 364 case AMDGPU_INFO_FW_VPE: 365 fw_info->ver = adev->vpe.fw_version; 366 fw_info->feature = adev->vpe.feature_version; 367 break; 368 default: 369 return -EINVAL; 370 } 371 return 0; 372 } 373 374 static int amdgpu_userq_metadata_info_gfx(struct amdgpu_device *adev, 375 struct drm_amdgpu_info *info, 376 struct drm_amdgpu_info_uq_metadata_gfx *meta) 377 { 378 int ret = -EOPNOTSUPP; 379 380 if (adev->gfx.funcs->get_gfx_shadow_info) { 381 struct amdgpu_gfx_shadow_info shadow = {}; 382 383 adev->gfx.funcs->get_gfx_shadow_info(adev, &shadow, true); 384 meta->shadow_size = shadow.shadow_size; 385 meta->shadow_alignment = shadow.shadow_alignment; 386 meta->csa_size = shadow.csa_size; 387 meta->csa_alignment = shadow.csa_alignment; 388 ret = 0; 389 } 390 391 return ret; 392 } 393 394 static int amdgpu_hw_ip_info(struct amdgpu_device *adev, 395 struct drm_amdgpu_info *info, 396 struct drm_amdgpu_info_hw_ip *result) 397 { 398 uint32_t ib_start_alignment = 0; 399 uint32_t ib_size_alignment = 0; 400 enum amd_ip_block_type type; 401 unsigned int num_rings = 0; 402 uint32_t num_slots = 0; 403 unsigned int i, j; 404 405 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 406 return -EINVAL; 407 408 switch (info->query_hw_ip.type) { 409 case AMDGPU_HW_IP_GFX: 410 type = AMD_IP_BLOCK_TYPE_GFX; 411 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 412 if (adev->gfx.gfx_ring[i].sched.ready && 413 !adev->gfx.gfx_ring[i].no_user_submission) 414 ++num_rings; 415 416 if (!adev->gfx.disable_uq) { 417 for (i = 0; i < AMDGPU_MES_MAX_GFX_PIPES; i++) 418 num_slots += hweight32(adev->mes.gfx_hqd_mask[i]); 419 } 420 421 ib_start_alignment = 32; 422 ib_size_alignment = 32; 423 break; 424 case AMDGPU_HW_IP_COMPUTE: 425 type = AMD_IP_BLOCK_TYPE_GFX; 426 for (i = 0; i < adev->gfx.num_compute_rings; i++) 427 if (adev->gfx.compute_ring[i].sched.ready && 428 !adev->gfx.compute_ring[i].no_user_submission) 429 ++num_rings; 430 431 if (!adev->sdma.disable_uq) { 432 for (i = 0; i < AMDGPU_MES_MAX_COMPUTE_PIPES; i++) 433 num_slots += hweight32(adev->mes.compute_hqd_mask[i]); 434 } 435 436 ib_start_alignment = 32; 437 ib_size_alignment = 32; 438 break; 439 case AMDGPU_HW_IP_DMA: 440 type = AMD_IP_BLOCK_TYPE_SDMA; 441 for (i = 0; i < adev->sdma.num_instances; i++) 442 if (adev->sdma.instance[i].ring.sched.ready && 443 !adev->sdma.instance[i].ring.no_user_submission) 444 ++num_rings; 445 446 if (!adev->gfx.disable_uq) { 447 for (i = 0; i < AMDGPU_MES_MAX_SDMA_PIPES; i++) 448 num_slots += hweight32(adev->mes.sdma_hqd_mask[i]); 449 } 450 451 ib_start_alignment = 256; 452 ib_size_alignment = 4; 453 break; 454 case AMDGPU_HW_IP_UVD: 455 type = AMD_IP_BLOCK_TYPE_UVD; 456 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 457 if (adev->uvd.harvest_config & (1 << i)) 458 continue; 459 460 if (adev->uvd.inst[i].ring.sched.ready && 461 !adev->uvd.inst[i].ring.no_user_submission) 462 ++num_rings; 463 } 464 ib_start_alignment = 256; 465 ib_size_alignment = 64; 466 break; 467 case AMDGPU_HW_IP_VCE: 468 type = AMD_IP_BLOCK_TYPE_VCE; 469 for (i = 0; i < adev->vce.num_rings; i++) 470 if (adev->vce.ring[i].sched.ready && 471 !adev->vce.ring[i].no_user_submission) 472 ++num_rings; 473 ib_start_alignment = 256; 474 ib_size_alignment = 4; 475 break; 476 case AMDGPU_HW_IP_UVD_ENC: 477 type = AMD_IP_BLOCK_TYPE_UVD; 478 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 479 if (adev->uvd.harvest_config & (1 << i)) 480 continue; 481 482 for (j = 0; j < adev->uvd.num_enc_rings; j++) 483 if (adev->uvd.inst[i].ring_enc[j].sched.ready && 484 !adev->uvd.inst[i].ring_enc[j].no_user_submission) 485 ++num_rings; 486 } 487 ib_start_alignment = 256; 488 ib_size_alignment = 4; 489 break; 490 case AMDGPU_HW_IP_VCN_DEC: 491 type = AMD_IP_BLOCK_TYPE_VCN; 492 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 493 if (adev->vcn.harvest_config & (1 << i)) 494 continue; 495 496 if (adev->vcn.inst[i].ring_dec.sched.ready && 497 !adev->vcn.inst[i].ring_dec.no_user_submission) 498 ++num_rings; 499 } 500 ib_start_alignment = 256; 501 ib_size_alignment = 64; 502 break; 503 case AMDGPU_HW_IP_VCN_ENC: 504 type = AMD_IP_BLOCK_TYPE_VCN; 505 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 506 if (adev->vcn.harvest_config & (1 << i)) 507 continue; 508 509 for (j = 0; j < adev->vcn.inst[i].num_enc_rings; j++) 510 if (adev->vcn.inst[i].ring_enc[j].sched.ready && 511 !adev->vcn.inst[i].ring_enc[j].no_user_submission) 512 ++num_rings; 513 } 514 ib_start_alignment = 256; 515 ib_size_alignment = 4; 516 break; 517 case AMDGPU_HW_IP_VCN_JPEG: 518 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 519 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 520 521 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { 522 if (adev->jpeg.harvest_config & (1 << i)) 523 continue; 524 525 for (j = 0; j < adev->jpeg.num_jpeg_rings; j++) 526 if (adev->jpeg.inst[i].ring_dec[j].sched.ready && 527 !adev->jpeg.inst[i].ring_dec[j].no_user_submission) 528 ++num_rings; 529 } 530 ib_start_alignment = 256; 531 ib_size_alignment = 64; 532 break; 533 case AMDGPU_HW_IP_VPE: 534 type = AMD_IP_BLOCK_TYPE_VPE; 535 if (adev->vpe.ring.sched.ready && 536 !adev->vpe.ring.no_user_submission) 537 ++num_rings; 538 ib_start_alignment = 256; 539 ib_size_alignment = 4; 540 break; 541 default: 542 return -EINVAL; 543 } 544 545 for (i = 0; i < adev->num_ip_blocks; i++) 546 if (adev->ip_blocks[i].version->type == type && 547 adev->ip_blocks[i].status.valid) 548 break; 549 550 if (i == adev->num_ip_blocks) 551 return 0; 552 553 num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type], 554 num_rings); 555 556 result->hw_ip_version_major = adev->ip_blocks[i].version->major; 557 result->hw_ip_version_minor = adev->ip_blocks[i].version->minor; 558 559 if (adev->asic_type >= CHIP_VEGA10) { 560 switch (type) { 561 case AMD_IP_BLOCK_TYPE_GFX: 562 result->ip_discovery_version = 563 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, GC_HWIP, 0)); 564 break; 565 case AMD_IP_BLOCK_TYPE_SDMA: 566 result->ip_discovery_version = 567 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, SDMA0_HWIP, 0)); 568 break; 569 case AMD_IP_BLOCK_TYPE_UVD: 570 case AMD_IP_BLOCK_TYPE_VCN: 571 case AMD_IP_BLOCK_TYPE_JPEG: 572 result->ip_discovery_version = 573 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, UVD_HWIP, 0)); 574 break; 575 case AMD_IP_BLOCK_TYPE_VCE: 576 result->ip_discovery_version = 577 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, VCE_HWIP, 0)); 578 break; 579 case AMD_IP_BLOCK_TYPE_VPE: 580 result->ip_discovery_version = 581 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, VPE_HWIP, 0)); 582 break; 583 default: 584 result->ip_discovery_version = 0; 585 break; 586 } 587 } else { 588 result->ip_discovery_version = 0; 589 } 590 result->capabilities_flags = 0; 591 result->available_rings = (1 << num_rings) - 1; 592 result->userq_num_slots = num_slots; 593 result->ib_start_alignment = ib_start_alignment; 594 result->ib_size_alignment = ib_size_alignment; 595 return 0; 596 } 597 598 /* 599 * Userspace get information ioctl 600 */ 601 /** 602 * amdgpu_info_ioctl - answer a device specific request. 603 * 604 * @dev: drm device pointer 605 * @data: request object 606 * @filp: drm filp 607 * 608 * This function is used to pass device specific parameters to the userspace 609 * drivers. Examples include: pci device id, pipeline parms, tiling params, 610 * etc. (all asics). 611 * Returns 0 on success, -EINVAL on failure. 612 */ 613 int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 614 { 615 struct amdgpu_device *adev = drm_to_adev(dev); 616 struct drm_amdgpu_info *info = data; 617 struct amdgpu_mode_info *minfo = &adev->mode_info; 618 void __user *out = (void __user *)(uintptr_t)info->return_pointer; 619 struct amdgpu_fpriv *fpriv; 620 struct amdgpu_ip_block *ip_block; 621 enum amd_ip_block_type type; 622 struct amdgpu_xcp *xcp; 623 u32 count, inst_mask; 624 uint32_t size = info->return_size; 625 struct drm_crtc *crtc; 626 uint32_t ui32 = 0; 627 uint64_t ui64 = 0; 628 int i, found, ret; 629 int ui32_size = sizeof(ui32); 630 631 if (!info->return_size || !info->return_pointer) 632 return -EINVAL; 633 634 switch (info->query) { 635 case AMDGPU_INFO_ACCEL_WORKING: 636 ui32 = adev->accel_working; 637 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 638 case AMDGPU_INFO_CRTC_FROM_ID: 639 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { 640 crtc = (struct drm_crtc *)minfo->crtcs[i]; 641 if (crtc && crtc->base.id == info->mode_crtc.id) { 642 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 643 644 ui32 = amdgpu_crtc->crtc_id; 645 found = 1; 646 break; 647 } 648 } 649 if (!found) { 650 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); 651 return -EINVAL; 652 } 653 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 654 case AMDGPU_INFO_HW_IP_INFO: { 655 struct drm_amdgpu_info_hw_ip ip = {}; 656 657 ret = amdgpu_hw_ip_info(adev, info, &ip); 658 if (ret) 659 return ret; 660 661 ret = copy_to_user(out, &ip, min_t(size_t, size, sizeof(ip))); 662 return ret ? -EFAULT : 0; 663 } 664 case AMDGPU_INFO_HW_IP_COUNT: { 665 fpriv = (struct amdgpu_fpriv *)filp->driver_priv; 666 type = amdgpu_ip_get_block_type(adev, info->query_hw_ip.type); 667 ip_block = amdgpu_device_ip_get_ip_block(adev, type); 668 669 if (!ip_block || !ip_block->status.valid) 670 return -EINVAL; 671 672 if (adev->xcp_mgr && adev->xcp_mgr->num_xcps > 0 && 673 fpriv->xcp_id < adev->xcp_mgr->num_xcps) { 674 xcp = &adev->xcp_mgr->xcp[fpriv->xcp_id]; 675 switch (type) { 676 case AMD_IP_BLOCK_TYPE_GFX: 677 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &inst_mask); 678 if (ret) 679 return ret; 680 count = hweight32(inst_mask); 681 break; 682 case AMD_IP_BLOCK_TYPE_SDMA: 683 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_SDMA, &inst_mask); 684 if (ret) 685 return ret; 686 count = hweight32(inst_mask); 687 break; 688 case AMD_IP_BLOCK_TYPE_JPEG: 689 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask); 690 if (ret) 691 return ret; 692 count = hweight32(inst_mask) * adev->jpeg.num_jpeg_rings; 693 break; 694 case AMD_IP_BLOCK_TYPE_VCN: 695 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask); 696 if (ret) 697 return ret; 698 count = hweight32(inst_mask); 699 break; 700 default: 701 return -EINVAL; 702 } 703 704 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; 705 } 706 707 switch (type) { 708 case AMD_IP_BLOCK_TYPE_GFX: 709 case AMD_IP_BLOCK_TYPE_VCE: 710 count = 1; 711 break; 712 case AMD_IP_BLOCK_TYPE_SDMA: 713 count = adev->sdma.num_instances; 714 break; 715 case AMD_IP_BLOCK_TYPE_JPEG: 716 count = adev->jpeg.num_jpeg_inst * adev->jpeg.num_jpeg_rings; 717 break; 718 case AMD_IP_BLOCK_TYPE_VCN: 719 count = adev->vcn.num_vcn_inst; 720 break; 721 case AMD_IP_BLOCK_TYPE_UVD: 722 count = adev->uvd.num_uvd_inst; 723 break; 724 /* For all other IP block types not listed in the switch statement 725 * the ip status is valid here and the instance count is one. 726 */ 727 default: 728 count = 1; 729 break; 730 } 731 732 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; 733 } 734 case AMDGPU_INFO_TIMESTAMP: 735 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev); 736 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 737 case AMDGPU_INFO_FW_VERSION: { 738 struct drm_amdgpu_info_firmware fw_info; 739 740 /* We only support one instance of each IP block right now. */ 741 if (info->query_fw.ip_instance != 0) 742 return -EINVAL; 743 744 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev); 745 if (ret) 746 return ret; 747 748 return copy_to_user(out, &fw_info, 749 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0; 750 } 751 case AMDGPU_INFO_NUM_BYTES_MOVED: 752 ui64 = atomic64_read(&adev->num_bytes_moved); 753 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 754 case AMDGPU_INFO_NUM_EVICTIONS: 755 ui64 = atomic64_read(&adev->num_evictions); 756 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 757 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS: 758 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults); 759 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 760 case AMDGPU_INFO_VRAM_USAGE: 761 ui64 = ttm_resource_manager_usage(&adev->mman.vram_mgr.manager); 762 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 763 case AMDGPU_INFO_VIS_VRAM_USAGE: 764 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr); 765 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 766 case AMDGPU_INFO_GTT_USAGE: 767 ui64 = ttm_resource_manager_usage(&adev->mman.gtt_mgr.manager); 768 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 769 case AMDGPU_INFO_GDS_CONFIG: { 770 struct drm_amdgpu_info_gds gds_info; 771 772 memset(&gds_info, 0, sizeof(gds_info)); 773 gds_info.compute_partition_size = adev->gds.gds_size; 774 gds_info.gds_total_size = adev->gds.gds_size; 775 gds_info.gws_per_compute_partition = adev->gds.gws_size; 776 gds_info.oa_per_compute_partition = adev->gds.oa_size; 777 return copy_to_user(out, &gds_info, 778 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0; 779 } 780 case AMDGPU_INFO_VRAM_GTT: { 781 struct drm_amdgpu_info_vram_gtt vram_gtt; 782 783 vram_gtt.vram_size = adev->gmc.real_vram_size - 784 atomic64_read(&adev->vram_pin_size) - 785 AMDGPU_VM_RESERVED_VRAM; 786 vram_gtt.vram_cpu_accessible_size = 787 min(adev->gmc.visible_vram_size - 788 atomic64_read(&adev->visible_pin_size), 789 vram_gtt.vram_size); 790 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size; 791 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size); 792 return copy_to_user(out, &vram_gtt, 793 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; 794 } 795 case AMDGPU_INFO_MEMORY: { 796 struct drm_amdgpu_memory_info mem; 797 struct ttm_resource_manager *gtt_man = 798 &adev->mman.gtt_mgr.manager; 799 struct ttm_resource_manager *vram_man = 800 &adev->mman.vram_mgr.manager; 801 802 memset(&mem, 0, sizeof(mem)); 803 mem.vram.total_heap_size = adev->gmc.real_vram_size; 804 mem.vram.usable_heap_size = adev->gmc.real_vram_size - 805 atomic64_read(&adev->vram_pin_size) - 806 AMDGPU_VM_RESERVED_VRAM; 807 mem.vram.heap_usage = 808 ttm_resource_manager_usage(vram_man); 809 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4; 810 811 mem.cpu_accessible_vram.total_heap_size = 812 adev->gmc.visible_vram_size; 813 mem.cpu_accessible_vram.usable_heap_size = 814 min(adev->gmc.visible_vram_size - 815 atomic64_read(&adev->visible_pin_size), 816 mem.vram.usable_heap_size); 817 mem.cpu_accessible_vram.heap_usage = 818 amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr); 819 mem.cpu_accessible_vram.max_allocation = 820 mem.cpu_accessible_vram.usable_heap_size * 3 / 4; 821 822 mem.gtt.total_heap_size = gtt_man->size; 823 mem.gtt.usable_heap_size = mem.gtt.total_heap_size - 824 atomic64_read(&adev->gart_pin_size); 825 mem.gtt.heap_usage = ttm_resource_manager_usage(gtt_man); 826 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4; 827 828 return copy_to_user(out, &mem, 829 min((size_t)size, sizeof(mem))) 830 ? -EFAULT : 0; 831 } 832 case AMDGPU_INFO_READ_MMR_REG: { 833 int ret = 0; 834 unsigned int n, alloc_size; 835 uint32_t *regs; 836 unsigned int se_num = (info->read_mmr_reg.instance >> 837 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & 838 AMDGPU_INFO_MMR_SE_INDEX_MASK; 839 unsigned int sh_num = (info->read_mmr_reg.instance >> 840 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & 841 AMDGPU_INFO_MMR_SH_INDEX_MASK; 842 843 if (!down_read_trylock(&adev->reset_domain->sem)) 844 return -ENOENT; 845 846 /* set full masks if the userspace set all bits 847 * in the bitfields 848 */ 849 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) { 850 se_num = 0xffffffff; 851 } else if (se_num >= AMDGPU_GFX_MAX_SE) { 852 ret = -EINVAL; 853 goto out; 854 } 855 856 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) { 857 sh_num = 0xffffffff; 858 } else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE) { 859 ret = -EINVAL; 860 goto out; 861 } 862 863 if (info->read_mmr_reg.count > 128) { 864 ret = -EINVAL; 865 goto out; 866 } 867 868 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL); 869 if (!regs) { 870 ret = -ENOMEM; 871 goto out; 872 } 873 874 alloc_size = info->read_mmr_reg.count * sizeof(*regs); 875 876 amdgpu_gfx_off_ctrl(adev, false); 877 for (i = 0; i < info->read_mmr_reg.count; i++) { 878 if (amdgpu_asic_read_register(adev, se_num, sh_num, 879 info->read_mmr_reg.dword_offset + i, 880 ®s[i])) { 881 DRM_DEBUG_KMS("unallowed offset %#x\n", 882 info->read_mmr_reg.dword_offset + i); 883 kfree(regs); 884 amdgpu_gfx_off_ctrl(adev, true); 885 ret = -EFAULT; 886 goto out; 887 } 888 } 889 amdgpu_gfx_off_ctrl(adev, true); 890 n = copy_to_user(out, regs, min(size, alloc_size)); 891 kfree(regs); 892 ret = (n ? -EFAULT : 0); 893 out: 894 up_read(&adev->reset_domain->sem); 895 return ret; 896 } 897 case AMDGPU_INFO_DEV_INFO: { 898 struct drm_amdgpu_info_device *dev_info; 899 uint64_t vm_size; 900 uint32_t pcie_gen_mask, pcie_width_mask; 901 902 dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL); 903 if (!dev_info) 904 return -ENOMEM; 905 906 dev_info->device_id = adev->pdev->device; 907 dev_info->chip_rev = adev->rev_id; 908 dev_info->external_rev = adev->external_rev_id; 909 dev_info->pci_rev = adev->pdev->revision; 910 dev_info->family = adev->family; 911 dev_info->num_shader_engines = adev->gfx.config.max_shader_engines; 912 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 913 /* return all clocks in KHz */ 914 dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; 915 if (adev->pm.dpm_enabled) { 916 dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10; 917 dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10; 918 dev_info->min_engine_clock = amdgpu_dpm_get_sclk(adev, true) * 10; 919 dev_info->min_memory_clock = amdgpu_dpm_get_mclk(adev, true) * 10; 920 } else { 921 dev_info->max_engine_clock = 922 dev_info->min_engine_clock = 923 adev->clock.default_sclk * 10; 924 dev_info->max_memory_clock = 925 dev_info->min_memory_clock = 926 adev->clock.default_mclk * 10; 927 } 928 dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; 929 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se * 930 adev->gfx.config.max_shader_engines; 931 dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; 932 dev_info->ids_flags = 0; 933 if (adev->flags & AMD_IS_APU) 934 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION; 935 if (adev->gfx.mcbp) 936 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION; 937 if (amdgpu_is_tmz(adev)) 938 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ; 939 if (adev->gfx.config.ta_cntl2_truncate_coord_mode) 940 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD; 941 942 /* Gang submit is not supported under SRIOV currently */ 943 if (!amdgpu_sriov_vf(adev)) 944 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_GANG_SUBMIT; 945 946 if (amdgpu_passthrough(adev)) 947 dev_info->ids_flags |= (AMDGPU_IDS_FLAGS_MODE_PT << 948 AMDGPU_IDS_FLAGS_MODE_SHIFT) & 949 AMDGPU_IDS_FLAGS_MODE_MASK; 950 else if (amdgpu_sriov_vf(adev)) 951 dev_info->ids_flags |= (AMDGPU_IDS_FLAGS_MODE_VF << 952 AMDGPU_IDS_FLAGS_MODE_SHIFT) & 953 AMDGPU_IDS_FLAGS_MODE_MASK; 954 955 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 956 vm_size -= AMDGPU_VA_RESERVED_TOP; 957 958 /* Older VCE FW versions are buggy and can handle only 40bits */ 959 if (adev->vce.fw_version && 960 adev->vce.fw_version < AMDGPU_VCE_FW_53_45) 961 vm_size = min(vm_size, 1ULL << 40); 962 963 dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_BOTTOM; 964 dev_info->virtual_address_max = 965 min(vm_size, AMDGPU_GMC_HOLE_START); 966 967 if (vm_size > AMDGPU_GMC_HOLE_START) { 968 dev_info->high_va_offset = AMDGPU_GMC_HOLE_END; 969 dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size; 970 } 971 dev_info->virtual_address_alignment = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 972 dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE; 973 dev_info->gart_page_size = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 974 dev_info->cu_active_number = adev->gfx.cu_info.number; 975 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; 976 dev_info->ce_ram_size = adev->gfx.ce_ram_size; 977 memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0], 978 sizeof(adev->gfx.cu_info.ao_cu_bitmap)); 979 memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], 980 sizeof(dev_info->cu_bitmap)); 981 dev_info->vram_type = adev->gmc.vram_type; 982 dev_info->vram_bit_width = adev->gmc.vram_width; 983 dev_info->vce_harvest_config = adev->vce.harvest_config; 984 dev_info->gc_double_offchip_lds_buf = 985 adev->gfx.config.double_offchip_lds_buf; 986 dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size; 987 dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs; 988 dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh; 989 dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches; 990 dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth; 991 dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth; 992 dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads; 993 994 if (adev->family >= AMDGPU_FAMILY_NV) 995 dev_info->pa_sc_tile_steering_override = 996 adev->gfx.config.pa_sc_tile_steering_override; 997 998 dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask; 999 1000 /* Combine the chip gen mask with the platform (CPU/mobo) mask. */ 1001 pcie_gen_mask = adev->pm.pcie_gen_mask & 1002 (adev->pm.pcie_gen_mask >> CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT); 1003 pcie_width_mask = adev->pm.pcie_mlw_mask & 1004 (adev->pm.pcie_mlw_mask >> CAIL_PCIE_LINK_WIDTH_SUPPORT_SHIFT); 1005 dev_info->pcie_gen = fls(pcie_gen_mask); 1006 dev_info->pcie_num_lanes = 1007 pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X32 ? 32 : 1008 pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X16 ? 16 : 1009 pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X12 ? 12 : 1010 pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X8 ? 8 : 1011 pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X4 ? 4 : 1012 pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X2 ? 2 : 1; 1013 1014 dev_info->tcp_cache_size = adev->gfx.config.gc_tcp_l1_size; 1015 dev_info->num_sqc_per_wgp = adev->gfx.config.gc_num_sqc_per_wgp; 1016 dev_info->sqc_data_cache_size = adev->gfx.config.gc_l1_data_cache_size_per_sqc; 1017 dev_info->sqc_inst_cache_size = adev->gfx.config.gc_l1_instruction_cache_size_per_sqc; 1018 dev_info->gl1c_cache_size = adev->gfx.config.gc_gl1c_size_per_instance * 1019 adev->gfx.config.gc_gl1c_per_sa; 1020 dev_info->gl2c_cache_size = adev->gfx.config.gc_gl2c_per_gpu; 1021 dev_info->mall_size = adev->gmc.mall_size; 1022 1023 1024 if (adev->gfx.funcs->get_gfx_shadow_info) { 1025 struct amdgpu_gfx_shadow_info shadow_info; 1026 1027 ret = amdgpu_gfx_get_gfx_shadow_info(adev, &shadow_info); 1028 if (!ret) { 1029 dev_info->shadow_size = shadow_info.shadow_size; 1030 dev_info->shadow_alignment = shadow_info.shadow_alignment; 1031 dev_info->csa_size = shadow_info.csa_size; 1032 dev_info->csa_alignment = shadow_info.csa_alignment; 1033 } 1034 } 1035 1036 dev_info->userq_ip_mask = amdgpu_userq_get_supported_ip_mask(adev); 1037 1038 ret = copy_to_user(out, dev_info, 1039 min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0; 1040 kfree(dev_info); 1041 return ret; 1042 } 1043 case AMDGPU_INFO_VCE_CLOCK_TABLE: { 1044 unsigned int i; 1045 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {}; 1046 struct amd_vce_state *vce_state; 1047 1048 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) { 1049 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i); 1050 if (vce_state) { 1051 vce_clk_table.entries[i].sclk = vce_state->sclk; 1052 vce_clk_table.entries[i].mclk = vce_state->mclk; 1053 vce_clk_table.entries[i].eclk = vce_state->evclk; 1054 vce_clk_table.num_valid_entries++; 1055 } 1056 } 1057 1058 return copy_to_user(out, &vce_clk_table, 1059 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0; 1060 } 1061 case AMDGPU_INFO_VBIOS: { 1062 uint32_t bios_size = adev->bios_size; 1063 1064 switch (info->vbios_info.type) { 1065 case AMDGPU_INFO_VBIOS_SIZE: 1066 return copy_to_user(out, &bios_size, 1067 min((size_t)size, sizeof(bios_size))) 1068 ? -EFAULT : 0; 1069 case AMDGPU_INFO_VBIOS_IMAGE: { 1070 uint8_t *bios; 1071 uint32_t bios_offset = info->vbios_info.offset; 1072 1073 if (bios_offset >= bios_size) 1074 return -EINVAL; 1075 1076 bios = adev->bios + bios_offset; 1077 return copy_to_user(out, bios, 1078 min((size_t)size, (size_t)(bios_size - bios_offset))) 1079 ? -EFAULT : 0; 1080 } 1081 case AMDGPU_INFO_VBIOS_INFO: { 1082 struct drm_amdgpu_info_vbios vbios_info = {}; 1083 struct atom_context *atom_context; 1084 1085 atom_context = adev->mode_info.atom_context; 1086 if (atom_context) { 1087 memcpy(vbios_info.name, atom_context->name, 1088 sizeof(atom_context->name)); 1089 memcpy(vbios_info.vbios_pn, atom_context->vbios_pn, 1090 sizeof(atom_context->vbios_pn)); 1091 vbios_info.version = atom_context->version; 1092 memcpy(vbios_info.vbios_ver_str, atom_context->vbios_ver_str, 1093 sizeof(atom_context->vbios_ver_str)); 1094 memcpy(vbios_info.date, atom_context->date, 1095 sizeof(atom_context->date)); 1096 } 1097 1098 return copy_to_user(out, &vbios_info, 1099 min((size_t)size, sizeof(vbios_info))) ? -EFAULT : 0; 1100 } 1101 default: 1102 DRM_DEBUG_KMS("Invalid request %d\n", 1103 info->vbios_info.type); 1104 return -EINVAL; 1105 } 1106 } 1107 case AMDGPU_INFO_NUM_HANDLES: { 1108 struct drm_amdgpu_info_num_handles handle; 1109 1110 switch (info->query_hw_ip.type) { 1111 case AMDGPU_HW_IP_UVD: 1112 /* Starting Polaris, we support unlimited UVD handles */ 1113 if (adev->asic_type < CHIP_POLARIS10) { 1114 handle.uvd_max_handles = adev->uvd.max_handles; 1115 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev); 1116 1117 return copy_to_user(out, &handle, 1118 min((size_t)size, sizeof(handle))) ? -EFAULT : 0; 1119 } else { 1120 return -ENODATA; 1121 } 1122 1123 break; 1124 default: 1125 return -EINVAL; 1126 } 1127 } 1128 case AMDGPU_INFO_SENSOR: { 1129 if (!adev->pm.dpm_enabled) 1130 return -ENOENT; 1131 1132 switch (info->sensor_info.type) { 1133 case AMDGPU_INFO_SENSOR_GFX_SCLK: 1134 /* get sclk in Mhz */ 1135 if (amdgpu_dpm_read_sensor(adev, 1136 AMDGPU_PP_SENSOR_GFX_SCLK, 1137 (void *)&ui32, &ui32_size)) { 1138 return -EINVAL; 1139 } 1140 ui32 /= 100; 1141 break; 1142 case AMDGPU_INFO_SENSOR_GFX_MCLK: 1143 /* get mclk in Mhz */ 1144 if (amdgpu_dpm_read_sensor(adev, 1145 AMDGPU_PP_SENSOR_GFX_MCLK, 1146 (void *)&ui32, &ui32_size)) { 1147 return -EINVAL; 1148 } 1149 ui32 /= 100; 1150 break; 1151 case AMDGPU_INFO_SENSOR_GPU_TEMP: 1152 /* get temperature in millidegrees C */ 1153 if (amdgpu_dpm_read_sensor(adev, 1154 AMDGPU_PP_SENSOR_GPU_TEMP, 1155 (void *)&ui32, &ui32_size)) { 1156 return -EINVAL; 1157 } 1158 break; 1159 case AMDGPU_INFO_SENSOR_GPU_LOAD: 1160 /* get GPU load */ 1161 if (amdgpu_dpm_read_sensor(adev, 1162 AMDGPU_PP_SENSOR_GPU_LOAD, 1163 (void *)&ui32, &ui32_size)) { 1164 return -EINVAL; 1165 } 1166 break; 1167 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER: 1168 /* get average GPU power */ 1169 if (amdgpu_dpm_read_sensor(adev, 1170 AMDGPU_PP_SENSOR_GPU_AVG_POWER, 1171 (void *)&ui32, &ui32_size)) { 1172 /* fall back to input power for backwards compat */ 1173 if (amdgpu_dpm_read_sensor(adev, 1174 AMDGPU_PP_SENSOR_GPU_INPUT_POWER, 1175 (void *)&ui32, &ui32_size)) { 1176 return -EINVAL; 1177 } 1178 } 1179 ui32 >>= 8; 1180 break; 1181 case AMDGPU_INFO_SENSOR_GPU_INPUT_POWER: 1182 /* get input GPU power */ 1183 if (amdgpu_dpm_read_sensor(adev, 1184 AMDGPU_PP_SENSOR_GPU_INPUT_POWER, 1185 (void *)&ui32, &ui32_size)) { 1186 return -EINVAL; 1187 } 1188 ui32 >>= 8; 1189 break; 1190 case AMDGPU_INFO_SENSOR_VDDNB: 1191 /* get VDDNB in millivolts */ 1192 if (amdgpu_dpm_read_sensor(adev, 1193 AMDGPU_PP_SENSOR_VDDNB, 1194 (void *)&ui32, &ui32_size)) { 1195 return -EINVAL; 1196 } 1197 break; 1198 case AMDGPU_INFO_SENSOR_VDDGFX: 1199 /* get VDDGFX in millivolts */ 1200 if (amdgpu_dpm_read_sensor(adev, 1201 AMDGPU_PP_SENSOR_VDDGFX, 1202 (void *)&ui32, &ui32_size)) { 1203 return -EINVAL; 1204 } 1205 break; 1206 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK: 1207 /* get stable pstate sclk in Mhz */ 1208 if (amdgpu_dpm_read_sensor(adev, 1209 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 1210 (void *)&ui32, &ui32_size)) { 1211 return -EINVAL; 1212 } 1213 ui32 /= 100; 1214 break; 1215 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK: 1216 /* get stable pstate mclk in Mhz */ 1217 if (amdgpu_dpm_read_sensor(adev, 1218 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 1219 (void *)&ui32, &ui32_size)) { 1220 return -EINVAL; 1221 } 1222 ui32 /= 100; 1223 break; 1224 case AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK: 1225 /* get peak pstate sclk in Mhz */ 1226 if (amdgpu_dpm_read_sensor(adev, 1227 AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK, 1228 (void *)&ui32, &ui32_size)) { 1229 return -EINVAL; 1230 } 1231 ui32 /= 100; 1232 break; 1233 case AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK: 1234 /* get peak pstate mclk in Mhz */ 1235 if (amdgpu_dpm_read_sensor(adev, 1236 AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK, 1237 (void *)&ui32, &ui32_size)) { 1238 return -EINVAL; 1239 } 1240 ui32 /= 100; 1241 break; 1242 default: 1243 DRM_DEBUG_KMS("Invalid request %d\n", 1244 info->sensor_info.type); 1245 return -EINVAL; 1246 } 1247 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 1248 } 1249 case AMDGPU_INFO_VRAM_LOST_COUNTER: 1250 ui32 = atomic_read(&adev->vram_lost_counter); 1251 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 1252 case AMDGPU_INFO_RAS_ENABLED_FEATURES: { 1253 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1254 uint64_t ras_mask; 1255 1256 if (!ras) 1257 return -EINVAL; 1258 ras_mask = (uint64_t)adev->ras_enabled << 32 | ras->features; 1259 1260 return copy_to_user(out, &ras_mask, 1261 min_t(u64, size, sizeof(ras_mask))) ? 1262 -EFAULT : 0; 1263 } 1264 case AMDGPU_INFO_VIDEO_CAPS: { 1265 const struct amdgpu_video_codecs *codecs; 1266 struct drm_amdgpu_info_video_caps *caps; 1267 int r; 1268 1269 if (!adev->asic_funcs->query_video_codecs) 1270 return -EINVAL; 1271 1272 switch (info->video_cap.type) { 1273 case AMDGPU_INFO_VIDEO_CAPS_DECODE: 1274 r = amdgpu_asic_query_video_codecs(adev, false, &codecs); 1275 if (r) 1276 return -EINVAL; 1277 break; 1278 case AMDGPU_INFO_VIDEO_CAPS_ENCODE: 1279 r = amdgpu_asic_query_video_codecs(adev, true, &codecs); 1280 if (r) 1281 return -EINVAL; 1282 break; 1283 default: 1284 DRM_DEBUG_KMS("Invalid request %d\n", 1285 info->video_cap.type); 1286 return -EINVAL; 1287 } 1288 1289 caps = kzalloc(sizeof(*caps), GFP_KERNEL); 1290 if (!caps) 1291 return -ENOMEM; 1292 1293 for (i = 0; i < codecs->codec_count; i++) { 1294 int idx = codecs->codec_array[i].codec_type; 1295 1296 switch (idx) { 1297 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2: 1298 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4: 1299 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1: 1300 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC: 1301 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC: 1302 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG: 1303 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9: 1304 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1: 1305 caps->codec_info[idx].valid = 1; 1306 caps->codec_info[idx].max_width = 1307 codecs->codec_array[i].max_width; 1308 caps->codec_info[idx].max_height = 1309 codecs->codec_array[i].max_height; 1310 caps->codec_info[idx].max_pixels_per_frame = 1311 codecs->codec_array[i].max_pixels_per_frame; 1312 caps->codec_info[idx].max_level = 1313 codecs->codec_array[i].max_level; 1314 break; 1315 default: 1316 break; 1317 } 1318 } 1319 r = copy_to_user(out, caps, 1320 min((size_t)size, sizeof(*caps))) ? -EFAULT : 0; 1321 kfree(caps); 1322 return r; 1323 } 1324 case AMDGPU_INFO_MAX_IBS: { 1325 uint32_t max_ibs[AMDGPU_HW_IP_NUM]; 1326 1327 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) 1328 max_ibs[i] = amdgpu_ring_max_ibs(i); 1329 1330 return copy_to_user(out, max_ibs, 1331 min((size_t)size, sizeof(max_ibs))) ? -EFAULT : 0; 1332 } 1333 case AMDGPU_INFO_GPUVM_FAULT: { 1334 struct amdgpu_fpriv *fpriv = filp->driver_priv; 1335 struct amdgpu_vm *vm = &fpriv->vm; 1336 struct drm_amdgpu_info_gpuvm_fault gpuvm_fault; 1337 unsigned long flags; 1338 1339 if (!vm) 1340 return -EINVAL; 1341 1342 memset(&gpuvm_fault, 0, sizeof(gpuvm_fault)); 1343 1344 xa_lock_irqsave(&adev->vm_manager.pasids, flags); 1345 gpuvm_fault.addr = vm->fault_info.addr; 1346 gpuvm_fault.status = vm->fault_info.status; 1347 gpuvm_fault.vmhub = vm->fault_info.vmhub; 1348 xa_unlock_irqrestore(&adev->vm_manager.pasids, flags); 1349 1350 return copy_to_user(out, &gpuvm_fault, 1351 min((size_t)size, sizeof(gpuvm_fault))) ? -EFAULT : 0; 1352 } 1353 case AMDGPU_INFO_UQ_FW_AREAS: { 1354 struct drm_amdgpu_info_uq_metadata meta_info = {}; 1355 1356 switch (info->query_hw_ip.type) { 1357 case AMDGPU_HW_IP_GFX: 1358 ret = amdgpu_userq_metadata_info_gfx(adev, info, &meta_info.gfx); 1359 if (ret) 1360 return ret; 1361 1362 ret = copy_to_user(out, &meta_info, 1363 min((size_t)size, sizeof(meta_info))) ? -EFAULT : 0; 1364 return 0; 1365 default: 1366 return -EINVAL; 1367 } 1368 } 1369 default: 1370 DRM_DEBUG_KMS("Invalid request %d\n", info->query); 1371 return -EINVAL; 1372 } 1373 return 0; 1374 } 1375 1376 /** 1377 * amdgpu_driver_open_kms - drm callback for open 1378 * 1379 * @dev: drm dev pointer 1380 * @file_priv: drm file 1381 * 1382 * On device open, init vm on cayman+ (all asics). 1383 * Returns 0 on success, error on failure. 1384 */ 1385 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 1386 { 1387 struct amdgpu_device *adev = drm_to_adev(dev); 1388 struct amdgpu_fpriv *fpriv; 1389 int r, pasid; 1390 1391 /* Ensure IB tests are run on ring */ 1392 flush_delayed_work(&adev->delayed_init_work); 1393 1394 1395 if (amdgpu_ras_intr_triggered()) { 1396 DRM_ERROR("RAS Intr triggered, device disabled!!"); 1397 return -EHWPOISON; 1398 } 1399 1400 file_priv->driver_priv = NULL; 1401 1402 r = pm_runtime_get_sync(dev->dev); 1403 if (r < 0) 1404 goto pm_put; 1405 1406 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 1407 if (unlikely(!fpriv)) { 1408 r = -ENOMEM; 1409 goto out_suspend; 1410 } 1411 1412 pasid = amdgpu_pasid_alloc(16); 1413 if (pasid < 0) { 1414 dev_warn(adev->dev, "No more PASIDs available!"); 1415 pasid = 0; 1416 } 1417 1418 r = amdgpu_xcp_open_device(adev, fpriv, file_priv); 1419 if (r) 1420 goto error_pasid; 1421 1422 amdgpu_debugfs_vm_init(file_priv); 1423 1424 r = amdgpu_vm_init(adev, &fpriv->vm, fpriv->xcp_id, pasid); 1425 if (r) 1426 goto error_pasid; 1427 1428 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL); 1429 if (!fpriv->prt_va) { 1430 r = -ENOMEM; 1431 goto error_vm; 1432 } 1433 1434 if (adev->gfx.mcbp) { 1435 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK; 1436 1437 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj, 1438 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE); 1439 if (r) 1440 goto error_vm; 1441 } 1442 1443 r = amdgpu_seq64_map(adev, &fpriv->vm, &fpriv->seq64_va); 1444 if (r) 1445 goto error_vm; 1446 1447 mutex_init(&fpriv->bo_list_lock); 1448 idr_init_base(&fpriv->bo_list_handles, 1); 1449 1450 r = amdgpu_userq_mgr_init(&fpriv->userq_mgr, file_priv, adev); 1451 if (r) 1452 DRM_WARN("Can't setup usermode queues, use legacy workload submission only\n"); 1453 1454 r = amdgpu_eviction_fence_init(&fpriv->evf_mgr); 1455 if (r) 1456 goto error_vm; 1457 1458 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr, adev); 1459 1460 file_priv->driver_priv = fpriv; 1461 goto out_suspend; 1462 1463 error_vm: 1464 amdgpu_vm_fini(adev, &fpriv->vm); 1465 1466 error_pasid: 1467 if (pasid) 1468 amdgpu_pasid_free(pasid); 1469 1470 kfree(fpriv); 1471 1472 out_suspend: 1473 pm_runtime_mark_last_busy(dev->dev); 1474 pm_put: 1475 pm_runtime_put_autosuspend(dev->dev); 1476 1477 return r; 1478 } 1479 1480 /** 1481 * amdgpu_driver_postclose_kms - drm callback for post close 1482 * 1483 * @dev: drm dev pointer 1484 * @file_priv: drm file 1485 * 1486 * On device post close, tear down vm on cayman+ (all asics). 1487 */ 1488 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1489 struct drm_file *file_priv) 1490 { 1491 struct amdgpu_device *adev = drm_to_adev(dev); 1492 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1493 struct amdgpu_bo_list *list; 1494 struct amdgpu_bo *pd; 1495 u32 pasid; 1496 int handle; 1497 1498 if (!fpriv) 1499 return; 1500 1501 pm_runtime_get_sync(dev->dev); 1502 1503 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL) 1504 amdgpu_uvd_free_handles(adev, file_priv); 1505 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL) 1506 amdgpu_vce_free_handles(adev, file_priv); 1507 1508 if (fpriv->csa_va) { 1509 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK; 1510 1511 WARN_ON(amdgpu_unmap_static_csa(adev, &fpriv->vm, adev->virt.csa_obj, 1512 fpriv->csa_va, csa_addr)); 1513 fpriv->csa_va = NULL; 1514 } 1515 1516 amdgpu_seq64_unmap(adev, fpriv); 1517 1518 pasid = fpriv->vm.pasid; 1519 pd = amdgpu_bo_ref(fpriv->vm.root.bo); 1520 if (!WARN_ON(amdgpu_bo_reserve(pd, true))) { 1521 amdgpu_vm_bo_del(adev, fpriv->prt_va); 1522 amdgpu_bo_unreserve(pd); 1523 } 1524 1525 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); 1526 amdgpu_vm_fini(adev, &fpriv->vm); 1527 1528 if (pasid) 1529 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid); 1530 amdgpu_bo_unref(&pd); 1531 1532 idr_for_each_entry(&fpriv->bo_list_handles, list, handle) 1533 amdgpu_bo_list_put(list); 1534 1535 idr_destroy(&fpriv->bo_list_handles); 1536 mutex_destroy(&fpriv->bo_list_lock); 1537 1538 kfree(fpriv); 1539 file_priv->driver_priv = NULL; 1540 1541 pm_runtime_mark_last_busy(dev->dev); 1542 pm_runtime_put_autosuspend(dev->dev); 1543 } 1544 1545 1546 void amdgpu_driver_release_kms(struct drm_device *dev) 1547 { 1548 struct amdgpu_device *adev = drm_to_adev(dev); 1549 1550 amdgpu_device_fini_sw(adev); 1551 pci_set_drvdata(adev->pdev, NULL); 1552 } 1553 1554 /* 1555 * VBlank related functions. 1556 */ 1557 /** 1558 * amdgpu_get_vblank_counter_kms - get frame count 1559 * 1560 * @crtc: crtc to get the frame count from 1561 * 1562 * Gets the frame count on the requested crtc (all asics). 1563 * Returns frame count on success, -EINVAL on failure. 1564 */ 1565 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc) 1566 { 1567 struct drm_device *dev = crtc->dev; 1568 unsigned int pipe = crtc->index; 1569 struct amdgpu_device *adev = drm_to_adev(dev); 1570 int vpos, hpos, stat; 1571 u32 count; 1572 1573 if (pipe >= adev->mode_info.num_crtc) { 1574 DRM_ERROR("Invalid crtc %u\n", pipe); 1575 return -EINVAL; 1576 } 1577 1578 /* The hw increments its frame counter at start of vsync, not at start 1579 * of vblank, as is required by DRM core vblank counter handling. 1580 * Cook the hw count here to make it appear to the caller as if it 1581 * incremented at start of vblank. We measure distance to start of 1582 * vblank in vpos. vpos therefore will be >= 0 between start of vblank 1583 * and start of vsync, so vpos >= 0 means to bump the hw frame counter 1584 * result by 1 to give the proper appearance to caller. 1585 */ 1586 if (adev->mode_info.crtcs[pipe]) { 1587 /* Repeat readout if needed to provide stable result if 1588 * we cross start of vsync during the queries. 1589 */ 1590 do { 1591 count = amdgpu_display_vblank_get_counter(adev, pipe); 1592 /* Ask amdgpu_display_get_crtc_scanoutpos to return 1593 * vpos as distance to start of vblank, instead of 1594 * regular vertical scanout pos. 1595 */ 1596 stat = amdgpu_display_get_crtc_scanoutpos( 1597 dev, pipe, GET_DISTANCE_TO_VBLANKSTART, 1598 &vpos, &hpos, NULL, NULL, 1599 &adev->mode_info.crtcs[pipe]->base.hwmode); 1600 } while (count != amdgpu_display_vblank_get_counter(adev, pipe)); 1601 1602 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 1603 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 1604 DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 1605 } else { 1606 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", 1607 pipe, vpos); 1608 1609 /* Bump counter if we are at >= leading edge of vblank, 1610 * but before vsync where vpos would turn negative and 1611 * the hw counter really increments. 1612 */ 1613 if (vpos >= 0) 1614 count++; 1615 } 1616 } else { 1617 /* Fallback to use value as is. */ 1618 count = amdgpu_display_vblank_get_counter(adev, pipe); 1619 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 1620 } 1621 1622 return count; 1623 } 1624 1625 /** 1626 * amdgpu_enable_vblank_kms - enable vblank interrupt 1627 * 1628 * @crtc: crtc to enable vblank interrupt for 1629 * 1630 * Enable the interrupt on the requested crtc (all asics). 1631 * Returns 0 on success, -EINVAL on failure. 1632 */ 1633 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc) 1634 { 1635 struct drm_device *dev = crtc->dev; 1636 unsigned int pipe = crtc->index; 1637 struct amdgpu_device *adev = drm_to_adev(dev); 1638 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1639 1640 return amdgpu_irq_get(adev, &adev->crtc_irq, idx); 1641 } 1642 1643 /** 1644 * amdgpu_disable_vblank_kms - disable vblank interrupt 1645 * 1646 * @crtc: crtc to disable vblank interrupt for 1647 * 1648 * Disable the interrupt on the requested crtc (all asics). 1649 */ 1650 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc) 1651 { 1652 struct drm_device *dev = crtc->dev; 1653 unsigned int pipe = crtc->index; 1654 struct amdgpu_device *adev = drm_to_adev(dev); 1655 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1656 1657 amdgpu_irq_put(adev, &adev->crtc_irq, idx); 1658 } 1659 1660 /* 1661 * Debugfs info 1662 */ 1663 #if defined(CONFIG_DEBUG_FS) 1664 1665 static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused) 1666 { 1667 struct amdgpu_device *adev = m->private; 1668 struct drm_amdgpu_info_firmware fw_info; 1669 struct drm_amdgpu_query_fw query_fw; 1670 struct atom_context *ctx = adev->mode_info.atom_context; 1671 uint8_t smu_program, smu_major, smu_minor, smu_debug; 1672 int ret, i; 1673 1674 static const char *ta_fw_name[TA_FW_TYPE_MAX_INDEX] = { 1675 #define TA_FW_NAME(type)[TA_FW_TYPE_PSP_##type] = #type 1676 TA_FW_NAME(XGMI), 1677 TA_FW_NAME(RAS), 1678 TA_FW_NAME(HDCP), 1679 TA_FW_NAME(DTM), 1680 TA_FW_NAME(RAP), 1681 TA_FW_NAME(SECUREDISPLAY), 1682 #undef TA_FW_NAME 1683 }; 1684 1685 /* VCE */ 1686 query_fw.fw_type = AMDGPU_INFO_FW_VCE; 1687 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1688 if (ret) 1689 return ret; 1690 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n", 1691 fw_info.feature, fw_info.ver); 1692 1693 /* UVD */ 1694 query_fw.fw_type = AMDGPU_INFO_FW_UVD; 1695 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1696 if (ret) 1697 return ret; 1698 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n", 1699 fw_info.feature, fw_info.ver); 1700 1701 /* GMC */ 1702 query_fw.fw_type = AMDGPU_INFO_FW_GMC; 1703 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1704 if (ret) 1705 return ret; 1706 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n", 1707 fw_info.feature, fw_info.ver); 1708 1709 /* ME */ 1710 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME; 1711 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1712 if (ret) 1713 return ret; 1714 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n", 1715 fw_info.feature, fw_info.ver); 1716 1717 /* PFP */ 1718 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP; 1719 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1720 if (ret) 1721 return ret; 1722 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n", 1723 fw_info.feature, fw_info.ver); 1724 1725 /* CE */ 1726 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE; 1727 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1728 if (ret) 1729 return ret; 1730 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n", 1731 fw_info.feature, fw_info.ver); 1732 1733 /* RLC */ 1734 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC; 1735 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1736 if (ret) 1737 return ret; 1738 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n", 1739 fw_info.feature, fw_info.ver); 1740 1741 /* RLC SAVE RESTORE LIST CNTL */ 1742 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL; 1743 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1744 if (ret) 1745 return ret; 1746 seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n", 1747 fw_info.feature, fw_info.ver); 1748 1749 /* RLC SAVE RESTORE LIST GPM MEM */ 1750 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM; 1751 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1752 if (ret) 1753 return ret; 1754 seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n", 1755 fw_info.feature, fw_info.ver); 1756 1757 /* RLC SAVE RESTORE LIST SRM MEM */ 1758 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM; 1759 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1760 if (ret) 1761 return ret; 1762 seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n", 1763 fw_info.feature, fw_info.ver); 1764 1765 /* RLCP */ 1766 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCP; 1767 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1768 if (ret) 1769 return ret; 1770 seq_printf(m, "RLCP feature version: %u, firmware version: 0x%08x\n", 1771 fw_info.feature, fw_info.ver); 1772 1773 /* RLCV */ 1774 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCV; 1775 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1776 if (ret) 1777 return ret; 1778 seq_printf(m, "RLCV feature version: %u, firmware version: 0x%08x\n", 1779 fw_info.feature, fw_info.ver); 1780 1781 /* MEC */ 1782 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC; 1783 query_fw.index = 0; 1784 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1785 if (ret) 1786 return ret; 1787 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n", 1788 fw_info.feature, fw_info.ver); 1789 1790 /* MEC2 */ 1791 if (adev->gfx.mec2_fw) { 1792 query_fw.index = 1; 1793 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1794 if (ret) 1795 return ret; 1796 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n", 1797 fw_info.feature, fw_info.ver); 1798 } 1799 1800 /* IMU */ 1801 query_fw.fw_type = AMDGPU_INFO_FW_IMU; 1802 query_fw.index = 0; 1803 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1804 if (ret) 1805 return ret; 1806 seq_printf(m, "IMU feature version: %u, firmware version: 0x%08x\n", 1807 fw_info.feature, fw_info.ver); 1808 1809 /* PSP SOS */ 1810 query_fw.fw_type = AMDGPU_INFO_FW_SOS; 1811 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1812 if (ret) 1813 return ret; 1814 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n", 1815 fw_info.feature, fw_info.ver); 1816 1817 1818 /* PSP ASD */ 1819 query_fw.fw_type = AMDGPU_INFO_FW_ASD; 1820 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1821 if (ret) 1822 return ret; 1823 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n", 1824 fw_info.feature, fw_info.ver); 1825 1826 query_fw.fw_type = AMDGPU_INFO_FW_TA; 1827 for (i = TA_FW_TYPE_PSP_XGMI; i < TA_FW_TYPE_MAX_INDEX; i++) { 1828 query_fw.index = i; 1829 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1830 if (ret) 1831 continue; 1832 1833 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n", 1834 ta_fw_name[i], fw_info.feature, fw_info.ver); 1835 } 1836 1837 /* SMC */ 1838 query_fw.fw_type = AMDGPU_INFO_FW_SMC; 1839 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1840 if (ret) 1841 return ret; 1842 smu_program = (fw_info.ver >> 24) & 0xff; 1843 smu_major = (fw_info.ver >> 16) & 0xff; 1844 smu_minor = (fw_info.ver >> 8) & 0xff; 1845 smu_debug = (fw_info.ver >> 0) & 0xff; 1846 seq_printf(m, "SMC feature version: %u, program: %d, firmware version: 0x%08x (%d.%d.%d)\n", 1847 fw_info.feature, smu_program, fw_info.ver, smu_major, smu_minor, smu_debug); 1848 1849 /* SDMA */ 1850 query_fw.fw_type = AMDGPU_INFO_FW_SDMA; 1851 for (i = 0; i < adev->sdma.num_instances; i++) { 1852 query_fw.index = i; 1853 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1854 if (ret) 1855 return ret; 1856 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n", 1857 i, fw_info.feature, fw_info.ver); 1858 } 1859 1860 /* VCN */ 1861 query_fw.fw_type = AMDGPU_INFO_FW_VCN; 1862 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1863 if (ret) 1864 return ret; 1865 seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n", 1866 fw_info.feature, fw_info.ver); 1867 1868 /* DMCU */ 1869 query_fw.fw_type = AMDGPU_INFO_FW_DMCU; 1870 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1871 if (ret) 1872 return ret; 1873 seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n", 1874 fw_info.feature, fw_info.ver); 1875 1876 /* DMCUB */ 1877 query_fw.fw_type = AMDGPU_INFO_FW_DMCUB; 1878 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1879 if (ret) 1880 return ret; 1881 seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n", 1882 fw_info.feature, fw_info.ver); 1883 1884 /* TOC */ 1885 query_fw.fw_type = AMDGPU_INFO_FW_TOC; 1886 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1887 if (ret) 1888 return ret; 1889 seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n", 1890 fw_info.feature, fw_info.ver); 1891 1892 /* CAP */ 1893 if (adev->psp.cap_fw) { 1894 query_fw.fw_type = AMDGPU_INFO_FW_CAP; 1895 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1896 if (ret) 1897 return ret; 1898 seq_printf(m, "CAP feature version: %u, firmware version: 0x%08x\n", 1899 fw_info.feature, fw_info.ver); 1900 } 1901 1902 /* MES_KIQ */ 1903 query_fw.fw_type = AMDGPU_INFO_FW_MES_KIQ; 1904 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1905 if (ret) 1906 return ret; 1907 seq_printf(m, "MES_KIQ feature version: %u, firmware version: 0x%08x\n", 1908 fw_info.feature, fw_info.ver); 1909 1910 /* MES */ 1911 query_fw.fw_type = AMDGPU_INFO_FW_MES; 1912 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1913 if (ret) 1914 return ret; 1915 seq_printf(m, "MES feature version: %u, firmware version: 0x%08x\n", 1916 fw_info.feature, fw_info.ver); 1917 1918 /* VPE */ 1919 query_fw.fw_type = AMDGPU_INFO_FW_VPE; 1920 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1921 if (ret) 1922 return ret; 1923 seq_printf(m, "VPE feature version: %u, firmware version: 0x%08x\n", 1924 fw_info.feature, fw_info.ver); 1925 1926 seq_printf(m, "VBIOS version: %s\n", ctx->vbios_pn); 1927 1928 return 0; 1929 } 1930 1931 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_firmware_info); 1932 1933 #endif 1934 1935 void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev) 1936 { 1937 #if defined(CONFIG_DEBUG_FS) 1938 struct drm_minor *minor = adev_to_drm(adev)->primary; 1939 struct dentry *root = minor->debugfs_root; 1940 1941 debugfs_create_file("amdgpu_firmware_info", 0444, root, 1942 adev, &amdgpu_debugfs_firmware_info_fops); 1943 1944 #endif 1945 } 1946