1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include "amdgpu.h" 30 #include <drm/amdgpu_drm.h> 31 #include <drm/clients/drm_fbdev_helper.h> 32 #include <drm/drm_drv.h> 33 #include <drm/drm_vblank.h> 34 #include "amdgpu_uvd.h" 35 #include "amdgpu_vce.h" 36 #include "atom.h" 37 38 #include <linux/vga_switcheroo.h> 39 #include <linux/slab.h> 40 #include <linux/uaccess.h> 41 #include <linux/pci.h> 42 #include <linux/pm_runtime.h> 43 #include "amdgpu_amdkfd.h" 44 #include "amdgpu_gem.h" 45 #include "amdgpu_display.h" 46 #include "amdgpu_ras.h" 47 #include "amdgpu_reset.h" 48 #include "amd_pcie.h" 49 #include "amdgpu_userq.h" 50 #include "amdgpu_video_codecs.h" 51 #include "amdgpu_ras_mgr.h" 52 53 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev) 54 { 55 struct amdgpu_gpu_instance *gpu_instance; 56 int i; 57 58 mutex_lock(&mgpu_info.mutex); 59 60 for (i = 0; i < mgpu_info.num_gpu; i++) { 61 gpu_instance = &(mgpu_info.gpu_ins[i]); 62 if (gpu_instance->adev == adev) { 63 mgpu_info.gpu_ins[i] = 64 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1]; 65 mgpu_info.num_gpu--; 66 if (adev->flags & AMD_IS_APU) 67 mgpu_info.num_apu--; 68 else 69 mgpu_info.num_dgpu--; 70 break; 71 } 72 } 73 74 mutex_unlock(&mgpu_info.mutex); 75 } 76 77 /** 78 * amdgpu_driver_unload_kms - Main unload function for KMS. 79 * 80 * @dev: drm dev pointer 81 * 82 * This is the main unload function for KMS (all asics). 83 * Returns 0 on success. 84 */ 85 void amdgpu_driver_unload_kms(struct drm_device *dev) 86 { 87 struct amdgpu_device *adev = drm_to_adev(dev); 88 89 if (adev == NULL || !adev->num_ip_blocks) 90 return; 91 92 amdgpu_unregister_gpu_instance(adev); 93 94 if (adev->rmmio == NULL) 95 return; 96 97 if (amdgpu_acpi_smart_shift_update(adev, AMDGPU_SS_DRV_UNLOAD)) 98 drm_warn(dev, "smart shift update failed\n"); 99 100 amdgpu_acpi_fini(adev); 101 amdgpu_device_fini_hw(adev); 102 } 103 104 void amdgpu_register_gpu_instance(struct amdgpu_device *adev) 105 { 106 struct amdgpu_gpu_instance *gpu_instance; 107 108 mutex_lock(&mgpu_info.mutex); 109 110 if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) { 111 drm_err(adev_to_drm(adev), "Cannot register more gpu instance\n"); 112 mutex_unlock(&mgpu_info.mutex); 113 return; 114 } 115 116 gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]); 117 gpu_instance->adev = adev; 118 gpu_instance->mgpu_fan_enabled = 0; 119 120 mgpu_info.num_gpu++; 121 if (adev->flags & AMD_IS_APU) 122 mgpu_info.num_apu++; 123 else 124 mgpu_info.num_dgpu++; 125 126 mutex_unlock(&mgpu_info.mutex); 127 } 128 129 /** 130 * amdgpu_driver_load_kms - Main load function for KMS. 131 * 132 * @adev: pointer to struct amdgpu_device 133 * @flags: device flags 134 * 135 * This is the main load function for KMS (all asics). 136 * Returns 0 on success, error on failure. 137 */ 138 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags) 139 { 140 struct drm_device *dev; 141 int r, acpi_status; 142 143 dev = adev_to_drm(adev); 144 145 /* amdgpu_device_init should report only fatal error 146 * like memory allocation failure or iomapping failure, 147 * or memory manager initialization failure, it must 148 * properly initialize the GPU MC controller and permit 149 * VRAM allocation 150 */ 151 r = amdgpu_device_init(adev, flags); 152 if (r) { 153 dev_err(dev->dev, "Fatal error during GPU init\n"); 154 goto out; 155 } 156 157 amdgpu_device_detect_runtime_pm_mode(adev); 158 159 /* Call ACPI methods: require modeset init 160 * but failure is not fatal 161 */ 162 163 acpi_status = amdgpu_acpi_init(adev); 164 if (acpi_status) 165 dev_dbg(dev->dev, "Error during ACPI methods call\n"); 166 167 if (amdgpu_acpi_smart_shift_update(adev, AMDGPU_SS_DRV_LOAD)) 168 drm_warn(dev, "smart shift update failed\n"); 169 170 out: 171 if (r) 172 amdgpu_driver_unload_kms(dev); 173 174 return r; 175 } 176 177 static enum amd_ip_block_type 178 amdgpu_ip_get_block_type(struct amdgpu_device *adev, uint32_t ip) 179 { 180 enum amd_ip_block_type type; 181 182 switch (ip) { 183 case AMDGPU_HW_IP_GFX: 184 type = AMD_IP_BLOCK_TYPE_GFX; 185 break; 186 case AMDGPU_HW_IP_COMPUTE: 187 type = AMD_IP_BLOCK_TYPE_GFX; 188 break; 189 case AMDGPU_HW_IP_DMA: 190 type = AMD_IP_BLOCK_TYPE_SDMA; 191 break; 192 case AMDGPU_HW_IP_UVD: 193 case AMDGPU_HW_IP_UVD_ENC: 194 type = AMD_IP_BLOCK_TYPE_UVD; 195 break; 196 case AMDGPU_HW_IP_VCE: 197 type = AMD_IP_BLOCK_TYPE_VCE; 198 break; 199 case AMDGPU_HW_IP_VCN_DEC: 200 case AMDGPU_HW_IP_VCN_ENC: 201 type = AMD_IP_BLOCK_TYPE_VCN; 202 break; 203 case AMDGPU_HW_IP_VCN_JPEG: 204 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 205 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 206 break; 207 case AMDGPU_HW_IP_VPE: 208 type = AMD_IP_BLOCK_TYPE_VPE; 209 break; 210 default: 211 type = AMD_IP_BLOCK_TYPE_NUM; 212 break; 213 } 214 215 return type; 216 } 217 218 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, 219 struct drm_amdgpu_query_fw *query_fw, 220 struct amdgpu_device *adev) 221 { 222 switch (query_fw->fw_type) { 223 case AMDGPU_INFO_FW_VCE: 224 fw_info->ver = adev->vce.fw_version; 225 fw_info->feature = adev->vce.fb_version; 226 break; 227 case AMDGPU_INFO_FW_UVD: 228 fw_info->ver = adev->uvd.fw_version; 229 fw_info->feature = 0; 230 break; 231 case AMDGPU_INFO_FW_VCN: 232 fw_info->ver = adev->vcn.fw_version; 233 fw_info->feature = 0; 234 break; 235 case AMDGPU_INFO_FW_GMC: 236 fw_info->ver = adev->gmc.fw_version; 237 fw_info->feature = 0; 238 break; 239 case AMDGPU_INFO_FW_GFX_ME: 240 fw_info->ver = adev->gfx.me_fw_version; 241 fw_info->feature = adev->gfx.me_feature_version; 242 break; 243 case AMDGPU_INFO_FW_GFX_PFP: 244 fw_info->ver = adev->gfx.pfp_fw_version; 245 fw_info->feature = adev->gfx.pfp_feature_version; 246 break; 247 case AMDGPU_INFO_FW_GFX_CE: 248 fw_info->ver = adev->gfx.ce_fw_version; 249 fw_info->feature = adev->gfx.ce_feature_version; 250 break; 251 case AMDGPU_INFO_FW_GFX_RLC: 252 fw_info->ver = adev->gfx.rlc_fw_version; 253 fw_info->feature = adev->gfx.rlc_feature_version; 254 break; 255 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL: 256 fw_info->ver = adev->gfx.rlc_srlc_fw_version; 257 fw_info->feature = adev->gfx.rlc_srlc_feature_version; 258 break; 259 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM: 260 fw_info->ver = adev->gfx.rlc_srlg_fw_version; 261 fw_info->feature = adev->gfx.rlc_srlg_feature_version; 262 break; 263 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM: 264 fw_info->ver = adev->gfx.rlc_srls_fw_version; 265 fw_info->feature = adev->gfx.rlc_srls_feature_version; 266 break; 267 case AMDGPU_INFO_FW_GFX_RLCP: 268 fw_info->ver = adev->gfx.rlcp_ucode_version; 269 fw_info->feature = adev->gfx.rlcp_ucode_feature_version; 270 break; 271 case AMDGPU_INFO_FW_GFX_RLCV: 272 fw_info->ver = adev->gfx.rlcv_ucode_version; 273 fw_info->feature = adev->gfx.rlcv_ucode_feature_version; 274 break; 275 case AMDGPU_INFO_FW_GFX_MEC: 276 if (query_fw->index == 0) { 277 fw_info->ver = adev->gfx.mec_fw_version; 278 fw_info->feature = adev->gfx.mec_feature_version; 279 } else if (query_fw->index == 1) { 280 fw_info->ver = adev->gfx.mec2_fw_version; 281 fw_info->feature = adev->gfx.mec2_feature_version; 282 } else 283 return -EINVAL; 284 break; 285 case AMDGPU_INFO_FW_SMC: 286 fw_info->ver = adev->pm.fw_version; 287 fw_info->feature = 0; 288 break; 289 case AMDGPU_INFO_FW_MP5: 290 fw_info->ver = adev->pm.mp5_fw_version; 291 fw_info->feature = 0; 292 break; 293 case AMDGPU_INFO_FW_TA: 294 switch (query_fw->index) { 295 case TA_FW_TYPE_PSP_XGMI: 296 fw_info->ver = adev->psp.xgmi_context.context.bin_desc.fw_version; 297 fw_info->feature = adev->psp.xgmi_context.context 298 .bin_desc.feature_version; 299 break; 300 case TA_FW_TYPE_PSP_RAS: 301 fw_info->ver = adev->psp.ras_context.context.bin_desc.fw_version; 302 fw_info->feature = adev->psp.ras_context.context 303 .bin_desc.feature_version; 304 break; 305 case TA_FW_TYPE_PSP_HDCP: 306 fw_info->ver = adev->psp.hdcp_context.context.bin_desc.fw_version; 307 fw_info->feature = adev->psp.hdcp_context.context 308 .bin_desc.feature_version; 309 break; 310 case TA_FW_TYPE_PSP_DTM: 311 fw_info->ver = adev->psp.dtm_context.context.bin_desc.fw_version; 312 fw_info->feature = adev->psp.dtm_context.context 313 .bin_desc.feature_version; 314 break; 315 case TA_FW_TYPE_PSP_RAP: 316 fw_info->ver = adev->psp.rap_context.context.bin_desc.fw_version; 317 fw_info->feature = adev->psp.rap_context.context 318 .bin_desc.feature_version; 319 break; 320 case TA_FW_TYPE_PSP_SECUREDISPLAY: 321 fw_info->ver = adev->psp.securedisplay_context.context.bin_desc.fw_version; 322 fw_info->feature = 323 adev->psp.securedisplay_context.context.bin_desc 324 .feature_version; 325 break; 326 default: 327 return -EINVAL; 328 } 329 break; 330 case AMDGPU_INFO_FW_SDMA: 331 if (query_fw->index >= adev->sdma.num_instances) 332 return -EINVAL; 333 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version; 334 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version; 335 break; 336 case AMDGPU_INFO_FW_SOS: 337 fw_info->ver = adev->psp.sos.fw_version; 338 fw_info->feature = adev->psp.sos.feature_version; 339 break; 340 case AMDGPU_INFO_FW_ASD: 341 fw_info->ver = adev->psp.asd_context.bin_desc.fw_version; 342 fw_info->feature = adev->psp.asd_context.bin_desc.feature_version; 343 break; 344 case AMDGPU_INFO_FW_DMCU: 345 fw_info->ver = adev->dm.dmcu_fw_version; 346 fw_info->feature = 0; 347 break; 348 case AMDGPU_INFO_FW_DMCUB: 349 fw_info->ver = adev->dm.dmcub_fw_version; 350 fw_info->feature = 0; 351 break; 352 case AMDGPU_INFO_FW_TOC: 353 fw_info->ver = adev->psp.toc.fw_version; 354 fw_info->feature = adev->psp.toc.feature_version; 355 break; 356 case AMDGPU_INFO_FW_CAP: 357 fw_info->ver = adev->psp.cap.fw_version; 358 fw_info->feature = adev->psp.cap.feature_version; 359 break; 360 case AMDGPU_INFO_FW_MES_KIQ: 361 fw_info->ver = adev->mes.kiq_version & AMDGPU_MES_VERSION_MASK; 362 fw_info->feature = (adev->mes.kiq_version & AMDGPU_MES_FEAT_VERSION_MASK) 363 >> AMDGPU_MES_FEAT_VERSION_SHIFT; 364 break; 365 case AMDGPU_INFO_FW_MES: 366 fw_info->ver = adev->mes.sched_version & AMDGPU_MES_VERSION_MASK; 367 fw_info->feature = (adev->mes.sched_version & AMDGPU_MES_FEAT_VERSION_MASK) 368 >> AMDGPU_MES_FEAT_VERSION_SHIFT; 369 break; 370 case AMDGPU_INFO_FW_IMU: 371 fw_info->ver = adev->gfx.imu_fw_version; 372 fw_info->feature = 0; 373 break; 374 case AMDGPU_INFO_FW_VPE: 375 fw_info->ver = adev->vpe.fw_version; 376 fw_info->feature = adev->vpe.feature_version; 377 break; 378 default: 379 return -EINVAL; 380 } 381 return 0; 382 } 383 384 static int amdgpu_userq_metadata_info_gfx(struct amdgpu_device *adev, 385 struct drm_amdgpu_info *info, 386 struct drm_amdgpu_info_uq_metadata_gfx *meta) 387 { 388 int ret = -EOPNOTSUPP; 389 390 if (adev->gfx.funcs->get_gfx_shadow_info) { 391 struct amdgpu_gfx_shadow_info shadow = {}; 392 393 adev->gfx.funcs->get_gfx_shadow_info(adev, &shadow, true); 394 meta->shadow_size = shadow.shadow_size; 395 meta->shadow_alignment = shadow.shadow_alignment; 396 meta->csa_size = shadow.csa_size; 397 meta->csa_alignment = shadow.csa_alignment; 398 ret = 0; 399 } 400 401 return ret; 402 } 403 404 static int amdgpu_userq_metadata_info_compute(struct amdgpu_device *adev, 405 struct drm_amdgpu_info *info, 406 struct drm_amdgpu_info_uq_metadata_compute *meta) 407 { 408 int ret = -EOPNOTSUPP; 409 410 if (adev->gfx.funcs->get_gfx_shadow_info) { 411 struct amdgpu_gfx_shadow_info shadow = {}; 412 413 adev->gfx.funcs->get_gfx_shadow_info(adev, &shadow, true); 414 meta->eop_size = shadow.eop_size; 415 meta->eop_alignment = shadow.eop_alignment; 416 ret = 0; 417 } 418 419 return ret; 420 } 421 422 static int amdgpu_userq_metadata_info_sdma(struct amdgpu_device *adev, 423 struct drm_amdgpu_info *info, 424 struct drm_amdgpu_info_uq_metadata_sdma *meta) 425 { 426 int ret = -EOPNOTSUPP; 427 428 if (adev->sdma.get_csa_info) { 429 struct amdgpu_sdma_csa_info csa = {}; 430 431 adev->sdma.get_csa_info(adev, &csa); 432 meta->csa_size = csa.size; 433 meta->csa_alignment = csa.alignment; 434 ret = 0; 435 } 436 437 return ret; 438 } 439 440 static int amdgpu_hw_ip_info(struct amdgpu_device *adev, 441 struct drm_amdgpu_info *info, 442 struct drm_amdgpu_info_hw_ip *result) 443 { 444 uint32_t ib_start_alignment = 0; 445 uint32_t ib_size_alignment = 0; 446 enum amd_ip_block_type type; 447 unsigned int num_rings = 0; 448 uint32_t num_slots = 0; 449 unsigned int i, j; 450 451 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 452 return -EINVAL; 453 454 switch (info->query_hw_ip.type) { 455 case AMDGPU_HW_IP_GFX: 456 type = AMD_IP_BLOCK_TYPE_GFX; 457 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 458 if (adev->gfx.gfx_ring[i].sched.ready && 459 !adev->gfx.gfx_ring[i].no_user_submission) 460 ++num_rings; 461 462 if (!adev->gfx.disable_uq) { 463 for (i = 0; i < AMDGPU_MES_MAX_GFX_PIPES; i++) 464 num_slots += hweight32(adev->mes.gfx_hqd_mask[i]); 465 } 466 467 ib_start_alignment = 32; 468 ib_size_alignment = 32; 469 break; 470 case AMDGPU_HW_IP_COMPUTE: 471 type = AMD_IP_BLOCK_TYPE_GFX; 472 for (i = 0; i < adev->gfx.num_compute_rings; i++) 473 if (adev->gfx.compute_ring[i].sched.ready && 474 !adev->gfx.compute_ring[i].no_user_submission) 475 ++num_rings; 476 477 if (!adev->sdma.disable_uq) { 478 for (i = 0; i < AMDGPU_MES_MAX_COMPUTE_PIPES; i++) 479 num_slots += hweight32(adev->mes.compute_hqd_mask[i]); 480 } 481 482 ib_start_alignment = 32; 483 ib_size_alignment = 32; 484 break; 485 case AMDGPU_HW_IP_DMA: 486 type = AMD_IP_BLOCK_TYPE_SDMA; 487 for (i = 0; i < adev->sdma.num_instances; i++) 488 if (adev->sdma.instance[i].ring.sched.ready && 489 !adev->sdma.instance[i].ring.no_user_submission) 490 ++num_rings; 491 492 if (!adev->gfx.disable_uq) { 493 for (i = 0; i < AMDGPU_MES_MAX_SDMA_PIPES; i++) 494 num_slots += hweight32(adev->mes.sdma_hqd_mask[i]); 495 } 496 497 ib_start_alignment = 256; 498 ib_size_alignment = 4; 499 break; 500 case AMDGPU_HW_IP_UVD: 501 type = AMD_IP_BLOCK_TYPE_UVD; 502 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 503 if (adev->uvd.harvest_config & (1 << i)) 504 continue; 505 506 if (adev->uvd.inst[i].ring.sched.ready && 507 !adev->uvd.inst[i].ring.no_user_submission) 508 ++num_rings; 509 } 510 ib_start_alignment = 256; 511 ib_size_alignment = 64; 512 break; 513 case AMDGPU_HW_IP_VCE: 514 type = AMD_IP_BLOCK_TYPE_VCE; 515 for (i = 0; i < adev->vce.num_rings; i++) 516 if (adev->vce.ring[i].sched.ready && 517 !adev->vce.ring[i].no_user_submission) 518 ++num_rings; 519 ib_start_alignment = 256; 520 ib_size_alignment = 4; 521 break; 522 case AMDGPU_HW_IP_UVD_ENC: 523 type = AMD_IP_BLOCK_TYPE_UVD; 524 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 525 if (adev->uvd.harvest_config & (1 << i)) 526 continue; 527 528 for (j = 0; j < adev->uvd.num_enc_rings; j++) 529 if (adev->uvd.inst[i].ring_enc[j].sched.ready && 530 !adev->uvd.inst[i].ring_enc[j].no_user_submission) 531 ++num_rings; 532 } 533 ib_start_alignment = 256; 534 ib_size_alignment = 4; 535 break; 536 case AMDGPU_HW_IP_VCN_DEC: 537 type = AMD_IP_BLOCK_TYPE_VCN; 538 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 539 if (adev->vcn.harvest_config & (1 << i)) 540 continue; 541 542 if (adev->vcn.inst[i].ring_dec.sched.ready && 543 !adev->vcn.inst[i].ring_dec.no_user_submission) 544 ++num_rings; 545 } 546 ib_start_alignment = 256; 547 ib_size_alignment = 64; 548 break; 549 case AMDGPU_HW_IP_VCN_ENC: 550 type = AMD_IP_BLOCK_TYPE_VCN; 551 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 552 if (adev->vcn.harvest_config & (1 << i)) 553 continue; 554 555 for (j = 0; j < adev->vcn.inst[i].num_enc_rings; j++) 556 if (adev->vcn.inst[i].ring_enc[j].sched.ready && 557 !adev->vcn.inst[i].ring_enc[j].no_user_submission) 558 ++num_rings; 559 } 560 ib_start_alignment = 256; 561 ib_size_alignment = 4; 562 break; 563 case AMDGPU_HW_IP_VCN_JPEG: 564 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 565 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 566 567 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { 568 if (adev->jpeg.harvest_config & (1 << i)) 569 continue; 570 571 for (j = 0; j < adev->jpeg.num_jpeg_rings; j++) 572 if (adev->jpeg.inst[i].ring_dec[j].sched.ready && 573 !adev->jpeg.inst[i].ring_dec[j].no_user_submission) 574 ++num_rings; 575 } 576 ib_start_alignment = 256; 577 ib_size_alignment = 64; 578 break; 579 case AMDGPU_HW_IP_VPE: 580 type = AMD_IP_BLOCK_TYPE_VPE; 581 if (adev->vpe.ring.sched.ready && 582 !adev->vpe.ring.no_user_submission) 583 ++num_rings; 584 ib_start_alignment = 256; 585 ib_size_alignment = 4; 586 break; 587 default: 588 return -EINVAL; 589 } 590 591 for (i = 0; i < adev->num_ip_blocks; i++) 592 if (adev->ip_blocks[i].version->type == type && 593 adev->ip_blocks[i].status.valid) 594 break; 595 596 if (i == adev->num_ip_blocks) 597 return 0; 598 599 num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type], 600 num_rings); 601 602 result->hw_ip_version_major = adev->ip_blocks[i].version->major; 603 result->hw_ip_version_minor = adev->ip_blocks[i].version->minor; 604 605 if (adev->asic_type >= CHIP_VEGA10) { 606 switch (type) { 607 case AMD_IP_BLOCK_TYPE_GFX: 608 result->ip_discovery_version = 609 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, GC_HWIP, 0)); 610 break; 611 case AMD_IP_BLOCK_TYPE_SDMA: 612 result->ip_discovery_version = 613 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, SDMA0_HWIP, 0)); 614 break; 615 case AMD_IP_BLOCK_TYPE_UVD: 616 case AMD_IP_BLOCK_TYPE_VCN: 617 case AMD_IP_BLOCK_TYPE_JPEG: 618 result->ip_discovery_version = 619 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, UVD_HWIP, 0)); 620 break; 621 case AMD_IP_BLOCK_TYPE_VCE: 622 result->ip_discovery_version = 623 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, VCE_HWIP, 0)); 624 break; 625 case AMD_IP_BLOCK_TYPE_VPE: 626 result->ip_discovery_version = 627 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, VPE_HWIP, 0)); 628 break; 629 default: 630 result->ip_discovery_version = 0; 631 break; 632 } 633 } else { 634 result->ip_discovery_version = 0; 635 } 636 result->capabilities_flags = 0; 637 result->available_rings = (1 << num_rings) - 1; 638 result->userq_num_slots = num_slots; 639 result->ib_start_alignment = ib_start_alignment; 640 result->ib_size_alignment = ib_size_alignment; 641 return 0; 642 } 643 644 /* 645 * Userspace get information ioctl 646 */ 647 /** 648 * amdgpu_info_ioctl - answer a device specific request. 649 * 650 * @dev: drm device pointer 651 * @data: request object 652 * @filp: drm filp 653 * 654 * This function is used to pass device specific parameters to the userspace 655 * drivers. Examples include: pci device id, pipeline parms, tiling params, 656 * etc. (all asics). 657 * Returns 0 on success, -EINVAL on failure. 658 */ 659 int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 660 { 661 struct amdgpu_device *adev = drm_to_adev(dev); 662 struct drm_amdgpu_info *info = data; 663 struct amdgpu_mode_info *minfo = &adev->mode_info; 664 void __user *out = (void __user *)(uintptr_t)info->return_pointer; 665 struct amdgpu_fpriv *fpriv; 666 struct amdgpu_ip_block *ip_block; 667 enum amd_ip_block_type type; 668 struct amdgpu_xcp *xcp; 669 u32 count, inst_mask; 670 uint32_t size = info->return_size; 671 struct drm_crtc *crtc; 672 uint32_t ui32 = 0; 673 uint64_t ui64 = 0; 674 int i, found, ret; 675 int ui32_size = sizeof(ui32); 676 677 if (!info->return_size || !info->return_pointer) 678 return -EINVAL; 679 680 switch (info->query) { 681 case AMDGPU_INFO_ACCEL_WORKING: 682 ui32 = adev->accel_working; 683 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 684 case AMDGPU_INFO_CRTC_FROM_ID: 685 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { 686 crtc = (struct drm_crtc *)minfo->crtcs[i]; 687 if (crtc && crtc->base.id == info->mode_crtc.id) { 688 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 689 690 ui32 = amdgpu_crtc->crtc_id; 691 found = 1; 692 break; 693 } 694 } 695 if (!found) { 696 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); 697 return -EINVAL; 698 } 699 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 700 case AMDGPU_INFO_HW_IP_INFO: { 701 struct drm_amdgpu_info_hw_ip ip = {}; 702 703 ret = amdgpu_hw_ip_info(adev, info, &ip); 704 if (ret) 705 return ret; 706 707 ret = copy_to_user(out, &ip, min_t(size_t, size, sizeof(ip))); 708 return ret ? -EFAULT : 0; 709 } 710 case AMDGPU_INFO_HW_IP_COUNT: { 711 fpriv = (struct amdgpu_fpriv *)filp->driver_priv; 712 type = amdgpu_ip_get_block_type(adev, info->query_hw_ip.type); 713 ip_block = amdgpu_device_ip_get_ip_block(adev, type); 714 715 if (!ip_block || !ip_block->status.valid) 716 return -EINVAL; 717 718 if (adev->xcp_mgr && adev->xcp_mgr->num_xcps > 0 && 719 fpriv->xcp_id < adev->xcp_mgr->num_xcps) { 720 xcp = &adev->xcp_mgr->xcp[fpriv->xcp_id]; 721 switch (type) { 722 case AMD_IP_BLOCK_TYPE_GFX: 723 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &inst_mask); 724 if (ret) 725 return ret; 726 count = hweight32(inst_mask); 727 break; 728 case AMD_IP_BLOCK_TYPE_SDMA: 729 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_SDMA, &inst_mask); 730 if (ret) 731 return ret; 732 count = hweight32(inst_mask); 733 break; 734 case AMD_IP_BLOCK_TYPE_JPEG: 735 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask); 736 if (ret) 737 return ret; 738 count = hweight32(inst_mask) * adev->jpeg.num_jpeg_rings; 739 break; 740 case AMD_IP_BLOCK_TYPE_VCN: 741 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask); 742 if (ret) 743 return ret; 744 count = hweight32(inst_mask); 745 break; 746 default: 747 return -EINVAL; 748 } 749 750 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; 751 } 752 753 switch (type) { 754 case AMD_IP_BLOCK_TYPE_GFX: 755 case AMD_IP_BLOCK_TYPE_VCE: 756 count = 1; 757 break; 758 case AMD_IP_BLOCK_TYPE_SDMA: 759 count = adev->sdma.num_instances; 760 break; 761 case AMD_IP_BLOCK_TYPE_JPEG: 762 count = adev->jpeg.num_jpeg_inst * adev->jpeg.num_jpeg_rings; 763 break; 764 case AMD_IP_BLOCK_TYPE_VCN: 765 count = adev->vcn.num_vcn_inst; 766 break; 767 case AMD_IP_BLOCK_TYPE_UVD: 768 count = adev->uvd.num_uvd_inst; 769 break; 770 case AMD_IP_BLOCK_TYPE_VPE: 771 count = adev->vpe.num_instances; 772 break; 773 /* For all other IP block types not listed in the switch statement 774 * the ip status is valid here and the instance count is one. 775 */ 776 default: 777 count = 1; 778 break; 779 } 780 781 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; 782 } 783 case AMDGPU_INFO_TIMESTAMP: 784 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev); 785 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 786 case AMDGPU_INFO_FW_VERSION: { 787 struct drm_amdgpu_info_firmware fw_info; 788 789 /* We only support one instance of each IP block right now. */ 790 if (info->query_fw.ip_instance != 0) 791 return -EINVAL; 792 793 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev); 794 if (ret) 795 return ret; 796 797 return copy_to_user(out, &fw_info, 798 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0; 799 } 800 case AMDGPU_INFO_NUM_BYTES_MOVED: 801 ui64 = atomic64_read(&adev->num_bytes_moved); 802 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 803 case AMDGPU_INFO_NUM_EVICTIONS: 804 ui64 = atomic64_read(&adev->num_evictions); 805 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 806 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS: 807 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults); 808 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 809 case AMDGPU_INFO_VRAM_USAGE: 810 ui64 = ttm_resource_manager_used(&adev->mman.vram_mgr.manager) ? 811 ttm_resource_manager_usage(&adev->mman.vram_mgr.manager) : 0; 812 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 813 case AMDGPU_INFO_VIS_VRAM_USAGE: 814 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr); 815 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 816 case AMDGPU_INFO_GTT_USAGE: 817 ui64 = ttm_resource_manager_usage(&adev->mman.gtt_mgr.manager); 818 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 819 case AMDGPU_INFO_GDS_CONFIG: { 820 struct drm_amdgpu_info_gds gds_info; 821 822 memset(&gds_info, 0, sizeof(gds_info)); 823 gds_info.compute_partition_size = adev->gds.gds_size; 824 gds_info.gds_total_size = adev->gds.gds_size; 825 gds_info.gws_per_compute_partition = adev->gds.gws_size; 826 gds_info.oa_per_compute_partition = adev->gds.oa_size; 827 return copy_to_user(out, &gds_info, 828 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0; 829 } 830 case AMDGPU_INFO_VRAM_GTT: { 831 struct drm_amdgpu_info_vram_gtt vram_gtt; 832 833 vram_gtt.vram_size = adev->gmc.real_vram_size - 834 atomic64_read(&adev->vram_pin_size) - 835 AMDGPU_VM_RESERVED_VRAM; 836 vram_gtt.vram_cpu_accessible_size = 837 min(adev->gmc.visible_vram_size - 838 atomic64_read(&adev->visible_pin_size), 839 vram_gtt.vram_size); 840 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size; 841 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size); 842 return copy_to_user(out, &vram_gtt, 843 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; 844 } 845 case AMDGPU_INFO_MEMORY: { 846 struct drm_amdgpu_memory_info mem; 847 struct ttm_resource_manager *gtt_man = 848 &adev->mman.gtt_mgr.manager; 849 struct ttm_resource_manager *vram_man = 850 &adev->mman.vram_mgr.manager; 851 852 memset(&mem, 0, sizeof(mem)); 853 mem.vram.total_heap_size = adev->gmc.real_vram_size; 854 mem.vram.usable_heap_size = adev->gmc.real_vram_size - 855 atomic64_read(&adev->vram_pin_size) - 856 AMDGPU_VM_RESERVED_VRAM; 857 mem.vram.heap_usage = ttm_resource_manager_used(&adev->mman.vram_mgr.manager) ? 858 ttm_resource_manager_usage(vram_man) : 0; 859 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4; 860 861 mem.cpu_accessible_vram.total_heap_size = 862 adev->gmc.visible_vram_size; 863 mem.cpu_accessible_vram.usable_heap_size = 864 min(adev->gmc.visible_vram_size - 865 atomic64_read(&adev->visible_pin_size), 866 mem.vram.usable_heap_size); 867 mem.cpu_accessible_vram.heap_usage = 868 amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr); 869 mem.cpu_accessible_vram.max_allocation = 870 mem.cpu_accessible_vram.usable_heap_size * 3 / 4; 871 872 mem.gtt.total_heap_size = gtt_man->size; 873 mem.gtt.usable_heap_size = mem.gtt.total_heap_size - 874 atomic64_read(&adev->gart_pin_size); 875 mem.gtt.heap_usage = ttm_resource_manager_usage(gtt_man); 876 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4; 877 878 return copy_to_user(out, &mem, 879 min((size_t)size, sizeof(mem))) 880 ? -EFAULT : 0; 881 } 882 case AMDGPU_INFO_READ_MMR_REG: { 883 unsigned int se_num = (info->read_mmr_reg.instance >> 884 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & 885 AMDGPU_INFO_MMR_SE_INDEX_MASK; 886 unsigned int sh_num = (info->read_mmr_reg.instance >> 887 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & 888 AMDGPU_INFO_MMR_SH_INDEX_MASK; 889 unsigned int alloc_size; 890 uint32_t *regs; 891 int ret; 892 893 /* set full masks if the userspace set all bits 894 * in the bitfields 895 */ 896 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) 897 se_num = 0xffffffff; 898 else if (se_num >= AMDGPU_GFX_MAX_SE) 899 return -EINVAL; 900 901 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) 902 sh_num = 0xffffffff; 903 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE) 904 return -EINVAL; 905 906 if (info->read_mmr_reg.count > 128) 907 return -EINVAL; 908 909 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), 910 GFP_KERNEL); 911 if (!regs) 912 return -ENOMEM; 913 914 down_read(&adev->reset_domain->sem); 915 alloc_size = info->read_mmr_reg.count * sizeof(*regs); 916 amdgpu_gfx_off_ctrl(adev, false); 917 ret = 0; 918 for (i = 0; i < info->read_mmr_reg.count; i++) { 919 if (amdgpu_asic_read_register(adev, se_num, sh_num, 920 info->read_mmr_reg.dword_offset + i, 921 ®s[i])) { 922 DRM_DEBUG_KMS("unallowed offset %#x\n", 923 info->read_mmr_reg.dword_offset + i); 924 ret = -EFAULT; 925 break; 926 } 927 } 928 amdgpu_gfx_off_ctrl(adev, true); 929 up_read(&adev->reset_domain->sem); 930 931 if (!ret) { 932 ret = copy_to_user(out, regs, min(size, alloc_size)) 933 ? -EFAULT : 0; 934 } 935 kfree(regs); 936 return ret; 937 } 938 case AMDGPU_INFO_DEV_INFO: { 939 struct drm_amdgpu_info_device *dev_info; 940 uint64_t vm_size; 941 uint32_t pcie_gen_mask, pcie_width_mask; 942 943 dev_info = kzalloc_obj(*dev_info); 944 if (!dev_info) 945 return -ENOMEM; 946 947 dev_info->device_id = adev->pdev->device; 948 dev_info->chip_rev = adev->rev_id; 949 dev_info->external_rev = adev->external_rev_id; 950 dev_info->pci_rev = adev->pdev->revision; 951 dev_info->family = adev->family; 952 dev_info->num_shader_engines = adev->gfx.config.max_shader_engines; 953 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 954 /* return all clocks in KHz */ 955 dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; 956 if (adev->pm.dpm_enabled) { 957 dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10; 958 dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10; 959 dev_info->min_engine_clock = amdgpu_dpm_get_sclk(adev, true) * 10; 960 dev_info->min_memory_clock = amdgpu_dpm_get_mclk(adev, true) * 10; 961 } else { 962 dev_info->max_engine_clock = 963 dev_info->min_engine_clock = 964 adev->clock.default_sclk * 10; 965 dev_info->max_memory_clock = 966 dev_info->min_memory_clock = 967 adev->clock.default_mclk * 10; 968 } 969 dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; 970 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se * 971 adev->gfx.config.max_shader_engines; 972 dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; 973 dev_info->ids_flags = 0; 974 if (adev->flags & AMD_IS_APU) 975 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION; 976 if (adev->gfx.mcbp) 977 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION; 978 if (amdgpu_is_tmz(adev)) 979 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ; 980 if (adev->gfx.config.ta_cntl2_truncate_coord_mode) 981 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD; 982 983 /* Gang submit is not supported under SRIOV currently */ 984 if (!amdgpu_sriov_vf(adev)) 985 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_GANG_SUBMIT; 986 987 if (amdgpu_passthrough(adev)) 988 dev_info->ids_flags |= (AMDGPU_IDS_FLAGS_MODE_PT << 989 AMDGPU_IDS_FLAGS_MODE_SHIFT) & 990 AMDGPU_IDS_FLAGS_MODE_MASK; 991 else if (amdgpu_sriov_vf(adev)) 992 dev_info->ids_flags |= (AMDGPU_IDS_FLAGS_MODE_VF << 993 AMDGPU_IDS_FLAGS_MODE_SHIFT) & 994 AMDGPU_IDS_FLAGS_MODE_MASK; 995 996 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 997 vm_size -= AMDGPU_VA_RESERVED_TOP; 998 999 /* Older VCE FW versions are buggy and can handle only 40bits */ 1000 if (adev->vce.fw_version && 1001 adev->vce.fw_version < AMDGPU_VCE_FW_53_45) 1002 vm_size = min(vm_size, 1ULL << 40); 1003 1004 dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_BOTTOM; 1005 dev_info->virtual_address_max = 1006 min(vm_size, AMDGPU_GMC_HOLE_START); 1007 1008 if (vm_size > AMDGPU_GMC_HOLE_START) { 1009 dev_info->high_va_offset = AMDGPU_GMC_HOLE_END; 1010 dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size; 1011 } 1012 dev_info->virtual_address_alignment = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 1013 dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE; 1014 dev_info->gart_page_size = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 1015 dev_info->cu_active_number = adev->gfx.cu_info.number; 1016 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; 1017 dev_info->ce_ram_size = adev->gfx.ce_ram_size; 1018 memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0], 1019 sizeof(adev->gfx.cu_info.ao_cu_bitmap)); 1020 memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], 1021 sizeof(dev_info->cu_bitmap)); 1022 dev_info->vram_type = adev->gmc.vram_type; 1023 dev_info->vram_bit_width = adev->gmc.vram_width; 1024 dev_info->vce_harvest_config = adev->vce.harvest_config; 1025 dev_info->gc_double_offchip_lds_buf = 1026 adev->gfx.config.double_offchip_lds_buf; 1027 dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size; 1028 dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs; 1029 dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh; 1030 dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches; 1031 dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth; 1032 dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth; 1033 dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads; 1034 1035 if (adev->family >= AMDGPU_FAMILY_NV) 1036 dev_info->pa_sc_tile_steering_override = 1037 adev->gfx.config.pa_sc_tile_steering_override; 1038 1039 dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask; 1040 1041 /* Combine the chip gen mask with the platform (CPU/mobo) mask. */ 1042 pcie_gen_mask = adev->pm.pcie_gen_mask & 1043 (adev->pm.pcie_gen_mask >> CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT); 1044 pcie_width_mask = adev->pm.pcie_mlw_mask & 1045 (adev->pm.pcie_mlw_mask >> CAIL_PCIE_LINK_WIDTH_SUPPORT_SHIFT); 1046 dev_info->pcie_gen = fls(pcie_gen_mask); 1047 dev_info->pcie_num_lanes = 1048 pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X32 ? 32 : 1049 pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X16 ? 16 : 1050 pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X12 ? 12 : 1051 pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X8 ? 8 : 1052 pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X4 ? 4 : 1053 pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X2 ? 2 : 1; 1054 1055 dev_info->tcp_cache_size = adev->gfx.config.gc_tcp_l1_size; 1056 dev_info->num_sqc_per_wgp = adev->gfx.config.gc_num_sqc_per_wgp; 1057 dev_info->sqc_data_cache_size = adev->gfx.config.gc_l1_data_cache_size_per_sqc; 1058 dev_info->sqc_inst_cache_size = adev->gfx.config.gc_l1_instruction_cache_size_per_sqc; 1059 dev_info->gl1c_cache_size = adev->gfx.config.gc_gl1c_size_per_instance * 1060 adev->gfx.config.gc_gl1c_per_sa; 1061 dev_info->gl2c_cache_size = adev->gfx.config.gc_gl2c_per_gpu; 1062 dev_info->mall_size = adev->gmc.mall_size; 1063 1064 1065 if (adev->gfx.funcs->get_gfx_shadow_info) { 1066 struct amdgpu_gfx_shadow_info shadow_info; 1067 1068 ret = amdgpu_gfx_get_gfx_shadow_info(adev, &shadow_info); 1069 if (!ret) { 1070 dev_info->shadow_size = shadow_info.shadow_size; 1071 dev_info->shadow_alignment = shadow_info.shadow_alignment; 1072 dev_info->csa_size = shadow_info.csa_size; 1073 dev_info->csa_alignment = shadow_info.csa_alignment; 1074 } 1075 } 1076 1077 dev_info->userq_ip_mask = amdgpu_userq_get_supported_ip_mask(adev); 1078 1079 ret = copy_to_user(out, dev_info, 1080 min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0; 1081 kfree(dev_info); 1082 return ret; 1083 } 1084 case AMDGPU_INFO_VCE_CLOCK_TABLE: { 1085 unsigned int i; 1086 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {}; 1087 struct amd_vce_state *vce_state; 1088 1089 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) { 1090 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i); 1091 if (vce_state) { 1092 vce_clk_table.entries[i].sclk = vce_state->sclk; 1093 vce_clk_table.entries[i].mclk = vce_state->mclk; 1094 vce_clk_table.entries[i].eclk = vce_state->evclk; 1095 vce_clk_table.num_valid_entries++; 1096 } 1097 } 1098 1099 return copy_to_user(out, &vce_clk_table, 1100 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0; 1101 } 1102 case AMDGPU_INFO_VBIOS: { 1103 uint32_t bios_size = adev->bios_size; 1104 1105 switch (info->vbios_info.type) { 1106 case AMDGPU_INFO_VBIOS_SIZE: 1107 return copy_to_user(out, &bios_size, 1108 min((size_t)size, sizeof(bios_size))) 1109 ? -EFAULT : 0; 1110 case AMDGPU_INFO_VBIOS_IMAGE: { 1111 uint8_t *bios; 1112 uint32_t bios_offset = info->vbios_info.offset; 1113 1114 if (bios_offset >= bios_size) 1115 return -EINVAL; 1116 1117 bios = adev->bios + bios_offset; 1118 return copy_to_user(out, bios, 1119 min((size_t)size, (size_t)(bios_size - bios_offset))) 1120 ? -EFAULT : 0; 1121 } 1122 case AMDGPU_INFO_VBIOS_INFO: { 1123 struct drm_amdgpu_info_vbios vbios_info = {}; 1124 struct atom_context *atom_context; 1125 1126 atom_context = adev->mode_info.atom_context; 1127 if (atom_context) { 1128 memcpy(vbios_info.name, atom_context->name, 1129 sizeof(atom_context->name)); 1130 memcpy(vbios_info.vbios_pn, atom_context->vbios_pn, 1131 sizeof(atom_context->vbios_pn)); 1132 vbios_info.version = atom_context->version; 1133 memcpy(vbios_info.vbios_ver_str, atom_context->vbios_ver_str, 1134 sizeof(atom_context->vbios_ver_str)); 1135 memcpy(vbios_info.date, atom_context->date, 1136 sizeof(atom_context->date)); 1137 } 1138 1139 return copy_to_user(out, &vbios_info, 1140 min((size_t)size, sizeof(vbios_info))) ? -EFAULT : 0; 1141 } 1142 default: 1143 DRM_DEBUG_KMS("Invalid request %d\n", 1144 info->vbios_info.type); 1145 return -EINVAL; 1146 } 1147 } 1148 case AMDGPU_INFO_NUM_HANDLES: { 1149 struct drm_amdgpu_info_num_handles handle; 1150 1151 switch (info->query_hw_ip.type) { 1152 case AMDGPU_HW_IP_UVD: 1153 /* Starting Polaris, we support unlimited UVD handles */ 1154 if (adev->asic_type < CHIP_POLARIS10) { 1155 handle.uvd_max_handles = adev->uvd.max_handles; 1156 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev); 1157 1158 return copy_to_user(out, &handle, 1159 min((size_t)size, sizeof(handle))) ? -EFAULT : 0; 1160 } else { 1161 return -ENODATA; 1162 } 1163 1164 break; 1165 default: 1166 return -EINVAL; 1167 } 1168 } 1169 case AMDGPU_INFO_SENSOR: { 1170 if (!adev->pm.dpm_enabled) 1171 return -ENOENT; 1172 1173 switch (info->sensor_info.type) { 1174 case AMDGPU_INFO_SENSOR_GFX_SCLK: 1175 /* get sclk in Mhz */ 1176 if (amdgpu_dpm_read_sensor(adev, 1177 AMDGPU_PP_SENSOR_GFX_SCLK, 1178 (void *)&ui32, &ui32_size)) { 1179 return -EINVAL; 1180 } 1181 ui32 /= 100; 1182 break; 1183 case AMDGPU_INFO_SENSOR_GFX_MCLK: 1184 /* get mclk in Mhz */ 1185 if (amdgpu_dpm_read_sensor(adev, 1186 AMDGPU_PP_SENSOR_GFX_MCLK, 1187 (void *)&ui32, &ui32_size)) { 1188 return -EINVAL; 1189 } 1190 ui32 /= 100; 1191 break; 1192 case AMDGPU_INFO_SENSOR_GPU_TEMP: 1193 /* get temperature in millidegrees C */ 1194 if (amdgpu_dpm_read_sensor(adev, 1195 AMDGPU_PP_SENSOR_GPU_TEMP, 1196 (void *)&ui32, &ui32_size)) { 1197 return -EINVAL; 1198 } 1199 break; 1200 case AMDGPU_INFO_SENSOR_GPU_LOAD: 1201 /* get GPU load */ 1202 if (amdgpu_dpm_read_sensor(adev, 1203 AMDGPU_PP_SENSOR_GPU_LOAD, 1204 (void *)&ui32, &ui32_size)) { 1205 return -EINVAL; 1206 } 1207 break; 1208 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER: 1209 /* get average GPU power */ 1210 if (amdgpu_dpm_read_sensor(adev, 1211 AMDGPU_PP_SENSOR_GPU_AVG_POWER, 1212 (void *)&ui32, &ui32_size)) { 1213 /* fall back to input power for backwards compat */ 1214 if (amdgpu_dpm_read_sensor(adev, 1215 AMDGPU_PP_SENSOR_GPU_INPUT_POWER, 1216 (void *)&ui32, &ui32_size)) { 1217 return -EINVAL; 1218 } 1219 } 1220 ui32 /= MILLIWATT_PER_WATT; 1221 break; 1222 case AMDGPU_INFO_SENSOR_GPU_INPUT_POWER: 1223 /* get input GPU power */ 1224 if (amdgpu_dpm_read_sensor(adev, 1225 AMDGPU_PP_SENSOR_GPU_INPUT_POWER, 1226 (void *)&ui32, &ui32_size)) { 1227 return -EINVAL; 1228 } 1229 ui32 /= MILLIWATT_PER_WATT; 1230 break; 1231 case AMDGPU_INFO_SENSOR_VDDNB: 1232 /* get VDDNB in millivolts */ 1233 if (amdgpu_dpm_read_sensor(adev, 1234 AMDGPU_PP_SENSOR_VDDNB, 1235 (void *)&ui32, &ui32_size)) { 1236 return -EINVAL; 1237 } 1238 break; 1239 case AMDGPU_INFO_SENSOR_VDDGFX: 1240 /* get VDDGFX in millivolts */ 1241 if (amdgpu_dpm_read_sensor(adev, 1242 AMDGPU_PP_SENSOR_VDDGFX, 1243 (void *)&ui32, &ui32_size)) { 1244 return -EINVAL; 1245 } 1246 break; 1247 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK: 1248 /* get stable pstate sclk in Mhz */ 1249 if (amdgpu_dpm_read_sensor(adev, 1250 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 1251 (void *)&ui32, &ui32_size)) { 1252 return -EINVAL; 1253 } 1254 ui32 /= 100; 1255 break; 1256 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK: 1257 /* get stable pstate mclk in Mhz */ 1258 if (amdgpu_dpm_read_sensor(adev, 1259 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 1260 (void *)&ui32, &ui32_size)) { 1261 return -EINVAL; 1262 } 1263 ui32 /= 100; 1264 break; 1265 case AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK: 1266 /* get peak pstate sclk in Mhz */ 1267 if (amdgpu_dpm_read_sensor(adev, 1268 AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK, 1269 (void *)&ui32, &ui32_size)) { 1270 return -EINVAL; 1271 } 1272 ui32 /= 100; 1273 break; 1274 case AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK: 1275 /* get peak pstate mclk in Mhz */ 1276 if (amdgpu_dpm_read_sensor(adev, 1277 AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK, 1278 (void *)&ui32, &ui32_size)) { 1279 return -EINVAL; 1280 } 1281 ui32 /= 100; 1282 break; 1283 default: 1284 DRM_DEBUG_KMS("Invalid request %d\n", 1285 info->sensor_info.type); 1286 return -EINVAL; 1287 } 1288 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 1289 } 1290 case AMDGPU_INFO_VRAM_LOST_COUNTER: 1291 ui32 = atomic_read(&adev->vram_lost_counter); 1292 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 1293 case AMDGPU_INFO_RAS_ENABLED_FEATURES: { 1294 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1295 uint64_t ras_mask; 1296 1297 if (!ras) 1298 return -EINVAL; 1299 1300 if (amdgpu_uniras_enabled(adev)) 1301 ras_mask = amdgpu_uniras_get_ras_caps(adev); 1302 else 1303 ras_mask = (uint64_t)adev->ras_enabled << 32 | ras->features; 1304 1305 return copy_to_user(out, &ras_mask, 1306 min_t(u64, size, sizeof(ras_mask))) ? 1307 -EFAULT : 0; 1308 } 1309 case AMDGPU_INFO_VIDEO_CAPS: { 1310 const struct amdgpu_video_codecs *codecs; 1311 struct drm_amdgpu_info_video_caps *caps; 1312 int r; 1313 1314 if (!adev->asic_funcs->query_video_codecs) 1315 return -EINVAL; 1316 1317 switch (info->video_cap.type) { 1318 case AMDGPU_INFO_VIDEO_CAPS_DECODE: 1319 r = amdgpu_asic_query_video_codecs(adev, false, &codecs); 1320 if (r) 1321 return -EINVAL; 1322 break; 1323 case AMDGPU_INFO_VIDEO_CAPS_ENCODE: 1324 r = amdgpu_asic_query_video_codecs(adev, true, &codecs); 1325 if (r) 1326 return -EINVAL; 1327 break; 1328 default: 1329 DRM_DEBUG_KMS("Invalid request %d\n", 1330 info->video_cap.type); 1331 return -EINVAL; 1332 } 1333 1334 caps = kzalloc_obj(*caps); 1335 if (!caps) 1336 return -ENOMEM; 1337 1338 for (i = 0; i < codecs->codec_count; i++) { 1339 int idx = codecs->codec_array[i].codec_type; 1340 1341 switch (idx) { 1342 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2: 1343 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4: 1344 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1: 1345 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC: 1346 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC: 1347 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG: 1348 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9: 1349 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1: 1350 caps->codec_info[idx].valid = 1; 1351 caps->codec_info[idx].max_width = 1352 codecs->codec_array[i].max_width; 1353 caps->codec_info[idx].max_height = 1354 codecs->codec_array[i].max_height; 1355 caps->codec_info[idx].max_pixels_per_frame = 1356 codecs->codec_array[i].max_pixels_per_frame; 1357 caps->codec_info[idx].max_level = 1358 codecs->codec_array[i].max_level; 1359 break; 1360 default: 1361 break; 1362 } 1363 } 1364 r = copy_to_user(out, caps, 1365 min((size_t)size, sizeof(*caps))) ? -EFAULT : 0; 1366 kfree(caps); 1367 return r; 1368 } 1369 case AMDGPU_INFO_MAX_IBS: { 1370 uint32_t max_ibs[AMDGPU_HW_IP_NUM]; 1371 1372 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) 1373 max_ibs[i] = amdgpu_ring_max_ibs(i); 1374 1375 return copy_to_user(out, max_ibs, 1376 min((size_t)size, sizeof(max_ibs))) ? -EFAULT : 0; 1377 } 1378 case AMDGPU_INFO_GPUVM_FAULT: { 1379 struct amdgpu_fpriv *fpriv = filp->driver_priv; 1380 struct amdgpu_vm *vm = &fpriv->vm; 1381 struct drm_amdgpu_info_gpuvm_fault gpuvm_fault; 1382 unsigned long flags; 1383 1384 if (!vm) 1385 return -EINVAL; 1386 1387 memset(&gpuvm_fault, 0, sizeof(gpuvm_fault)); 1388 1389 amdgpu_pasid_lock(&flags); 1390 gpuvm_fault.addr = vm->fault_info.addr; 1391 gpuvm_fault.status = vm->fault_info.status; 1392 gpuvm_fault.vmhub = vm->fault_info.vmhub; 1393 amdgpu_pasid_unlock(flags); 1394 1395 return copy_to_user(out, &gpuvm_fault, 1396 min((size_t)size, sizeof(gpuvm_fault))) ? -EFAULT : 0; 1397 } 1398 case AMDGPU_INFO_UQ_FW_AREAS: { 1399 struct drm_amdgpu_info_uq_metadata meta_info = {}; 1400 1401 switch (info->query_hw_ip.type) { 1402 case AMDGPU_HW_IP_GFX: 1403 ret = amdgpu_userq_metadata_info_gfx(adev, info, &meta_info.gfx); 1404 if (ret) 1405 return ret; 1406 1407 ret = copy_to_user(out, &meta_info, 1408 min((size_t)size, sizeof(meta_info))) ? -EFAULT : 0; 1409 return 0; 1410 case AMDGPU_HW_IP_COMPUTE: 1411 ret = amdgpu_userq_metadata_info_compute(adev, info, &meta_info.compute); 1412 if (ret) 1413 return ret; 1414 1415 ret = copy_to_user(out, &meta_info, 1416 min((size_t)size, sizeof(meta_info))) ? -EFAULT : 0; 1417 return 0; 1418 case AMDGPU_HW_IP_DMA: 1419 ret = amdgpu_userq_metadata_info_sdma(adev, info, &meta_info.sdma); 1420 if (ret) 1421 return ret; 1422 1423 ret = copy_to_user(out, &meta_info, 1424 min((size_t)size, sizeof(meta_info))) ? -EFAULT : 0; 1425 return 0; 1426 default: 1427 return -EINVAL; 1428 } 1429 } 1430 default: 1431 DRM_DEBUG_KMS("Invalid request %d\n", info->query); 1432 return -EINVAL; 1433 } 1434 return 0; 1435 } 1436 1437 /** 1438 * amdgpu_proc_options_ioctl - set per-fd user options 1439 * 1440 * @dev: drm dev pointer 1441 * @data: pointer to struct drm_amdgpu_proc_options 1442 * @filp: drm file 1443 * 1444 * Sets options stored on the per-file amdgpu_fpriv. Currently the only 1445 * supported option is %AMDGPU_PROC_OPTIONS_OP_KFD_SIGBUS_DELAY which 1446 * controls how KFD delivers SIGBUS for poison/RAS events to the calling 1447 * process (immediate, suppressed, or delayed by N milliseconds). 1448 */ 1449 int amdgpu_proc_options_ioctl(struct drm_device *dev, void *data, 1450 struct drm_file *filp) 1451 { 1452 struct drm_amdgpu_proc_options *args = data; 1453 1454 switch (args->op) { 1455 case AMDGPU_PROC_OPTIONS_OP_KFD_SIGBUS_DELAY: 1456 return amdgpu_amdkfd_set_sigbus_delay(current, 1457 args->kfd_sigbus_delay.value); 1458 default: 1459 DRM_DEBUG_KMS("Invalid user option op %u\n", args->op); 1460 return -EINVAL; 1461 } 1462 } 1463 1464 /** 1465 * amdgpu_driver_open_kms - drm callback for open 1466 * 1467 * @dev: drm dev pointer 1468 * @file_priv: drm file 1469 * 1470 * On device open, init vm on cayman+ (all asics). 1471 * Returns 0 on success, error on failure. 1472 */ 1473 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 1474 { 1475 struct amdgpu_device *adev = drm_to_adev(dev); 1476 struct amdgpu_fpriv *fpriv; 1477 struct drm_exec exec; 1478 int r, pasid = 0; 1479 1480 /* Ensure IB tests are run on ring */ 1481 flush_delayed_work(&adev->delayed_init_work); 1482 1483 1484 if (amdgpu_ras_intr_triggered()) { 1485 DRM_ERROR("RAS Intr triggered, device disabled!!"); 1486 return -EHWPOISON; 1487 } 1488 1489 file_priv->driver_priv = NULL; 1490 1491 r = pm_runtime_get_sync(dev->dev); 1492 if (r < 0) 1493 goto pm_put; 1494 1495 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 1496 if (unlikely(!fpriv)) { 1497 r = -ENOMEM; 1498 goto out_suspend; 1499 } 1500 1501 r = amdgpu_xcp_open_device(adev, fpriv, file_priv); 1502 if (r) 1503 goto error_pasid; 1504 1505 amdgpu_debugfs_vm_init(file_priv); 1506 1507 r = amdgpu_vm_init(adev, &fpriv->vm, fpriv->xcp_id); 1508 if (r) 1509 goto error_pasid; 1510 1511 pasid = amdgpu_pasid_alloc(16, fpriv); 1512 if (pasid < 0) { 1513 dev_warn(adev->dev, "No more PASIDs available!"); 1514 pasid = 0; 1515 } 1516 fpriv->vm.pasid = pasid; 1517 1518 drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES, 0); 1519 drm_exec_until_all_locked(&exec) { 1520 r = amdgpu_vm_lock_pd(&fpriv->vm, &exec, 0); 1521 drm_exec_retry_on_contention(&exec); 1522 if (unlikely(r)) 1523 goto error_vm; 1524 } 1525 1526 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL); 1527 drm_exec_fini(&exec); 1528 if (!fpriv->prt_va) { 1529 r = -ENOMEM; 1530 goto error_vm; 1531 } 1532 1533 if (adev->gfx.mcbp) { 1534 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK; 1535 1536 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj, 1537 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE); 1538 if (r) 1539 goto error_vm; 1540 } 1541 1542 r = amdgpu_seq64_map(adev, &fpriv->vm, &fpriv->seq64_va); 1543 if (r) 1544 goto error_vm; 1545 1546 xa_init_flags(&fpriv->bo_list_handles, XA_FLAGS_ALLOC1); 1547 1548 r = amdgpu_userq_mgr_init(&fpriv->userq_mgr, file_priv, adev); 1549 if (r) 1550 drm_warn(adev_to_drm(adev), 1551 "Failed to init usermode queue manager (%d), use legacy workload submission only\n", 1552 r); 1553 1554 amdgpu_evf_mgr_init(&fpriv->evf_mgr); 1555 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr, adev); 1556 1557 file_priv->driver_priv = fpriv; 1558 goto out_suspend; 1559 1560 error_vm: 1561 if (pasid) { 1562 amdgpu_pasid_free(pasid); 1563 pasid = 0; 1564 } 1565 1566 amdgpu_vm_fini(adev, &fpriv->vm); 1567 1568 error_pasid: 1569 kfree(fpriv); 1570 1571 out_suspend: 1572 pm_put: 1573 pm_runtime_put_autosuspend(dev->dev); 1574 1575 return r; 1576 } 1577 1578 /** 1579 * amdgpu_driver_postclose_kms - drm callback for post close 1580 * 1581 * @dev: drm dev pointer 1582 * @file_priv: drm file 1583 * 1584 * On device post close, tear down vm on cayman+ (all asics). 1585 */ 1586 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1587 struct drm_file *file_priv) 1588 { 1589 struct amdgpu_device *adev = drm_to_adev(dev); 1590 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1591 struct amdgpu_bo_list *list; 1592 struct amdgpu_bo *pd; 1593 unsigned long handle; 1594 u32 pasid; 1595 1596 if (!fpriv) 1597 return; 1598 1599 pm_runtime_get_sync(dev->dev); 1600 1601 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL) 1602 amdgpu_uvd_free_handles(adev, file_priv); 1603 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL) 1604 amdgpu_vce_free_handles(adev, file_priv); 1605 1606 if (fpriv->csa_va) { 1607 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK; 1608 1609 WARN_ON(amdgpu_unmap_static_csa(adev, &fpriv->vm, adev->virt.csa_obj, 1610 fpriv->csa_va, csa_addr)); 1611 fpriv->csa_va = NULL; 1612 } 1613 1614 amdgpu_seq64_unmap(adev, fpriv); 1615 1616 pasid = fpriv->vm.pasid; 1617 pd = amdgpu_bo_ref(fpriv->vm.root.bo); 1618 if (!WARN_ON(amdgpu_bo_reserve(pd, true))) { 1619 amdgpu_vm_bo_del(adev, fpriv->prt_va); 1620 amdgpu_bo_unreserve(pd); 1621 } 1622 1623 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); 1624 1625 if (pasid) 1626 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid); 1627 1628 amdgpu_vm_fini(adev, &fpriv->vm); 1629 amdgpu_bo_unref(&pd); 1630 1631 xa_for_each(&fpriv->bo_list_handles, handle, list) 1632 amdgpu_bo_list_put(list); 1633 xa_destroy(&fpriv->bo_list_handles); 1634 1635 kfree(fpriv); 1636 file_priv->driver_priv = NULL; 1637 1638 pm_runtime_put_autosuspend(dev->dev); 1639 } 1640 1641 1642 void amdgpu_driver_release_kms(struct drm_device *dev) 1643 { 1644 struct amdgpu_device *adev = drm_to_adev(dev); 1645 1646 amdgpu_device_fini_sw(adev); 1647 pci_set_drvdata(adev->pdev, NULL); 1648 } 1649 1650 /* 1651 * VBlank related functions. 1652 */ 1653 /** 1654 * amdgpu_get_vblank_counter_kms - get frame count 1655 * 1656 * @crtc: crtc to get the frame count from 1657 * 1658 * Gets the frame count on the requested crtc (all asics). 1659 * Returns frame count on success, -EINVAL on failure. 1660 */ 1661 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc) 1662 { 1663 struct drm_device *dev = crtc->dev; 1664 unsigned int pipe = crtc->index; 1665 struct amdgpu_device *adev = drm_to_adev(dev); 1666 int vpos, hpos, stat; 1667 u32 count; 1668 1669 if (pipe >= adev->mode_info.num_crtc) { 1670 DRM_ERROR("Invalid crtc %u\n", pipe); 1671 return -EINVAL; 1672 } 1673 if (!down_read_trylock(&adev->reset_domain->sem)) 1674 return drm_crtc_vblank_count(crtc); 1675 1676 1677 /* The hw increments its frame counter at start of vsync, not at start 1678 * of vblank, as is required by DRM core vblank counter handling. 1679 * Cook the hw count here to make it appear to the caller as if it 1680 * incremented at start of vblank. We measure distance to start of 1681 * vblank in vpos. vpos therefore will be >= 0 between start of vblank 1682 * and start of vsync, so vpos >= 0 means to bump the hw frame counter 1683 * result by 1 to give the proper appearance to caller. 1684 */ 1685 if (adev->mode_info.crtcs[pipe]) { 1686 /* Repeat readout if needed to provide stable result if 1687 * we cross start of vsync during the queries. 1688 */ 1689 do { 1690 count = amdgpu_display_vblank_get_counter(adev, pipe); 1691 /* Ask amdgpu_display_get_crtc_scanoutpos to return 1692 * vpos as distance to start of vblank, instead of 1693 * regular vertical scanout pos. 1694 */ 1695 stat = amdgpu_display_get_crtc_scanoutpos( 1696 dev, pipe, GET_DISTANCE_TO_VBLANKSTART, 1697 &vpos, &hpos, NULL, NULL, 1698 &adev->mode_info.crtcs[pipe]->base.hwmode); 1699 } while (count != amdgpu_display_vblank_get_counter(adev, pipe)); 1700 1701 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 1702 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 1703 DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 1704 } else { 1705 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", 1706 pipe, vpos); 1707 1708 /* Bump counter if we are at >= leading edge of vblank, 1709 * but before vsync where vpos would turn negative and 1710 * the hw counter really increments. 1711 */ 1712 if (vpos >= 0) 1713 count++; 1714 } 1715 } else { 1716 /* Fallback to use value as is. */ 1717 count = amdgpu_display_vblank_get_counter(adev, pipe); 1718 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 1719 } 1720 1721 up_read(&adev->reset_domain->sem); 1722 return count; 1723 } 1724 1725 /** 1726 * amdgpu_enable_vblank_kms - enable vblank interrupt 1727 * 1728 * @crtc: crtc to enable vblank interrupt for 1729 * 1730 * Enable the interrupt on the requested crtc (all asics). 1731 * Returns 0 on success, -EINVAL on failure. 1732 */ 1733 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc) 1734 { 1735 struct drm_device *dev = crtc->dev; 1736 unsigned int pipe = crtc->index; 1737 struct amdgpu_device *adev = drm_to_adev(dev); 1738 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1739 1740 return amdgpu_irq_get(adev, &adev->crtc_irq, idx); 1741 } 1742 1743 /** 1744 * amdgpu_disable_vblank_kms - disable vblank interrupt 1745 * 1746 * @crtc: crtc to disable vblank interrupt for 1747 * 1748 * Disable the interrupt on the requested crtc (all asics). 1749 */ 1750 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc) 1751 { 1752 struct drm_device *dev = crtc->dev; 1753 unsigned int pipe = crtc->index; 1754 struct amdgpu_device *adev = drm_to_adev(dev); 1755 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1756 1757 amdgpu_irq_put(adev, &adev->crtc_irq, idx); 1758 } 1759 1760 /* 1761 * Debugfs info 1762 */ 1763 #if defined(CONFIG_DEBUG_FS) 1764 1765 static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused) 1766 { 1767 struct amdgpu_device *adev = m->private; 1768 struct drm_amdgpu_info_firmware fw_info; 1769 struct drm_amdgpu_query_fw query_fw; 1770 struct atom_context *ctx = adev->mode_info.atom_context; 1771 uint8_t smu_program, smu_major, smu_minor, smu_debug; 1772 int ret, i; 1773 1774 static const char *ta_fw_name[TA_FW_TYPE_MAX_INDEX] = { 1775 #define TA_FW_NAME(type)[TA_FW_TYPE_PSP_##type] = #type 1776 TA_FW_NAME(XGMI), 1777 TA_FW_NAME(RAS), 1778 TA_FW_NAME(HDCP), 1779 TA_FW_NAME(DTM), 1780 TA_FW_NAME(RAP), 1781 TA_FW_NAME(SECUREDISPLAY), 1782 #undef TA_FW_NAME 1783 }; 1784 1785 /* VCE */ 1786 query_fw.fw_type = AMDGPU_INFO_FW_VCE; 1787 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1788 if (ret) 1789 return ret; 1790 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n", 1791 fw_info.feature, fw_info.ver); 1792 1793 /* UVD */ 1794 query_fw.fw_type = AMDGPU_INFO_FW_UVD; 1795 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1796 if (ret) 1797 return ret; 1798 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n", 1799 fw_info.feature, fw_info.ver); 1800 1801 /* GMC */ 1802 query_fw.fw_type = AMDGPU_INFO_FW_GMC; 1803 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1804 if (ret) 1805 return ret; 1806 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n", 1807 fw_info.feature, fw_info.ver); 1808 1809 /* ME */ 1810 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME; 1811 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1812 if (ret) 1813 return ret; 1814 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n", 1815 fw_info.feature, fw_info.ver); 1816 1817 /* PFP */ 1818 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP; 1819 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1820 if (ret) 1821 return ret; 1822 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n", 1823 fw_info.feature, fw_info.ver); 1824 1825 /* CE */ 1826 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE; 1827 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1828 if (ret) 1829 return ret; 1830 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n", 1831 fw_info.feature, fw_info.ver); 1832 1833 /* RLC */ 1834 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC; 1835 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1836 if (ret) 1837 return ret; 1838 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n", 1839 fw_info.feature, fw_info.ver); 1840 1841 /* RLC SAVE RESTORE LIST CNTL */ 1842 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL; 1843 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1844 if (ret) 1845 return ret; 1846 seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n", 1847 fw_info.feature, fw_info.ver); 1848 1849 /* RLC SAVE RESTORE LIST GPM MEM */ 1850 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM; 1851 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1852 if (ret) 1853 return ret; 1854 seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n", 1855 fw_info.feature, fw_info.ver); 1856 1857 /* RLC SAVE RESTORE LIST SRM MEM */ 1858 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM; 1859 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1860 if (ret) 1861 return ret; 1862 seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n", 1863 fw_info.feature, fw_info.ver); 1864 1865 /* RLCP */ 1866 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCP; 1867 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1868 if (ret) 1869 return ret; 1870 seq_printf(m, "RLCP feature version: %u, firmware version: 0x%08x\n", 1871 fw_info.feature, fw_info.ver); 1872 1873 /* RLCV */ 1874 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCV; 1875 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1876 if (ret) 1877 return ret; 1878 seq_printf(m, "RLCV feature version: %u, firmware version: 0x%08x\n", 1879 fw_info.feature, fw_info.ver); 1880 1881 /* MEC */ 1882 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC; 1883 query_fw.index = 0; 1884 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1885 if (ret) 1886 return ret; 1887 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n", 1888 fw_info.feature, fw_info.ver); 1889 1890 /* MEC2 */ 1891 if (adev->gfx.mec2_fw) { 1892 query_fw.index = 1; 1893 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1894 if (ret) 1895 return ret; 1896 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n", 1897 fw_info.feature, fw_info.ver); 1898 } 1899 1900 /* IMU */ 1901 query_fw.fw_type = AMDGPU_INFO_FW_IMU; 1902 query_fw.index = 0; 1903 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1904 if (ret) 1905 return ret; 1906 seq_printf(m, "IMU feature version: %u, firmware version: 0x%08x\n", 1907 fw_info.feature, fw_info.ver); 1908 1909 /* PSP SOS */ 1910 query_fw.fw_type = AMDGPU_INFO_FW_SOS; 1911 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1912 if (ret) 1913 return ret; 1914 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n", 1915 fw_info.feature, fw_info.ver); 1916 1917 1918 /* PSP ASD */ 1919 query_fw.fw_type = AMDGPU_INFO_FW_ASD; 1920 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1921 if (ret) 1922 return ret; 1923 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n", 1924 fw_info.feature, fw_info.ver); 1925 1926 query_fw.fw_type = AMDGPU_INFO_FW_TA; 1927 for (i = TA_FW_TYPE_PSP_XGMI; i < TA_FW_TYPE_MAX_INDEX; i++) { 1928 query_fw.index = i; 1929 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1930 if (ret) 1931 continue; 1932 1933 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n", 1934 ta_fw_name[i], fw_info.feature, fw_info.ver); 1935 } 1936 1937 /* SMC */ 1938 query_fw.fw_type = AMDGPU_INFO_FW_SMC; 1939 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1940 if (ret) 1941 return ret; 1942 smu_program = (fw_info.ver >> 24) & 0xff; 1943 smu_major = (fw_info.ver >> 16) & 0xff; 1944 smu_minor = (fw_info.ver >> 8) & 0xff; 1945 smu_debug = (fw_info.ver >> 0) & 0xff; 1946 seq_printf(m, "SMC feature version: %u, program: %d, firmware version: 0x%08x (%d.%d.%d)\n", 1947 fw_info.feature, smu_program, fw_info.ver, smu_major, smu_minor, smu_debug); 1948 1949 /* MP5 */ 1950 query_fw.fw_type = AMDGPU_INFO_FW_MP5; 1951 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1952 if (ret) 1953 return ret; 1954 seq_printf(m, "MP5 feature version: %u, firmware version: 0x%08x\n", 1955 fw_info.feature, fw_info.ver); 1956 1957 /* SDMA */ 1958 query_fw.fw_type = AMDGPU_INFO_FW_SDMA; 1959 for (i = 0; i < adev->sdma.num_instances; i++) { 1960 query_fw.index = i; 1961 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1962 if (ret) 1963 return ret; 1964 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n", 1965 i, fw_info.feature, fw_info.ver); 1966 } 1967 1968 /* VCN */ 1969 query_fw.fw_type = AMDGPU_INFO_FW_VCN; 1970 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1971 if (ret) 1972 return ret; 1973 seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n", 1974 fw_info.feature, fw_info.ver); 1975 1976 /* DMCU */ 1977 query_fw.fw_type = AMDGPU_INFO_FW_DMCU; 1978 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1979 if (ret) 1980 return ret; 1981 seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n", 1982 fw_info.feature, fw_info.ver); 1983 1984 /* DMCUB */ 1985 query_fw.fw_type = AMDGPU_INFO_FW_DMCUB; 1986 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1987 if (ret) 1988 return ret; 1989 seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n", 1990 fw_info.feature, fw_info.ver); 1991 1992 /* TOC */ 1993 query_fw.fw_type = AMDGPU_INFO_FW_TOC; 1994 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1995 if (ret) 1996 return ret; 1997 seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n", 1998 fw_info.feature, fw_info.ver); 1999 2000 /* CAP */ 2001 if (adev->psp.cap_fw) { 2002 query_fw.fw_type = AMDGPU_INFO_FW_CAP; 2003 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 2004 if (ret) 2005 return ret; 2006 seq_printf(m, "CAP feature version: %u, firmware version: 0x%08x\n", 2007 fw_info.feature, fw_info.ver); 2008 } 2009 2010 /* MES_KIQ */ 2011 query_fw.fw_type = AMDGPU_INFO_FW_MES_KIQ; 2012 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 2013 if (ret) 2014 return ret; 2015 seq_printf(m, "MES_KIQ feature version: %u, firmware version: 0x%08x\n", 2016 fw_info.feature, fw_info.ver); 2017 2018 /* MES */ 2019 query_fw.fw_type = AMDGPU_INFO_FW_MES; 2020 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 2021 if (ret) 2022 return ret; 2023 seq_printf(m, "MES feature version: %u, firmware version: 0x%08x\n", 2024 fw_info.feature, fw_info.ver); 2025 2026 /* VPE */ 2027 query_fw.fw_type = AMDGPU_INFO_FW_VPE; 2028 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 2029 if (ret) 2030 return ret; 2031 seq_printf(m, "VPE feature version: %u, firmware version: 0x%08x\n", 2032 fw_info.feature, fw_info.ver); 2033 2034 seq_printf(m, "VBIOS version: %s\n", ctx->vbios_pn); 2035 2036 return 0; 2037 } 2038 2039 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_firmware_info); 2040 2041 #endif 2042 2043 void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev) 2044 { 2045 #if defined(CONFIG_DEBUG_FS) 2046 struct drm_minor *minor = adev_to_drm(adev)->primary; 2047 struct dentry *root = minor->debugfs_root; 2048 2049 debugfs_create_file("amdgpu_firmware_info", 0444, root, 2050 adev, &amdgpu_debugfs_firmware_info_fops); 2051 2052 #endif 2053 } 2054