1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include "amdgpu.h" 30 #include <drm/amdgpu_drm.h> 31 #include <drm/drm_drv.h> 32 #include <drm/drm_fb_helper.h> 33 #include "amdgpu_uvd.h" 34 #include "amdgpu_vce.h" 35 #include "atom.h" 36 37 #include <linux/vga_switcheroo.h> 38 #include <linux/slab.h> 39 #include <linux/uaccess.h> 40 #include <linux/pci.h> 41 #include <linux/pm_runtime.h> 42 #include "amdgpu_amdkfd.h" 43 #include "amdgpu_gem.h" 44 #include "amdgpu_display.h" 45 #include "amdgpu_ras.h" 46 #include "amdgpu_reset.h" 47 #include "amd_pcie.h" 48 #include "amdgpu_userq.h" 49 #include "amdgpu_video_codecs.h" 50 51 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev) 52 { 53 struct amdgpu_gpu_instance *gpu_instance; 54 int i; 55 56 mutex_lock(&mgpu_info.mutex); 57 58 for (i = 0; i < mgpu_info.num_gpu; i++) { 59 gpu_instance = &(mgpu_info.gpu_ins[i]); 60 if (gpu_instance->adev == adev) { 61 mgpu_info.gpu_ins[i] = 62 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1]; 63 mgpu_info.num_gpu--; 64 if (adev->flags & AMD_IS_APU) 65 mgpu_info.num_apu--; 66 else 67 mgpu_info.num_dgpu--; 68 break; 69 } 70 } 71 72 mutex_unlock(&mgpu_info.mutex); 73 } 74 75 /** 76 * amdgpu_driver_unload_kms - Main unload function for KMS. 77 * 78 * @dev: drm dev pointer 79 * 80 * This is the main unload function for KMS (all asics). 81 * Returns 0 on success. 82 */ 83 void amdgpu_driver_unload_kms(struct drm_device *dev) 84 { 85 struct amdgpu_device *adev = drm_to_adev(dev); 86 87 if (adev == NULL || !adev->num_ip_blocks) 88 return; 89 90 amdgpu_unregister_gpu_instance(adev); 91 92 if (adev->rmmio == NULL) 93 return; 94 95 if (amdgpu_acpi_smart_shift_update(adev, AMDGPU_SS_DRV_UNLOAD)) 96 drm_warn(dev, "smart shift update failed\n"); 97 98 amdgpu_acpi_fini(adev); 99 amdgpu_device_fini_hw(adev); 100 } 101 102 void amdgpu_register_gpu_instance(struct amdgpu_device *adev) 103 { 104 struct amdgpu_gpu_instance *gpu_instance; 105 106 mutex_lock(&mgpu_info.mutex); 107 108 if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) { 109 drm_err(adev_to_drm(adev), "Cannot register more gpu instance\n"); 110 mutex_unlock(&mgpu_info.mutex); 111 return; 112 } 113 114 gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]); 115 gpu_instance->adev = adev; 116 gpu_instance->mgpu_fan_enabled = 0; 117 118 mgpu_info.num_gpu++; 119 if (adev->flags & AMD_IS_APU) 120 mgpu_info.num_apu++; 121 else 122 mgpu_info.num_dgpu++; 123 124 mutex_unlock(&mgpu_info.mutex); 125 } 126 127 /** 128 * amdgpu_driver_load_kms - Main load function for KMS. 129 * 130 * @adev: pointer to struct amdgpu_device 131 * @flags: device flags 132 * 133 * This is the main load function for KMS (all asics). 134 * Returns 0 on success, error on failure. 135 */ 136 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags) 137 { 138 struct drm_device *dev; 139 int r, acpi_status; 140 141 dev = adev_to_drm(adev); 142 143 /* amdgpu_device_init should report only fatal error 144 * like memory allocation failure or iomapping failure, 145 * or memory manager initialization failure, it must 146 * properly initialize the GPU MC controller and permit 147 * VRAM allocation 148 */ 149 r = amdgpu_device_init(adev, flags); 150 if (r) { 151 dev_err(dev->dev, "Fatal error during GPU init\n"); 152 goto out; 153 } 154 155 amdgpu_device_detect_runtime_pm_mode(adev); 156 157 /* Call ACPI methods: require modeset init 158 * but failure is not fatal 159 */ 160 161 acpi_status = amdgpu_acpi_init(adev); 162 if (acpi_status) 163 dev_dbg(dev->dev, "Error during ACPI methods call\n"); 164 165 if (amdgpu_acpi_smart_shift_update(adev, AMDGPU_SS_DRV_LOAD)) 166 drm_warn(dev, "smart shift update failed\n"); 167 168 out: 169 if (r) 170 amdgpu_driver_unload_kms(dev); 171 172 return r; 173 } 174 175 static enum amd_ip_block_type 176 amdgpu_ip_get_block_type(struct amdgpu_device *adev, uint32_t ip) 177 { 178 enum amd_ip_block_type type; 179 180 switch (ip) { 181 case AMDGPU_HW_IP_GFX: 182 type = AMD_IP_BLOCK_TYPE_GFX; 183 break; 184 case AMDGPU_HW_IP_COMPUTE: 185 type = AMD_IP_BLOCK_TYPE_GFX; 186 break; 187 case AMDGPU_HW_IP_DMA: 188 type = AMD_IP_BLOCK_TYPE_SDMA; 189 break; 190 case AMDGPU_HW_IP_UVD: 191 case AMDGPU_HW_IP_UVD_ENC: 192 type = AMD_IP_BLOCK_TYPE_UVD; 193 break; 194 case AMDGPU_HW_IP_VCE: 195 type = AMD_IP_BLOCK_TYPE_VCE; 196 break; 197 case AMDGPU_HW_IP_VCN_DEC: 198 case AMDGPU_HW_IP_VCN_ENC: 199 type = AMD_IP_BLOCK_TYPE_VCN; 200 break; 201 case AMDGPU_HW_IP_VCN_JPEG: 202 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 203 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 204 break; 205 case AMDGPU_HW_IP_VPE: 206 type = AMD_IP_BLOCK_TYPE_VPE; 207 break; 208 default: 209 type = AMD_IP_BLOCK_TYPE_NUM; 210 break; 211 } 212 213 return type; 214 } 215 216 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, 217 struct drm_amdgpu_query_fw *query_fw, 218 struct amdgpu_device *adev) 219 { 220 switch (query_fw->fw_type) { 221 case AMDGPU_INFO_FW_VCE: 222 fw_info->ver = adev->vce.fw_version; 223 fw_info->feature = adev->vce.fb_version; 224 break; 225 case AMDGPU_INFO_FW_UVD: 226 fw_info->ver = adev->uvd.fw_version; 227 fw_info->feature = 0; 228 break; 229 case AMDGPU_INFO_FW_VCN: 230 fw_info->ver = adev->vcn.fw_version; 231 fw_info->feature = 0; 232 break; 233 case AMDGPU_INFO_FW_GMC: 234 fw_info->ver = adev->gmc.fw_version; 235 fw_info->feature = 0; 236 break; 237 case AMDGPU_INFO_FW_GFX_ME: 238 fw_info->ver = adev->gfx.me_fw_version; 239 fw_info->feature = adev->gfx.me_feature_version; 240 break; 241 case AMDGPU_INFO_FW_GFX_PFP: 242 fw_info->ver = adev->gfx.pfp_fw_version; 243 fw_info->feature = adev->gfx.pfp_feature_version; 244 break; 245 case AMDGPU_INFO_FW_GFX_CE: 246 fw_info->ver = adev->gfx.ce_fw_version; 247 fw_info->feature = adev->gfx.ce_feature_version; 248 break; 249 case AMDGPU_INFO_FW_GFX_RLC: 250 fw_info->ver = adev->gfx.rlc_fw_version; 251 fw_info->feature = adev->gfx.rlc_feature_version; 252 break; 253 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL: 254 fw_info->ver = adev->gfx.rlc_srlc_fw_version; 255 fw_info->feature = adev->gfx.rlc_srlc_feature_version; 256 break; 257 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM: 258 fw_info->ver = adev->gfx.rlc_srlg_fw_version; 259 fw_info->feature = adev->gfx.rlc_srlg_feature_version; 260 break; 261 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM: 262 fw_info->ver = adev->gfx.rlc_srls_fw_version; 263 fw_info->feature = adev->gfx.rlc_srls_feature_version; 264 break; 265 case AMDGPU_INFO_FW_GFX_RLCP: 266 fw_info->ver = adev->gfx.rlcp_ucode_version; 267 fw_info->feature = adev->gfx.rlcp_ucode_feature_version; 268 break; 269 case AMDGPU_INFO_FW_GFX_RLCV: 270 fw_info->ver = adev->gfx.rlcv_ucode_version; 271 fw_info->feature = adev->gfx.rlcv_ucode_feature_version; 272 break; 273 case AMDGPU_INFO_FW_GFX_MEC: 274 if (query_fw->index == 0) { 275 fw_info->ver = adev->gfx.mec_fw_version; 276 fw_info->feature = adev->gfx.mec_feature_version; 277 } else if (query_fw->index == 1) { 278 fw_info->ver = adev->gfx.mec2_fw_version; 279 fw_info->feature = adev->gfx.mec2_feature_version; 280 } else 281 return -EINVAL; 282 break; 283 case AMDGPU_INFO_FW_SMC: 284 fw_info->ver = adev->pm.fw_version; 285 fw_info->feature = 0; 286 break; 287 case AMDGPU_INFO_FW_TA: 288 switch (query_fw->index) { 289 case TA_FW_TYPE_PSP_XGMI: 290 fw_info->ver = adev->psp.xgmi_context.context.bin_desc.fw_version; 291 fw_info->feature = adev->psp.xgmi_context.context 292 .bin_desc.feature_version; 293 break; 294 case TA_FW_TYPE_PSP_RAS: 295 fw_info->ver = adev->psp.ras_context.context.bin_desc.fw_version; 296 fw_info->feature = adev->psp.ras_context.context 297 .bin_desc.feature_version; 298 break; 299 case TA_FW_TYPE_PSP_HDCP: 300 fw_info->ver = adev->psp.hdcp_context.context.bin_desc.fw_version; 301 fw_info->feature = adev->psp.hdcp_context.context 302 .bin_desc.feature_version; 303 break; 304 case TA_FW_TYPE_PSP_DTM: 305 fw_info->ver = adev->psp.dtm_context.context.bin_desc.fw_version; 306 fw_info->feature = adev->psp.dtm_context.context 307 .bin_desc.feature_version; 308 break; 309 case TA_FW_TYPE_PSP_RAP: 310 fw_info->ver = adev->psp.rap_context.context.bin_desc.fw_version; 311 fw_info->feature = adev->psp.rap_context.context 312 .bin_desc.feature_version; 313 break; 314 case TA_FW_TYPE_PSP_SECUREDISPLAY: 315 fw_info->ver = adev->psp.securedisplay_context.context.bin_desc.fw_version; 316 fw_info->feature = 317 adev->psp.securedisplay_context.context.bin_desc 318 .feature_version; 319 break; 320 default: 321 return -EINVAL; 322 } 323 break; 324 case AMDGPU_INFO_FW_SDMA: 325 if (query_fw->index >= adev->sdma.num_instances) 326 return -EINVAL; 327 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version; 328 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version; 329 break; 330 case AMDGPU_INFO_FW_SOS: 331 fw_info->ver = adev->psp.sos.fw_version; 332 fw_info->feature = adev->psp.sos.feature_version; 333 break; 334 case AMDGPU_INFO_FW_ASD: 335 fw_info->ver = adev->psp.asd_context.bin_desc.fw_version; 336 fw_info->feature = adev->psp.asd_context.bin_desc.feature_version; 337 break; 338 case AMDGPU_INFO_FW_DMCU: 339 fw_info->ver = adev->dm.dmcu_fw_version; 340 fw_info->feature = 0; 341 break; 342 case AMDGPU_INFO_FW_DMCUB: 343 fw_info->ver = adev->dm.dmcub_fw_version; 344 fw_info->feature = 0; 345 break; 346 case AMDGPU_INFO_FW_TOC: 347 fw_info->ver = adev->psp.toc.fw_version; 348 fw_info->feature = adev->psp.toc.feature_version; 349 break; 350 case AMDGPU_INFO_FW_CAP: 351 fw_info->ver = adev->psp.cap_fw_version; 352 fw_info->feature = adev->psp.cap_feature_version; 353 break; 354 case AMDGPU_INFO_FW_MES_KIQ: 355 fw_info->ver = adev->mes.kiq_version & AMDGPU_MES_VERSION_MASK; 356 fw_info->feature = (adev->mes.kiq_version & AMDGPU_MES_FEAT_VERSION_MASK) 357 >> AMDGPU_MES_FEAT_VERSION_SHIFT; 358 break; 359 case AMDGPU_INFO_FW_MES: 360 fw_info->ver = adev->mes.sched_version & AMDGPU_MES_VERSION_MASK; 361 fw_info->feature = (adev->mes.sched_version & AMDGPU_MES_FEAT_VERSION_MASK) 362 >> AMDGPU_MES_FEAT_VERSION_SHIFT; 363 break; 364 case AMDGPU_INFO_FW_IMU: 365 fw_info->ver = adev->gfx.imu_fw_version; 366 fw_info->feature = 0; 367 break; 368 case AMDGPU_INFO_FW_VPE: 369 fw_info->ver = adev->vpe.fw_version; 370 fw_info->feature = adev->vpe.feature_version; 371 break; 372 default: 373 return -EINVAL; 374 } 375 return 0; 376 } 377 378 static int amdgpu_userq_metadata_info_gfx(struct amdgpu_device *adev, 379 struct drm_amdgpu_info *info, 380 struct drm_amdgpu_info_uq_metadata_gfx *meta) 381 { 382 int ret = -EOPNOTSUPP; 383 384 if (adev->gfx.funcs->get_gfx_shadow_info) { 385 struct amdgpu_gfx_shadow_info shadow = {}; 386 387 adev->gfx.funcs->get_gfx_shadow_info(adev, &shadow, true); 388 meta->shadow_size = shadow.shadow_size; 389 meta->shadow_alignment = shadow.shadow_alignment; 390 meta->csa_size = shadow.csa_size; 391 meta->csa_alignment = shadow.csa_alignment; 392 ret = 0; 393 } 394 395 return ret; 396 } 397 398 static int amdgpu_userq_metadata_info_compute(struct amdgpu_device *adev, 399 struct drm_amdgpu_info *info, 400 struct drm_amdgpu_info_uq_metadata_compute *meta) 401 { 402 int ret = -EOPNOTSUPP; 403 404 if (adev->gfx.funcs->get_gfx_shadow_info) { 405 struct amdgpu_gfx_shadow_info shadow = {}; 406 407 adev->gfx.funcs->get_gfx_shadow_info(adev, &shadow, true); 408 meta->eop_size = shadow.eop_size; 409 meta->eop_alignment = shadow.eop_alignment; 410 ret = 0; 411 } 412 413 return ret; 414 } 415 416 static int amdgpu_userq_metadata_info_sdma(struct amdgpu_device *adev, 417 struct drm_amdgpu_info *info, 418 struct drm_amdgpu_info_uq_metadata_sdma *meta) 419 { 420 int ret = -EOPNOTSUPP; 421 422 if (adev->sdma.get_csa_info) { 423 struct amdgpu_sdma_csa_info csa = {}; 424 425 adev->sdma.get_csa_info(adev, &csa); 426 meta->csa_size = csa.size; 427 meta->csa_alignment = csa.alignment; 428 ret = 0; 429 } 430 431 return ret; 432 } 433 434 static int amdgpu_hw_ip_info(struct amdgpu_device *adev, 435 struct drm_amdgpu_info *info, 436 struct drm_amdgpu_info_hw_ip *result) 437 { 438 uint32_t ib_start_alignment = 0; 439 uint32_t ib_size_alignment = 0; 440 enum amd_ip_block_type type; 441 unsigned int num_rings = 0; 442 uint32_t num_slots = 0; 443 unsigned int i, j; 444 445 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 446 return -EINVAL; 447 448 switch (info->query_hw_ip.type) { 449 case AMDGPU_HW_IP_GFX: 450 type = AMD_IP_BLOCK_TYPE_GFX; 451 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 452 if (adev->gfx.gfx_ring[i].sched.ready && 453 !adev->gfx.gfx_ring[i].no_user_submission) 454 ++num_rings; 455 456 if (!adev->gfx.disable_uq) { 457 for (i = 0; i < AMDGPU_MES_MAX_GFX_PIPES; i++) 458 num_slots += hweight32(adev->mes.gfx_hqd_mask[i]); 459 } 460 461 ib_start_alignment = 32; 462 ib_size_alignment = 32; 463 break; 464 case AMDGPU_HW_IP_COMPUTE: 465 type = AMD_IP_BLOCK_TYPE_GFX; 466 for (i = 0; i < adev->gfx.num_compute_rings; i++) 467 if (adev->gfx.compute_ring[i].sched.ready && 468 !adev->gfx.compute_ring[i].no_user_submission) 469 ++num_rings; 470 471 if (!adev->sdma.disable_uq) { 472 for (i = 0; i < AMDGPU_MES_MAX_COMPUTE_PIPES; i++) 473 num_slots += hweight32(adev->mes.compute_hqd_mask[i]); 474 } 475 476 ib_start_alignment = 32; 477 ib_size_alignment = 32; 478 break; 479 case AMDGPU_HW_IP_DMA: 480 type = AMD_IP_BLOCK_TYPE_SDMA; 481 for (i = 0; i < adev->sdma.num_instances; i++) 482 if (adev->sdma.instance[i].ring.sched.ready && 483 !adev->sdma.instance[i].ring.no_user_submission) 484 ++num_rings; 485 486 if (!adev->gfx.disable_uq) { 487 for (i = 0; i < AMDGPU_MES_MAX_SDMA_PIPES; i++) 488 num_slots += hweight32(adev->mes.sdma_hqd_mask[i]); 489 } 490 491 ib_start_alignment = 256; 492 ib_size_alignment = 4; 493 break; 494 case AMDGPU_HW_IP_UVD: 495 type = AMD_IP_BLOCK_TYPE_UVD; 496 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 497 if (adev->uvd.harvest_config & (1 << i)) 498 continue; 499 500 if (adev->uvd.inst[i].ring.sched.ready && 501 !adev->uvd.inst[i].ring.no_user_submission) 502 ++num_rings; 503 } 504 ib_start_alignment = 256; 505 ib_size_alignment = 64; 506 break; 507 case AMDGPU_HW_IP_VCE: 508 type = AMD_IP_BLOCK_TYPE_VCE; 509 for (i = 0; i < adev->vce.num_rings; i++) 510 if (adev->vce.ring[i].sched.ready && 511 !adev->vce.ring[i].no_user_submission) 512 ++num_rings; 513 ib_start_alignment = 256; 514 ib_size_alignment = 4; 515 break; 516 case AMDGPU_HW_IP_UVD_ENC: 517 type = AMD_IP_BLOCK_TYPE_UVD; 518 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 519 if (adev->uvd.harvest_config & (1 << i)) 520 continue; 521 522 for (j = 0; j < adev->uvd.num_enc_rings; j++) 523 if (adev->uvd.inst[i].ring_enc[j].sched.ready && 524 !adev->uvd.inst[i].ring_enc[j].no_user_submission) 525 ++num_rings; 526 } 527 ib_start_alignment = 256; 528 ib_size_alignment = 4; 529 break; 530 case AMDGPU_HW_IP_VCN_DEC: 531 type = AMD_IP_BLOCK_TYPE_VCN; 532 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 533 if (adev->vcn.harvest_config & (1 << i)) 534 continue; 535 536 if (adev->vcn.inst[i].ring_dec.sched.ready && 537 !adev->vcn.inst[i].ring_dec.no_user_submission) 538 ++num_rings; 539 } 540 ib_start_alignment = 256; 541 ib_size_alignment = 64; 542 break; 543 case AMDGPU_HW_IP_VCN_ENC: 544 type = AMD_IP_BLOCK_TYPE_VCN; 545 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 546 if (adev->vcn.harvest_config & (1 << i)) 547 continue; 548 549 for (j = 0; j < adev->vcn.inst[i].num_enc_rings; j++) 550 if (adev->vcn.inst[i].ring_enc[j].sched.ready && 551 !adev->vcn.inst[i].ring_enc[j].no_user_submission) 552 ++num_rings; 553 } 554 ib_start_alignment = 256; 555 ib_size_alignment = 4; 556 break; 557 case AMDGPU_HW_IP_VCN_JPEG: 558 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 559 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 560 561 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { 562 if (adev->jpeg.harvest_config & (1 << i)) 563 continue; 564 565 for (j = 0; j < adev->jpeg.num_jpeg_rings; j++) 566 if (adev->jpeg.inst[i].ring_dec[j].sched.ready && 567 !adev->jpeg.inst[i].ring_dec[j].no_user_submission) 568 ++num_rings; 569 } 570 ib_start_alignment = 256; 571 ib_size_alignment = 64; 572 break; 573 case AMDGPU_HW_IP_VPE: 574 type = AMD_IP_BLOCK_TYPE_VPE; 575 if (adev->vpe.ring.sched.ready && 576 !adev->vpe.ring.no_user_submission) 577 ++num_rings; 578 ib_start_alignment = 256; 579 ib_size_alignment = 4; 580 break; 581 default: 582 return -EINVAL; 583 } 584 585 for (i = 0; i < adev->num_ip_blocks; i++) 586 if (adev->ip_blocks[i].version->type == type && 587 adev->ip_blocks[i].status.valid) 588 break; 589 590 if (i == adev->num_ip_blocks) 591 return 0; 592 593 num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type], 594 num_rings); 595 596 result->hw_ip_version_major = adev->ip_blocks[i].version->major; 597 result->hw_ip_version_minor = adev->ip_blocks[i].version->minor; 598 599 if (adev->asic_type >= CHIP_VEGA10) { 600 switch (type) { 601 case AMD_IP_BLOCK_TYPE_GFX: 602 result->ip_discovery_version = 603 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, GC_HWIP, 0)); 604 break; 605 case AMD_IP_BLOCK_TYPE_SDMA: 606 result->ip_discovery_version = 607 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, SDMA0_HWIP, 0)); 608 break; 609 case AMD_IP_BLOCK_TYPE_UVD: 610 case AMD_IP_BLOCK_TYPE_VCN: 611 case AMD_IP_BLOCK_TYPE_JPEG: 612 result->ip_discovery_version = 613 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, UVD_HWIP, 0)); 614 break; 615 case AMD_IP_BLOCK_TYPE_VCE: 616 result->ip_discovery_version = 617 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, VCE_HWIP, 0)); 618 break; 619 case AMD_IP_BLOCK_TYPE_VPE: 620 result->ip_discovery_version = 621 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, VPE_HWIP, 0)); 622 break; 623 default: 624 result->ip_discovery_version = 0; 625 break; 626 } 627 } else { 628 result->ip_discovery_version = 0; 629 } 630 result->capabilities_flags = 0; 631 result->available_rings = (1 << num_rings) - 1; 632 result->userq_num_slots = num_slots; 633 result->ib_start_alignment = ib_start_alignment; 634 result->ib_size_alignment = ib_size_alignment; 635 return 0; 636 } 637 638 /* 639 * Userspace get information ioctl 640 */ 641 /** 642 * amdgpu_info_ioctl - answer a device specific request. 643 * 644 * @dev: drm device pointer 645 * @data: request object 646 * @filp: drm filp 647 * 648 * This function is used to pass device specific parameters to the userspace 649 * drivers. Examples include: pci device id, pipeline parms, tiling params, 650 * etc. (all asics). 651 * Returns 0 on success, -EINVAL on failure. 652 */ 653 int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 654 { 655 struct amdgpu_device *adev = drm_to_adev(dev); 656 struct drm_amdgpu_info *info = data; 657 struct amdgpu_mode_info *minfo = &adev->mode_info; 658 void __user *out = (void __user *)(uintptr_t)info->return_pointer; 659 struct amdgpu_fpriv *fpriv; 660 struct amdgpu_ip_block *ip_block; 661 enum amd_ip_block_type type; 662 struct amdgpu_xcp *xcp; 663 u32 count, inst_mask; 664 uint32_t size = info->return_size; 665 struct drm_crtc *crtc; 666 uint32_t ui32 = 0; 667 uint64_t ui64 = 0; 668 int i, found, ret; 669 int ui32_size = sizeof(ui32); 670 671 if (!info->return_size || !info->return_pointer) 672 return -EINVAL; 673 674 switch (info->query) { 675 case AMDGPU_INFO_ACCEL_WORKING: 676 ui32 = adev->accel_working; 677 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 678 case AMDGPU_INFO_CRTC_FROM_ID: 679 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { 680 crtc = (struct drm_crtc *)minfo->crtcs[i]; 681 if (crtc && crtc->base.id == info->mode_crtc.id) { 682 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 683 684 ui32 = amdgpu_crtc->crtc_id; 685 found = 1; 686 break; 687 } 688 } 689 if (!found) { 690 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); 691 return -EINVAL; 692 } 693 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 694 case AMDGPU_INFO_HW_IP_INFO: { 695 struct drm_amdgpu_info_hw_ip ip = {}; 696 697 ret = amdgpu_hw_ip_info(adev, info, &ip); 698 if (ret) 699 return ret; 700 701 ret = copy_to_user(out, &ip, min_t(size_t, size, sizeof(ip))); 702 return ret ? -EFAULT : 0; 703 } 704 case AMDGPU_INFO_HW_IP_COUNT: { 705 fpriv = (struct amdgpu_fpriv *)filp->driver_priv; 706 type = amdgpu_ip_get_block_type(adev, info->query_hw_ip.type); 707 ip_block = amdgpu_device_ip_get_ip_block(adev, type); 708 709 if (!ip_block || !ip_block->status.valid) 710 return -EINVAL; 711 712 if (adev->xcp_mgr && adev->xcp_mgr->num_xcps > 0 && 713 fpriv->xcp_id < adev->xcp_mgr->num_xcps) { 714 xcp = &adev->xcp_mgr->xcp[fpriv->xcp_id]; 715 switch (type) { 716 case AMD_IP_BLOCK_TYPE_GFX: 717 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &inst_mask); 718 if (ret) 719 return ret; 720 count = hweight32(inst_mask); 721 break; 722 case AMD_IP_BLOCK_TYPE_SDMA: 723 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_SDMA, &inst_mask); 724 if (ret) 725 return ret; 726 count = hweight32(inst_mask); 727 break; 728 case AMD_IP_BLOCK_TYPE_JPEG: 729 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask); 730 if (ret) 731 return ret; 732 count = hweight32(inst_mask) * adev->jpeg.num_jpeg_rings; 733 break; 734 case AMD_IP_BLOCK_TYPE_VCN: 735 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask); 736 if (ret) 737 return ret; 738 count = hweight32(inst_mask); 739 break; 740 default: 741 return -EINVAL; 742 } 743 744 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; 745 } 746 747 switch (type) { 748 case AMD_IP_BLOCK_TYPE_GFX: 749 case AMD_IP_BLOCK_TYPE_VCE: 750 count = 1; 751 break; 752 case AMD_IP_BLOCK_TYPE_SDMA: 753 count = adev->sdma.num_instances; 754 break; 755 case AMD_IP_BLOCK_TYPE_JPEG: 756 count = adev->jpeg.num_jpeg_inst * adev->jpeg.num_jpeg_rings; 757 break; 758 case AMD_IP_BLOCK_TYPE_VCN: 759 count = adev->vcn.num_vcn_inst; 760 break; 761 case AMD_IP_BLOCK_TYPE_UVD: 762 count = adev->uvd.num_uvd_inst; 763 break; 764 case AMD_IP_BLOCK_TYPE_VPE: 765 count = adev->vpe.num_instances; 766 break; 767 /* For all other IP block types not listed in the switch statement 768 * the ip status is valid here and the instance count is one. 769 */ 770 default: 771 count = 1; 772 break; 773 } 774 775 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; 776 } 777 case AMDGPU_INFO_TIMESTAMP: 778 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev); 779 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 780 case AMDGPU_INFO_FW_VERSION: { 781 struct drm_amdgpu_info_firmware fw_info; 782 783 /* We only support one instance of each IP block right now. */ 784 if (info->query_fw.ip_instance != 0) 785 return -EINVAL; 786 787 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev); 788 if (ret) 789 return ret; 790 791 return copy_to_user(out, &fw_info, 792 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0; 793 } 794 case AMDGPU_INFO_NUM_BYTES_MOVED: 795 ui64 = atomic64_read(&adev->num_bytes_moved); 796 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 797 case AMDGPU_INFO_NUM_EVICTIONS: 798 ui64 = atomic64_read(&adev->num_evictions); 799 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 800 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS: 801 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults); 802 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 803 case AMDGPU_INFO_VRAM_USAGE: 804 ui64 = ttm_resource_manager_used(&adev->mman.vram_mgr.manager) ? 805 ttm_resource_manager_usage(&adev->mman.vram_mgr.manager) : 0; 806 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 807 case AMDGPU_INFO_VIS_VRAM_USAGE: 808 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr); 809 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 810 case AMDGPU_INFO_GTT_USAGE: 811 ui64 = ttm_resource_manager_usage(&adev->mman.gtt_mgr.manager); 812 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 813 case AMDGPU_INFO_GDS_CONFIG: { 814 struct drm_amdgpu_info_gds gds_info; 815 816 memset(&gds_info, 0, sizeof(gds_info)); 817 gds_info.compute_partition_size = adev->gds.gds_size; 818 gds_info.gds_total_size = adev->gds.gds_size; 819 gds_info.gws_per_compute_partition = adev->gds.gws_size; 820 gds_info.oa_per_compute_partition = adev->gds.oa_size; 821 return copy_to_user(out, &gds_info, 822 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0; 823 } 824 case AMDGPU_INFO_VRAM_GTT: { 825 struct drm_amdgpu_info_vram_gtt vram_gtt; 826 827 vram_gtt.vram_size = adev->gmc.real_vram_size - 828 atomic64_read(&adev->vram_pin_size) - 829 AMDGPU_VM_RESERVED_VRAM; 830 vram_gtt.vram_cpu_accessible_size = 831 min(adev->gmc.visible_vram_size - 832 atomic64_read(&adev->visible_pin_size), 833 vram_gtt.vram_size); 834 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size; 835 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size); 836 return copy_to_user(out, &vram_gtt, 837 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; 838 } 839 case AMDGPU_INFO_MEMORY: { 840 struct drm_amdgpu_memory_info mem; 841 struct ttm_resource_manager *gtt_man = 842 &adev->mman.gtt_mgr.manager; 843 struct ttm_resource_manager *vram_man = 844 &adev->mman.vram_mgr.manager; 845 846 memset(&mem, 0, sizeof(mem)); 847 mem.vram.total_heap_size = adev->gmc.real_vram_size; 848 mem.vram.usable_heap_size = adev->gmc.real_vram_size - 849 atomic64_read(&adev->vram_pin_size) - 850 AMDGPU_VM_RESERVED_VRAM; 851 mem.vram.heap_usage = ttm_resource_manager_used(&adev->mman.vram_mgr.manager) ? 852 ttm_resource_manager_usage(vram_man) : 0; 853 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4; 854 855 mem.cpu_accessible_vram.total_heap_size = 856 adev->gmc.visible_vram_size; 857 mem.cpu_accessible_vram.usable_heap_size = 858 min(adev->gmc.visible_vram_size - 859 atomic64_read(&adev->visible_pin_size), 860 mem.vram.usable_heap_size); 861 mem.cpu_accessible_vram.heap_usage = 862 amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr); 863 mem.cpu_accessible_vram.max_allocation = 864 mem.cpu_accessible_vram.usable_heap_size * 3 / 4; 865 866 mem.gtt.total_heap_size = gtt_man->size; 867 mem.gtt.usable_heap_size = mem.gtt.total_heap_size - 868 atomic64_read(&adev->gart_pin_size); 869 mem.gtt.heap_usage = ttm_resource_manager_usage(gtt_man); 870 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4; 871 872 return copy_to_user(out, &mem, 873 min((size_t)size, sizeof(mem))) 874 ? -EFAULT : 0; 875 } 876 case AMDGPU_INFO_READ_MMR_REG: { 877 unsigned int se_num = (info->read_mmr_reg.instance >> 878 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & 879 AMDGPU_INFO_MMR_SE_INDEX_MASK; 880 unsigned int sh_num = (info->read_mmr_reg.instance >> 881 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & 882 AMDGPU_INFO_MMR_SH_INDEX_MASK; 883 unsigned int alloc_size; 884 uint32_t *regs; 885 int ret; 886 887 /* set full masks if the userspace set all bits 888 * in the bitfields 889 */ 890 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) 891 se_num = 0xffffffff; 892 else if (se_num >= AMDGPU_GFX_MAX_SE) 893 return -EINVAL; 894 895 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) 896 sh_num = 0xffffffff; 897 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE) 898 return -EINVAL; 899 900 if (info->read_mmr_reg.count > 128) 901 return -EINVAL; 902 903 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), 904 GFP_KERNEL); 905 if (!regs) 906 return -ENOMEM; 907 908 down_read(&adev->reset_domain->sem); 909 alloc_size = info->read_mmr_reg.count * sizeof(*regs); 910 amdgpu_gfx_off_ctrl(adev, false); 911 ret = 0; 912 for (i = 0; i < info->read_mmr_reg.count; i++) { 913 if (amdgpu_asic_read_register(adev, se_num, sh_num, 914 info->read_mmr_reg.dword_offset + i, 915 ®s[i])) { 916 DRM_DEBUG_KMS("unallowed offset %#x\n", 917 info->read_mmr_reg.dword_offset + i); 918 ret = -EFAULT; 919 break; 920 } 921 } 922 amdgpu_gfx_off_ctrl(adev, true); 923 up_read(&adev->reset_domain->sem); 924 925 if (!ret) { 926 ret = copy_to_user(out, regs, min(size, alloc_size)) 927 ? -EFAULT : 0; 928 } 929 kfree(regs); 930 return ret; 931 } 932 case AMDGPU_INFO_DEV_INFO: { 933 struct drm_amdgpu_info_device *dev_info; 934 uint64_t vm_size; 935 uint32_t pcie_gen_mask, pcie_width_mask; 936 937 dev_info = kzalloc_obj(*dev_info); 938 if (!dev_info) 939 return -ENOMEM; 940 941 dev_info->device_id = adev->pdev->device; 942 dev_info->chip_rev = adev->rev_id; 943 dev_info->external_rev = adev->external_rev_id; 944 dev_info->pci_rev = adev->pdev->revision; 945 dev_info->family = adev->family; 946 dev_info->num_shader_engines = adev->gfx.config.max_shader_engines; 947 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 948 /* return all clocks in KHz */ 949 dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; 950 if (adev->pm.dpm_enabled) { 951 dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10; 952 dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10; 953 dev_info->min_engine_clock = amdgpu_dpm_get_sclk(adev, true) * 10; 954 dev_info->min_memory_clock = amdgpu_dpm_get_mclk(adev, true) * 10; 955 } else { 956 dev_info->max_engine_clock = 957 dev_info->min_engine_clock = 958 adev->clock.default_sclk * 10; 959 dev_info->max_memory_clock = 960 dev_info->min_memory_clock = 961 adev->clock.default_mclk * 10; 962 } 963 dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; 964 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se * 965 adev->gfx.config.max_shader_engines; 966 dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; 967 dev_info->ids_flags = 0; 968 if (adev->flags & AMD_IS_APU) 969 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION; 970 if (adev->gfx.mcbp) 971 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION; 972 if (amdgpu_is_tmz(adev)) 973 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ; 974 if (adev->gfx.config.ta_cntl2_truncate_coord_mode) 975 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD; 976 977 /* Gang submit is not supported under SRIOV currently */ 978 if (!amdgpu_sriov_vf(adev)) 979 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_GANG_SUBMIT; 980 981 if (amdgpu_passthrough(adev)) 982 dev_info->ids_flags |= (AMDGPU_IDS_FLAGS_MODE_PT << 983 AMDGPU_IDS_FLAGS_MODE_SHIFT) & 984 AMDGPU_IDS_FLAGS_MODE_MASK; 985 else if (amdgpu_sriov_vf(adev)) 986 dev_info->ids_flags |= (AMDGPU_IDS_FLAGS_MODE_VF << 987 AMDGPU_IDS_FLAGS_MODE_SHIFT) & 988 AMDGPU_IDS_FLAGS_MODE_MASK; 989 990 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 991 vm_size -= AMDGPU_VA_RESERVED_TOP; 992 993 /* Older VCE FW versions are buggy and can handle only 40bits */ 994 if (adev->vce.fw_version && 995 adev->vce.fw_version < AMDGPU_VCE_FW_53_45) 996 vm_size = min(vm_size, 1ULL << 40); 997 998 dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_BOTTOM; 999 dev_info->virtual_address_max = 1000 min(vm_size, AMDGPU_GMC_HOLE_START); 1001 1002 if (vm_size > AMDGPU_GMC_HOLE_START) { 1003 dev_info->high_va_offset = AMDGPU_GMC_HOLE_END; 1004 dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size; 1005 } 1006 dev_info->virtual_address_alignment = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 1007 dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE; 1008 dev_info->gart_page_size = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 1009 dev_info->cu_active_number = adev->gfx.cu_info.number; 1010 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; 1011 dev_info->ce_ram_size = adev->gfx.ce_ram_size; 1012 memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0], 1013 sizeof(adev->gfx.cu_info.ao_cu_bitmap)); 1014 memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], 1015 sizeof(dev_info->cu_bitmap)); 1016 dev_info->vram_type = adev->gmc.vram_type; 1017 dev_info->vram_bit_width = adev->gmc.vram_width; 1018 dev_info->vce_harvest_config = adev->vce.harvest_config; 1019 dev_info->gc_double_offchip_lds_buf = 1020 adev->gfx.config.double_offchip_lds_buf; 1021 dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size; 1022 dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs; 1023 dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh; 1024 dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches; 1025 dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth; 1026 dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth; 1027 dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads; 1028 1029 if (adev->family >= AMDGPU_FAMILY_NV) 1030 dev_info->pa_sc_tile_steering_override = 1031 adev->gfx.config.pa_sc_tile_steering_override; 1032 1033 dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask; 1034 1035 /* Combine the chip gen mask with the platform (CPU/mobo) mask. */ 1036 pcie_gen_mask = adev->pm.pcie_gen_mask & 1037 (adev->pm.pcie_gen_mask >> CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT); 1038 pcie_width_mask = adev->pm.pcie_mlw_mask & 1039 (adev->pm.pcie_mlw_mask >> CAIL_PCIE_LINK_WIDTH_SUPPORT_SHIFT); 1040 dev_info->pcie_gen = fls(pcie_gen_mask); 1041 dev_info->pcie_num_lanes = 1042 pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X32 ? 32 : 1043 pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X16 ? 16 : 1044 pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X12 ? 12 : 1045 pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X8 ? 8 : 1046 pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X4 ? 4 : 1047 pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X2 ? 2 : 1; 1048 1049 dev_info->tcp_cache_size = adev->gfx.config.gc_tcp_l1_size; 1050 dev_info->num_sqc_per_wgp = adev->gfx.config.gc_num_sqc_per_wgp; 1051 dev_info->sqc_data_cache_size = adev->gfx.config.gc_l1_data_cache_size_per_sqc; 1052 dev_info->sqc_inst_cache_size = adev->gfx.config.gc_l1_instruction_cache_size_per_sqc; 1053 dev_info->gl1c_cache_size = adev->gfx.config.gc_gl1c_size_per_instance * 1054 adev->gfx.config.gc_gl1c_per_sa; 1055 dev_info->gl2c_cache_size = adev->gfx.config.gc_gl2c_per_gpu; 1056 dev_info->mall_size = adev->gmc.mall_size; 1057 1058 1059 if (adev->gfx.funcs->get_gfx_shadow_info) { 1060 struct amdgpu_gfx_shadow_info shadow_info; 1061 1062 ret = amdgpu_gfx_get_gfx_shadow_info(adev, &shadow_info); 1063 if (!ret) { 1064 dev_info->shadow_size = shadow_info.shadow_size; 1065 dev_info->shadow_alignment = shadow_info.shadow_alignment; 1066 dev_info->csa_size = shadow_info.csa_size; 1067 dev_info->csa_alignment = shadow_info.csa_alignment; 1068 } 1069 } 1070 1071 dev_info->userq_ip_mask = amdgpu_userq_get_supported_ip_mask(adev); 1072 1073 ret = copy_to_user(out, dev_info, 1074 min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0; 1075 kfree(dev_info); 1076 return ret; 1077 } 1078 case AMDGPU_INFO_VCE_CLOCK_TABLE: { 1079 unsigned int i; 1080 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {}; 1081 struct amd_vce_state *vce_state; 1082 1083 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) { 1084 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i); 1085 if (vce_state) { 1086 vce_clk_table.entries[i].sclk = vce_state->sclk; 1087 vce_clk_table.entries[i].mclk = vce_state->mclk; 1088 vce_clk_table.entries[i].eclk = vce_state->evclk; 1089 vce_clk_table.num_valid_entries++; 1090 } 1091 } 1092 1093 return copy_to_user(out, &vce_clk_table, 1094 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0; 1095 } 1096 case AMDGPU_INFO_VBIOS: { 1097 uint32_t bios_size = adev->bios_size; 1098 1099 switch (info->vbios_info.type) { 1100 case AMDGPU_INFO_VBIOS_SIZE: 1101 return copy_to_user(out, &bios_size, 1102 min((size_t)size, sizeof(bios_size))) 1103 ? -EFAULT : 0; 1104 case AMDGPU_INFO_VBIOS_IMAGE: { 1105 uint8_t *bios; 1106 uint32_t bios_offset = info->vbios_info.offset; 1107 1108 if (bios_offset >= bios_size) 1109 return -EINVAL; 1110 1111 bios = adev->bios + bios_offset; 1112 return copy_to_user(out, bios, 1113 min((size_t)size, (size_t)(bios_size - bios_offset))) 1114 ? -EFAULT : 0; 1115 } 1116 case AMDGPU_INFO_VBIOS_INFO: { 1117 struct drm_amdgpu_info_vbios vbios_info = {}; 1118 struct atom_context *atom_context; 1119 1120 atom_context = adev->mode_info.atom_context; 1121 if (atom_context) { 1122 memcpy(vbios_info.name, atom_context->name, 1123 sizeof(atom_context->name)); 1124 memcpy(vbios_info.vbios_pn, atom_context->vbios_pn, 1125 sizeof(atom_context->vbios_pn)); 1126 vbios_info.version = atom_context->version; 1127 memcpy(vbios_info.vbios_ver_str, atom_context->vbios_ver_str, 1128 sizeof(atom_context->vbios_ver_str)); 1129 memcpy(vbios_info.date, atom_context->date, 1130 sizeof(atom_context->date)); 1131 } 1132 1133 return copy_to_user(out, &vbios_info, 1134 min((size_t)size, sizeof(vbios_info))) ? -EFAULT : 0; 1135 } 1136 default: 1137 DRM_DEBUG_KMS("Invalid request %d\n", 1138 info->vbios_info.type); 1139 return -EINVAL; 1140 } 1141 } 1142 case AMDGPU_INFO_NUM_HANDLES: { 1143 struct drm_amdgpu_info_num_handles handle; 1144 1145 switch (info->query_hw_ip.type) { 1146 case AMDGPU_HW_IP_UVD: 1147 /* Starting Polaris, we support unlimited UVD handles */ 1148 if (adev->asic_type < CHIP_POLARIS10) { 1149 handle.uvd_max_handles = adev->uvd.max_handles; 1150 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev); 1151 1152 return copy_to_user(out, &handle, 1153 min((size_t)size, sizeof(handle))) ? -EFAULT : 0; 1154 } else { 1155 return -ENODATA; 1156 } 1157 1158 break; 1159 default: 1160 return -EINVAL; 1161 } 1162 } 1163 case AMDGPU_INFO_SENSOR: { 1164 if (!adev->pm.dpm_enabled) 1165 return -ENOENT; 1166 1167 switch (info->sensor_info.type) { 1168 case AMDGPU_INFO_SENSOR_GFX_SCLK: 1169 /* get sclk in Mhz */ 1170 if (amdgpu_dpm_read_sensor(adev, 1171 AMDGPU_PP_SENSOR_GFX_SCLK, 1172 (void *)&ui32, &ui32_size)) { 1173 return -EINVAL; 1174 } 1175 ui32 /= 100; 1176 break; 1177 case AMDGPU_INFO_SENSOR_GFX_MCLK: 1178 /* get mclk in Mhz */ 1179 if (amdgpu_dpm_read_sensor(adev, 1180 AMDGPU_PP_SENSOR_GFX_MCLK, 1181 (void *)&ui32, &ui32_size)) { 1182 return -EINVAL; 1183 } 1184 ui32 /= 100; 1185 break; 1186 case AMDGPU_INFO_SENSOR_GPU_TEMP: 1187 /* get temperature in millidegrees C */ 1188 if (amdgpu_dpm_read_sensor(adev, 1189 AMDGPU_PP_SENSOR_GPU_TEMP, 1190 (void *)&ui32, &ui32_size)) { 1191 return -EINVAL; 1192 } 1193 break; 1194 case AMDGPU_INFO_SENSOR_GPU_LOAD: 1195 /* get GPU load */ 1196 if (amdgpu_dpm_read_sensor(adev, 1197 AMDGPU_PP_SENSOR_GPU_LOAD, 1198 (void *)&ui32, &ui32_size)) { 1199 return -EINVAL; 1200 } 1201 break; 1202 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER: 1203 /* get average GPU power */ 1204 if (amdgpu_dpm_read_sensor(adev, 1205 AMDGPU_PP_SENSOR_GPU_AVG_POWER, 1206 (void *)&ui32, &ui32_size)) { 1207 /* fall back to input power for backwards compat */ 1208 if (amdgpu_dpm_read_sensor(adev, 1209 AMDGPU_PP_SENSOR_GPU_INPUT_POWER, 1210 (void *)&ui32, &ui32_size)) { 1211 return -EINVAL; 1212 } 1213 } 1214 ui32 /= MILLIWATT_PER_WATT; 1215 break; 1216 case AMDGPU_INFO_SENSOR_GPU_INPUT_POWER: 1217 /* get input GPU power */ 1218 if (amdgpu_dpm_read_sensor(adev, 1219 AMDGPU_PP_SENSOR_GPU_INPUT_POWER, 1220 (void *)&ui32, &ui32_size)) { 1221 return -EINVAL; 1222 } 1223 ui32 /= MILLIWATT_PER_WATT; 1224 break; 1225 case AMDGPU_INFO_SENSOR_VDDNB: 1226 /* get VDDNB in millivolts */ 1227 if (amdgpu_dpm_read_sensor(adev, 1228 AMDGPU_PP_SENSOR_VDDNB, 1229 (void *)&ui32, &ui32_size)) { 1230 return -EINVAL; 1231 } 1232 break; 1233 case AMDGPU_INFO_SENSOR_VDDGFX: 1234 /* get VDDGFX in millivolts */ 1235 if (amdgpu_dpm_read_sensor(adev, 1236 AMDGPU_PP_SENSOR_VDDGFX, 1237 (void *)&ui32, &ui32_size)) { 1238 return -EINVAL; 1239 } 1240 break; 1241 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK: 1242 /* get stable pstate sclk in Mhz */ 1243 if (amdgpu_dpm_read_sensor(adev, 1244 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 1245 (void *)&ui32, &ui32_size)) { 1246 return -EINVAL; 1247 } 1248 ui32 /= 100; 1249 break; 1250 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK: 1251 /* get stable pstate mclk in Mhz */ 1252 if (amdgpu_dpm_read_sensor(adev, 1253 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 1254 (void *)&ui32, &ui32_size)) { 1255 return -EINVAL; 1256 } 1257 ui32 /= 100; 1258 break; 1259 case AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK: 1260 /* get peak pstate sclk in Mhz */ 1261 if (amdgpu_dpm_read_sensor(adev, 1262 AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK, 1263 (void *)&ui32, &ui32_size)) { 1264 return -EINVAL; 1265 } 1266 ui32 /= 100; 1267 break; 1268 case AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK: 1269 /* get peak pstate mclk in Mhz */ 1270 if (amdgpu_dpm_read_sensor(adev, 1271 AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK, 1272 (void *)&ui32, &ui32_size)) { 1273 return -EINVAL; 1274 } 1275 ui32 /= 100; 1276 break; 1277 default: 1278 DRM_DEBUG_KMS("Invalid request %d\n", 1279 info->sensor_info.type); 1280 return -EINVAL; 1281 } 1282 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 1283 } 1284 case AMDGPU_INFO_VRAM_LOST_COUNTER: 1285 ui32 = atomic_read(&adev->vram_lost_counter); 1286 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 1287 case AMDGPU_INFO_RAS_ENABLED_FEATURES: { 1288 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1289 uint64_t ras_mask; 1290 1291 if (!ras) 1292 return -EINVAL; 1293 ras_mask = (uint64_t)adev->ras_enabled << 32 | ras->features; 1294 1295 return copy_to_user(out, &ras_mask, 1296 min_t(u64, size, sizeof(ras_mask))) ? 1297 -EFAULT : 0; 1298 } 1299 case AMDGPU_INFO_VIDEO_CAPS: { 1300 const struct amdgpu_video_codecs *codecs; 1301 struct drm_amdgpu_info_video_caps *caps; 1302 int r; 1303 1304 if (!adev->asic_funcs->query_video_codecs) 1305 return -EINVAL; 1306 1307 switch (info->video_cap.type) { 1308 case AMDGPU_INFO_VIDEO_CAPS_DECODE: 1309 r = amdgpu_asic_query_video_codecs(adev, false, &codecs); 1310 if (r) 1311 return -EINVAL; 1312 break; 1313 case AMDGPU_INFO_VIDEO_CAPS_ENCODE: 1314 r = amdgpu_asic_query_video_codecs(adev, true, &codecs); 1315 if (r) 1316 return -EINVAL; 1317 break; 1318 default: 1319 DRM_DEBUG_KMS("Invalid request %d\n", 1320 info->video_cap.type); 1321 return -EINVAL; 1322 } 1323 1324 caps = kzalloc_obj(*caps); 1325 if (!caps) 1326 return -ENOMEM; 1327 1328 for (i = 0; i < codecs->codec_count; i++) { 1329 int idx = codecs->codec_array[i].codec_type; 1330 1331 switch (idx) { 1332 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2: 1333 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4: 1334 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1: 1335 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC: 1336 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC: 1337 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG: 1338 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9: 1339 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1: 1340 caps->codec_info[idx].valid = 1; 1341 caps->codec_info[idx].max_width = 1342 codecs->codec_array[i].max_width; 1343 caps->codec_info[idx].max_height = 1344 codecs->codec_array[i].max_height; 1345 caps->codec_info[idx].max_pixels_per_frame = 1346 codecs->codec_array[i].max_pixels_per_frame; 1347 caps->codec_info[idx].max_level = 1348 codecs->codec_array[i].max_level; 1349 break; 1350 default: 1351 break; 1352 } 1353 } 1354 r = copy_to_user(out, caps, 1355 min((size_t)size, sizeof(*caps))) ? -EFAULT : 0; 1356 kfree(caps); 1357 return r; 1358 } 1359 case AMDGPU_INFO_MAX_IBS: { 1360 uint32_t max_ibs[AMDGPU_HW_IP_NUM]; 1361 1362 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) 1363 max_ibs[i] = amdgpu_ring_max_ibs(i); 1364 1365 return copy_to_user(out, max_ibs, 1366 min((size_t)size, sizeof(max_ibs))) ? -EFAULT : 0; 1367 } 1368 case AMDGPU_INFO_GPUVM_FAULT: { 1369 struct amdgpu_fpriv *fpriv = filp->driver_priv; 1370 struct amdgpu_vm *vm = &fpriv->vm; 1371 struct drm_amdgpu_info_gpuvm_fault gpuvm_fault; 1372 unsigned long flags; 1373 1374 if (!vm) 1375 return -EINVAL; 1376 1377 memset(&gpuvm_fault, 0, sizeof(gpuvm_fault)); 1378 1379 amdgpu_pasid_lock(&flags); 1380 gpuvm_fault.addr = vm->fault_info.addr; 1381 gpuvm_fault.status = vm->fault_info.status; 1382 gpuvm_fault.vmhub = vm->fault_info.vmhub; 1383 amdgpu_pasid_unlock(flags); 1384 1385 return copy_to_user(out, &gpuvm_fault, 1386 min((size_t)size, sizeof(gpuvm_fault))) ? -EFAULT : 0; 1387 } 1388 case AMDGPU_INFO_UQ_FW_AREAS: { 1389 struct drm_amdgpu_info_uq_metadata meta_info = {}; 1390 1391 switch (info->query_hw_ip.type) { 1392 case AMDGPU_HW_IP_GFX: 1393 ret = amdgpu_userq_metadata_info_gfx(adev, info, &meta_info.gfx); 1394 if (ret) 1395 return ret; 1396 1397 ret = copy_to_user(out, &meta_info, 1398 min((size_t)size, sizeof(meta_info))) ? -EFAULT : 0; 1399 return 0; 1400 case AMDGPU_HW_IP_COMPUTE: 1401 ret = amdgpu_userq_metadata_info_compute(adev, info, &meta_info.compute); 1402 if (ret) 1403 return ret; 1404 1405 ret = copy_to_user(out, &meta_info, 1406 min((size_t)size, sizeof(meta_info))) ? -EFAULT : 0; 1407 return 0; 1408 case AMDGPU_HW_IP_DMA: 1409 ret = amdgpu_userq_metadata_info_sdma(adev, info, &meta_info.sdma); 1410 if (ret) 1411 return ret; 1412 1413 ret = copy_to_user(out, &meta_info, 1414 min((size_t)size, sizeof(meta_info))) ? -EFAULT : 0; 1415 return 0; 1416 default: 1417 return -EINVAL; 1418 } 1419 } 1420 default: 1421 DRM_DEBUG_KMS("Invalid request %d\n", info->query); 1422 return -EINVAL; 1423 } 1424 return 0; 1425 } 1426 1427 /** 1428 * amdgpu_proc_options_ioctl - set per-fd user options 1429 * 1430 * @dev: drm dev pointer 1431 * @data: pointer to struct drm_amdgpu_proc_options 1432 * @filp: drm file 1433 * 1434 * Sets options stored on the per-file amdgpu_fpriv. Currently the only 1435 * supported option is %AMDGPU_PROC_OPTIONS_OP_KFD_SIGBUS_DELAY which 1436 * controls how KFD delivers SIGBUS for poison/RAS events to the calling 1437 * process (immediate, suppressed, or delayed by N milliseconds). 1438 */ 1439 int amdgpu_proc_options_ioctl(struct drm_device *dev, void *data, 1440 struct drm_file *filp) 1441 { 1442 struct drm_amdgpu_proc_options *args = data; 1443 1444 switch (args->op) { 1445 case AMDGPU_PROC_OPTIONS_OP_KFD_SIGBUS_DELAY: 1446 return amdgpu_amdkfd_set_sigbus_delay(current, 1447 args->kfd_sigbus_delay.value); 1448 default: 1449 DRM_DEBUG_KMS("Invalid user option op %u\n", args->op); 1450 return -EINVAL; 1451 } 1452 } 1453 1454 /** 1455 * amdgpu_driver_open_kms - drm callback for open 1456 * 1457 * @dev: drm dev pointer 1458 * @file_priv: drm file 1459 * 1460 * On device open, init vm on cayman+ (all asics). 1461 * Returns 0 on success, error on failure. 1462 */ 1463 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 1464 { 1465 struct amdgpu_device *adev = drm_to_adev(dev); 1466 struct amdgpu_fpriv *fpriv; 1467 struct drm_exec exec; 1468 int r, pasid = 0; 1469 1470 /* Ensure IB tests are run on ring */ 1471 flush_delayed_work(&adev->delayed_init_work); 1472 1473 1474 if (amdgpu_ras_intr_triggered()) { 1475 DRM_ERROR("RAS Intr triggered, device disabled!!"); 1476 return -EHWPOISON; 1477 } 1478 1479 file_priv->driver_priv = NULL; 1480 1481 r = pm_runtime_get_sync(dev->dev); 1482 if (r < 0) 1483 goto pm_put; 1484 1485 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 1486 if (unlikely(!fpriv)) { 1487 r = -ENOMEM; 1488 goto out_suspend; 1489 } 1490 1491 r = amdgpu_xcp_open_device(adev, fpriv, file_priv); 1492 if (r) 1493 goto error_pasid; 1494 1495 amdgpu_debugfs_vm_init(file_priv); 1496 1497 r = amdgpu_vm_init(adev, &fpriv->vm, fpriv->xcp_id); 1498 if (r) 1499 goto error_pasid; 1500 1501 pasid = amdgpu_pasid_alloc(16, fpriv); 1502 if (pasid < 0) { 1503 dev_warn(adev->dev, "No more PASIDs available!"); 1504 pasid = 0; 1505 } 1506 fpriv->vm.pasid = pasid; 1507 1508 drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES, 0); 1509 drm_exec_until_all_locked(&exec) { 1510 r = amdgpu_vm_lock_pd(&fpriv->vm, &exec, 0); 1511 drm_exec_retry_on_contention(&exec); 1512 if (unlikely(r)) 1513 goto error_vm; 1514 } 1515 1516 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL); 1517 drm_exec_fini(&exec); 1518 if (!fpriv->prt_va) { 1519 r = -ENOMEM; 1520 goto error_vm; 1521 } 1522 1523 if (adev->gfx.mcbp) { 1524 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK; 1525 1526 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj, 1527 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE); 1528 if (r) 1529 goto error_vm; 1530 } 1531 1532 r = amdgpu_seq64_map(adev, &fpriv->vm, &fpriv->seq64_va); 1533 if (r) 1534 goto error_vm; 1535 1536 xa_init_flags(&fpriv->bo_list_handles, XA_FLAGS_ALLOC1); 1537 1538 r = amdgpu_userq_mgr_init(&fpriv->userq_mgr, file_priv, adev); 1539 if (r) 1540 drm_warn(adev_to_drm(adev), 1541 "Failed to init usermode queue manager (%d), use legacy workload submission only\n", 1542 r); 1543 1544 amdgpu_evf_mgr_init(&fpriv->evf_mgr); 1545 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr, adev); 1546 1547 file_priv->driver_priv = fpriv; 1548 goto out_suspend; 1549 1550 error_vm: 1551 if (pasid) { 1552 amdgpu_pasid_free(pasid); 1553 pasid = 0; 1554 } 1555 1556 amdgpu_vm_fini(adev, &fpriv->vm); 1557 1558 error_pasid: 1559 kfree(fpriv); 1560 1561 out_suspend: 1562 pm_put: 1563 pm_runtime_put_autosuspend(dev->dev); 1564 1565 return r; 1566 } 1567 1568 /** 1569 * amdgpu_driver_postclose_kms - drm callback for post close 1570 * 1571 * @dev: drm dev pointer 1572 * @file_priv: drm file 1573 * 1574 * On device post close, tear down vm on cayman+ (all asics). 1575 */ 1576 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1577 struct drm_file *file_priv) 1578 { 1579 struct amdgpu_device *adev = drm_to_adev(dev); 1580 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1581 struct amdgpu_bo_list *list; 1582 struct amdgpu_bo *pd; 1583 unsigned long handle; 1584 u32 pasid; 1585 1586 if (!fpriv) 1587 return; 1588 1589 pm_runtime_get_sync(dev->dev); 1590 1591 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL) 1592 amdgpu_uvd_free_handles(adev, file_priv); 1593 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL) 1594 amdgpu_vce_free_handles(adev, file_priv); 1595 1596 if (fpriv->csa_va) { 1597 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK; 1598 1599 WARN_ON(amdgpu_unmap_static_csa(adev, &fpriv->vm, adev->virt.csa_obj, 1600 fpriv->csa_va, csa_addr)); 1601 fpriv->csa_va = NULL; 1602 } 1603 1604 amdgpu_seq64_unmap(adev, fpriv); 1605 1606 pasid = fpriv->vm.pasid; 1607 pd = amdgpu_bo_ref(fpriv->vm.root.bo); 1608 if (!WARN_ON(amdgpu_bo_reserve(pd, true))) { 1609 amdgpu_vm_bo_del(adev, fpriv->prt_va); 1610 amdgpu_bo_unreserve(pd); 1611 } 1612 1613 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); 1614 1615 if (pasid) 1616 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid); 1617 1618 amdgpu_vm_fini(adev, &fpriv->vm); 1619 amdgpu_bo_unref(&pd); 1620 1621 xa_for_each(&fpriv->bo_list_handles, handle, list) 1622 amdgpu_bo_list_put(list); 1623 xa_destroy(&fpriv->bo_list_handles); 1624 1625 kfree(fpriv); 1626 file_priv->driver_priv = NULL; 1627 1628 pm_runtime_put_autosuspend(dev->dev); 1629 } 1630 1631 1632 void amdgpu_driver_release_kms(struct drm_device *dev) 1633 { 1634 struct amdgpu_device *adev = drm_to_adev(dev); 1635 1636 amdgpu_device_fini_sw(adev); 1637 pci_set_drvdata(adev->pdev, NULL); 1638 } 1639 1640 /* 1641 * VBlank related functions. 1642 */ 1643 /** 1644 * amdgpu_get_vblank_counter_kms - get frame count 1645 * 1646 * @crtc: crtc to get the frame count from 1647 * 1648 * Gets the frame count on the requested crtc (all asics). 1649 * Returns frame count on success, -EINVAL on failure. 1650 */ 1651 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc) 1652 { 1653 struct drm_device *dev = crtc->dev; 1654 unsigned int pipe = crtc->index; 1655 struct amdgpu_device *adev = drm_to_adev(dev); 1656 int vpos, hpos, stat; 1657 u32 count; 1658 1659 if (pipe >= adev->mode_info.num_crtc) { 1660 DRM_ERROR("Invalid crtc %u\n", pipe); 1661 return -EINVAL; 1662 } 1663 1664 /* The hw increments its frame counter at start of vsync, not at start 1665 * of vblank, as is required by DRM core vblank counter handling. 1666 * Cook the hw count here to make it appear to the caller as if it 1667 * incremented at start of vblank. We measure distance to start of 1668 * vblank in vpos. vpos therefore will be >= 0 between start of vblank 1669 * and start of vsync, so vpos >= 0 means to bump the hw frame counter 1670 * result by 1 to give the proper appearance to caller. 1671 */ 1672 if (adev->mode_info.crtcs[pipe]) { 1673 /* Repeat readout if needed to provide stable result if 1674 * we cross start of vsync during the queries. 1675 */ 1676 do { 1677 count = amdgpu_display_vblank_get_counter(adev, pipe); 1678 /* Ask amdgpu_display_get_crtc_scanoutpos to return 1679 * vpos as distance to start of vblank, instead of 1680 * regular vertical scanout pos. 1681 */ 1682 stat = amdgpu_display_get_crtc_scanoutpos( 1683 dev, pipe, GET_DISTANCE_TO_VBLANKSTART, 1684 &vpos, &hpos, NULL, NULL, 1685 &adev->mode_info.crtcs[pipe]->base.hwmode); 1686 } while (count != amdgpu_display_vblank_get_counter(adev, pipe)); 1687 1688 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 1689 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 1690 DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 1691 } else { 1692 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", 1693 pipe, vpos); 1694 1695 /* Bump counter if we are at >= leading edge of vblank, 1696 * but before vsync where vpos would turn negative and 1697 * the hw counter really increments. 1698 */ 1699 if (vpos >= 0) 1700 count++; 1701 } 1702 } else { 1703 /* Fallback to use value as is. */ 1704 count = amdgpu_display_vblank_get_counter(adev, pipe); 1705 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 1706 } 1707 1708 return count; 1709 } 1710 1711 /** 1712 * amdgpu_enable_vblank_kms - enable vblank interrupt 1713 * 1714 * @crtc: crtc to enable vblank interrupt for 1715 * 1716 * Enable the interrupt on the requested crtc (all asics). 1717 * Returns 0 on success, -EINVAL on failure. 1718 */ 1719 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc) 1720 { 1721 struct drm_device *dev = crtc->dev; 1722 unsigned int pipe = crtc->index; 1723 struct amdgpu_device *adev = drm_to_adev(dev); 1724 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1725 1726 return amdgpu_irq_get(adev, &adev->crtc_irq, idx); 1727 } 1728 1729 /** 1730 * amdgpu_disable_vblank_kms - disable vblank interrupt 1731 * 1732 * @crtc: crtc to disable vblank interrupt for 1733 * 1734 * Disable the interrupt on the requested crtc (all asics). 1735 */ 1736 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc) 1737 { 1738 struct drm_device *dev = crtc->dev; 1739 unsigned int pipe = crtc->index; 1740 struct amdgpu_device *adev = drm_to_adev(dev); 1741 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1742 1743 amdgpu_irq_put(adev, &adev->crtc_irq, idx); 1744 } 1745 1746 /* 1747 * Debugfs info 1748 */ 1749 #if defined(CONFIG_DEBUG_FS) 1750 1751 static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused) 1752 { 1753 struct amdgpu_device *adev = m->private; 1754 struct drm_amdgpu_info_firmware fw_info; 1755 struct drm_amdgpu_query_fw query_fw; 1756 struct atom_context *ctx = adev->mode_info.atom_context; 1757 uint8_t smu_program, smu_major, smu_minor, smu_debug; 1758 int ret, i; 1759 1760 static const char *ta_fw_name[TA_FW_TYPE_MAX_INDEX] = { 1761 #define TA_FW_NAME(type)[TA_FW_TYPE_PSP_##type] = #type 1762 TA_FW_NAME(XGMI), 1763 TA_FW_NAME(RAS), 1764 TA_FW_NAME(HDCP), 1765 TA_FW_NAME(DTM), 1766 TA_FW_NAME(RAP), 1767 TA_FW_NAME(SECUREDISPLAY), 1768 #undef TA_FW_NAME 1769 }; 1770 1771 /* VCE */ 1772 query_fw.fw_type = AMDGPU_INFO_FW_VCE; 1773 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1774 if (ret) 1775 return ret; 1776 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n", 1777 fw_info.feature, fw_info.ver); 1778 1779 /* UVD */ 1780 query_fw.fw_type = AMDGPU_INFO_FW_UVD; 1781 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1782 if (ret) 1783 return ret; 1784 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n", 1785 fw_info.feature, fw_info.ver); 1786 1787 /* GMC */ 1788 query_fw.fw_type = AMDGPU_INFO_FW_GMC; 1789 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1790 if (ret) 1791 return ret; 1792 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n", 1793 fw_info.feature, fw_info.ver); 1794 1795 /* ME */ 1796 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME; 1797 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1798 if (ret) 1799 return ret; 1800 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n", 1801 fw_info.feature, fw_info.ver); 1802 1803 /* PFP */ 1804 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP; 1805 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1806 if (ret) 1807 return ret; 1808 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n", 1809 fw_info.feature, fw_info.ver); 1810 1811 /* CE */ 1812 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE; 1813 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1814 if (ret) 1815 return ret; 1816 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n", 1817 fw_info.feature, fw_info.ver); 1818 1819 /* RLC */ 1820 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC; 1821 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1822 if (ret) 1823 return ret; 1824 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n", 1825 fw_info.feature, fw_info.ver); 1826 1827 /* RLC SAVE RESTORE LIST CNTL */ 1828 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL; 1829 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1830 if (ret) 1831 return ret; 1832 seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n", 1833 fw_info.feature, fw_info.ver); 1834 1835 /* RLC SAVE RESTORE LIST GPM MEM */ 1836 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM; 1837 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1838 if (ret) 1839 return ret; 1840 seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n", 1841 fw_info.feature, fw_info.ver); 1842 1843 /* RLC SAVE RESTORE LIST SRM MEM */ 1844 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM; 1845 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1846 if (ret) 1847 return ret; 1848 seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n", 1849 fw_info.feature, fw_info.ver); 1850 1851 /* RLCP */ 1852 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCP; 1853 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1854 if (ret) 1855 return ret; 1856 seq_printf(m, "RLCP feature version: %u, firmware version: 0x%08x\n", 1857 fw_info.feature, fw_info.ver); 1858 1859 /* RLCV */ 1860 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCV; 1861 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1862 if (ret) 1863 return ret; 1864 seq_printf(m, "RLCV feature version: %u, firmware version: 0x%08x\n", 1865 fw_info.feature, fw_info.ver); 1866 1867 /* MEC */ 1868 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC; 1869 query_fw.index = 0; 1870 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1871 if (ret) 1872 return ret; 1873 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n", 1874 fw_info.feature, fw_info.ver); 1875 1876 /* MEC2 */ 1877 if (adev->gfx.mec2_fw) { 1878 query_fw.index = 1; 1879 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1880 if (ret) 1881 return ret; 1882 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n", 1883 fw_info.feature, fw_info.ver); 1884 } 1885 1886 /* IMU */ 1887 query_fw.fw_type = AMDGPU_INFO_FW_IMU; 1888 query_fw.index = 0; 1889 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1890 if (ret) 1891 return ret; 1892 seq_printf(m, "IMU feature version: %u, firmware version: 0x%08x\n", 1893 fw_info.feature, fw_info.ver); 1894 1895 /* PSP SOS */ 1896 query_fw.fw_type = AMDGPU_INFO_FW_SOS; 1897 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1898 if (ret) 1899 return ret; 1900 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n", 1901 fw_info.feature, fw_info.ver); 1902 1903 1904 /* PSP ASD */ 1905 query_fw.fw_type = AMDGPU_INFO_FW_ASD; 1906 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1907 if (ret) 1908 return ret; 1909 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n", 1910 fw_info.feature, fw_info.ver); 1911 1912 query_fw.fw_type = AMDGPU_INFO_FW_TA; 1913 for (i = TA_FW_TYPE_PSP_XGMI; i < TA_FW_TYPE_MAX_INDEX; i++) { 1914 query_fw.index = i; 1915 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1916 if (ret) 1917 continue; 1918 1919 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n", 1920 ta_fw_name[i], fw_info.feature, fw_info.ver); 1921 } 1922 1923 /* SMC */ 1924 query_fw.fw_type = AMDGPU_INFO_FW_SMC; 1925 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1926 if (ret) 1927 return ret; 1928 smu_program = (fw_info.ver >> 24) & 0xff; 1929 smu_major = (fw_info.ver >> 16) & 0xff; 1930 smu_minor = (fw_info.ver >> 8) & 0xff; 1931 smu_debug = (fw_info.ver >> 0) & 0xff; 1932 seq_printf(m, "SMC feature version: %u, program: %d, firmware version: 0x%08x (%d.%d.%d)\n", 1933 fw_info.feature, smu_program, fw_info.ver, smu_major, smu_minor, smu_debug); 1934 1935 /* SDMA */ 1936 query_fw.fw_type = AMDGPU_INFO_FW_SDMA; 1937 for (i = 0; i < adev->sdma.num_instances; i++) { 1938 query_fw.index = i; 1939 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1940 if (ret) 1941 return ret; 1942 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n", 1943 i, fw_info.feature, fw_info.ver); 1944 } 1945 1946 /* VCN */ 1947 query_fw.fw_type = AMDGPU_INFO_FW_VCN; 1948 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1949 if (ret) 1950 return ret; 1951 seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n", 1952 fw_info.feature, fw_info.ver); 1953 1954 /* DMCU */ 1955 query_fw.fw_type = AMDGPU_INFO_FW_DMCU; 1956 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1957 if (ret) 1958 return ret; 1959 seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n", 1960 fw_info.feature, fw_info.ver); 1961 1962 /* DMCUB */ 1963 query_fw.fw_type = AMDGPU_INFO_FW_DMCUB; 1964 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1965 if (ret) 1966 return ret; 1967 seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n", 1968 fw_info.feature, fw_info.ver); 1969 1970 /* TOC */ 1971 query_fw.fw_type = AMDGPU_INFO_FW_TOC; 1972 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1973 if (ret) 1974 return ret; 1975 seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n", 1976 fw_info.feature, fw_info.ver); 1977 1978 /* CAP */ 1979 if (adev->psp.cap_fw) { 1980 query_fw.fw_type = AMDGPU_INFO_FW_CAP; 1981 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1982 if (ret) 1983 return ret; 1984 seq_printf(m, "CAP feature version: %u, firmware version: 0x%08x\n", 1985 fw_info.feature, fw_info.ver); 1986 } 1987 1988 /* MES_KIQ */ 1989 query_fw.fw_type = AMDGPU_INFO_FW_MES_KIQ; 1990 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1991 if (ret) 1992 return ret; 1993 seq_printf(m, "MES_KIQ feature version: %u, firmware version: 0x%08x\n", 1994 fw_info.feature, fw_info.ver); 1995 1996 /* MES */ 1997 query_fw.fw_type = AMDGPU_INFO_FW_MES; 1998 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1999 if (ret) 2000 return ret; 2001 seq_printf(m, "MES feature version: %u, firmware version: 0x%08x\n", 2002 fw_info.feature, fw_info.ver); 2003 2004 /* VPE */ 2005 query_fw.fw_type = AMDGPU_INFO_FW_VPE; 2006 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 2007 if (ret) 2008 return ret; 2009 seq_printf(m, "VPE feature version: %u, firmware version: 0x%08x\n", 2010 fw_info.feature, fw_info.ver); 2011 2012 seq_printf(m, "VBIOS version: %s\n", ctx->vbios_pn); 2013 2014 return 0; 2015 } 2016 2017 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_firmware_info); 2018 2019 #endif 2020 2021 void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev) 2022 { 2023 #if defined(CONFIG_DEBUG_FS) 2024 struct drm_minor *minor = adev_to_drm(adev)->primary; 2025 struct dentry *root = minor->debugfs_root; 2026 2027 debugfs_create_file("amdgpu_firmware_info", 0444, root, 2028 adev, &amdgpu_debugfs_firmware_info_fops); 2029 2030 #endif 2031 } 2032