1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include "amdgpu.h" 30 #include <drm/amdgpu_drm.h> 31 #include "amdgpu_uvd.h" 32 #include "amdgpu_vce.h" 33 #include "atom.h" 34 35 #include <linux/vga_switcheroo.h> 36 #include <linux/slab.h> 37 #include <linux/uaccess.h> 38 #include <linux/pci.h> 39 #include <linux/pm_runtime.h> 40 #include "amdgpu_amdkfd.h" 41 #include "amdgpu_gem.h" 42 #include "amdgpu_display.h" 43 #include "amdgpu_ras.h" 44 45 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev) 46 { 47 struct amdgpu_gpu_instance *gpu_instance; 48 int i; 49 50 mutex_lock(&mgpu_info.mutex); 51 52 for (i = 0; i < mgpu_info.num_gpu; i++) { 53 gpu_instance = &(mgpu_info.gpu_ins[i]); 54 if (gpu_instance->adev == adev) { 55 mgpu_info.gpu_ins[i] = 56 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1]; 57 mgpu_info.num_gpu--; 58 if (adev->flags & AMD_IS_APU) 59 mgpu_info.num_apu--; 60 else 61 mgpu_info.num_dgpu--; 62 break; 63 } 64 } 65 66 mutex_unlock(&mgpu_info.mutex); 67 } 68 69 /** 70 * amdgpu_driver_unload_kms - Main unload function for KMS. 71 * 72 * @dev: drm dev pointer 73 * 74 * This is the main unload function for KMS (all asics). 75 * Returns 0 on success. 76 */ 77 void amdgpu_driver_unload_kms(struct drm_device *dev) 78 { 79 struct amdgpu_device *adev = drm_to_adev(dev); 80 81 if (adev == NULL) 82 return; 83 84 amdgpu_unregister_gpu_instance(adev); 85 86 if (adev->rmmio == NULL) 87 return; 88 89 if (adev->runpm) { 90 pm_runtime_get_sync(dev->dev); 91 pm_runtime_forbid(dev->dev); 92 } 93 94 amdgpu_acpi_fini(adev); 95 amdgpu_device_fini(adev); 96 } 97 98 void amdgpu_register_gpu_instance(struct amdgpu_device *adev) 99 { 100 struct amdgpu_gpu_instance *gpu_instance; 101 102 mutex_lock(&mgpu_info.mutex); 103 104 if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) { 105 DRM_ERROR("Cannot register more gpu instance\n"); 106 mutex_unlock(&mgpu_info.mutex); 107 return; 108 } 109 110 gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]); 111 gpu_instance->adev = adev; 112 gpu_instance->mgpu_fan_enabled = 0; 113 114 mgpu_info.num_gpu++; 115 if (adev->flags & AMD_IS_APU) 116 mgpu_info.num_apu++; 117 else 118 mgpu_info.num_dgpu++; 119 120 mutex_unlock(&mgpu_info.mutex); 121 } 122 123 /** 124 * amdgpu_driver_load_kms - Main load function for KMS. 125 * 126 * @adev: pointer to struct amdgpu_device 127 * @flags: device flags 128 * 129 * This is the main load function for KMS (all asics). 130 * Returns 0 on success, error on failure. 131 */ 132 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags) 133 { 134 struct drm_device *dev; 135 struct pci_dev *parent; 136 int r, acpi_status; 137 138 dev = adev_to_drm(adev); 139 140 if (amdgpu_has_atpx() && 141 (amdgpu_is_atpx_hybrid() || 142 amdgpu_has_atpx_dgpu_power_cntl()) && 143 ((flags & AMD_IS_APU) == 0) && 144 !pci_is_thunderbolt_attached(to_pci_dev(dev->dev))) 145 flags |= AMD_IS_PX; 146 147 parent = pci_upstream_bridge(adev->pdev); 148 adev->has_pr3 = parent ? pci_pr3_present(parent) : false; 149 150 /* amdgpu_device_init should report only fatal error 151 * like memory allocation failure or iomapping failure, 152 * or memory manager initialization failure, it must 153 * properly initialize the GPU MC controller and permit 154 * VRAM allocation 155 */ 156 r = amdgpu_device_init(adev, flags); 157 if (r) { 158 dev_err(dev->dev, "Fatal error during GPU init\n"); 159 goto out; 160 } 161 162 if (amdgpu_device_supports_atpx(dev) && 163 (amdgpu_runtime_pm != 0)) { /* enable runpm by default for atpx */ 164 adev->runpm = true; 165 dev_info(adev->dev, "Using ATPX for runtime pm\n"); 166 } else if (amdgpu_device_supports_boco(dev) && 167 (amdgpu_runtime_pm != 0)) { /* enable runpm by default for boco */ 168 adev->runpm = true; 169 dev_info(adev->dev, "Using BOCO for runtime pm\n"); 170 } else if (amdgpu_device_supports_baco(dev) && 171 (amdgpu_runtime_pm != 0)) { 172 switch (adev->asic_type) { 173 case CHIP_VEGA20: 174 case CHIP_ARCTURUS: 175 case CHIP_SIENNA_CICHLID: 176 case CHIP_NAVY_FLOUNDER: 177 /* enable runpm if runpm=1 */ 178 if (amdgpu_runtime_pm > 0) 179 adev->runpm = true; 180 break; 181 case CHIP_VEGA10: 182 /* turn runpm on if noretry=0 */ 183 if (!adev->gmc.noretry) 184 adev->runpm = true; 185 break; 186 default: 187 /* enable runpm on CI+ */ 188 adev->runpm = true; 189 break; 190 } 191 if (adev->runpm) 192 dev_info(adev->dev, "Using BACO for runtime pm\n"); 193 } 194 195 /* Call ACPI methods: require modeset init 196 * but failure is not fatal 197 */ 198 199 acpi_status = amdgpu_acpi_init(adev); 200 if (acpi_status) 201 dev_dbg(dev->dev, "Error during ACPI methods call\n"); 202 203 if (adev->runpm) { 204 /* only need to skip on ATPX */ 205 if (amdgpu_device_supports_atpx(dev) && 206 !amdgpu_is_atpx_hybrid()) 207 dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 208 pm_runtime_use_autosuspend(dev->dev); 209 pm_runtime_set_autosuspend_delay(dev->dev, 5000); 210 pm_runtime_allow(dev->dev); 211 pm_runtime_mark_last_busy(dev->dev); 212 pm_runtime_put_autosuspend(dev->dev); 213 } 214 215 out: 216 if (r) { 217 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */ 218 if (adev->rmmio && adev->runpm) 219 pm_runtime_put_noidle(dev->dev); 220 amdgpu_driver_unload_kms(dev); 221 } 222 223 return r; 224 } 225 226 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, 227 struct drm_amdgpu_query_fw *query_fw, 228 struct amdgpu_device *adev) 229 { 230 switch (query_fw->fw_type) { 231 case AMDGPU_INFO_FW_VCE: 232 fw_info->ver = adev->vce.fw_version; 233 fw_info->feature = adev->vce.fb_version; 234 break; 235 case AMDGPU_INFO_FW_UVD: 236 fw_info->ver = adev->uvd.fw_version; 237 fw_info->feature = 0; 238 break; 239 case AMDGPU_INFO_FW_VCN: 240 fw_info->ver = adev->vcn.fw_version; 241 fw_info->feature = 0; 242 break; 243 case AMDGPU_INFO_FW_GMC: 244 fw_info->ver = adev->gmc.fw_version; 245 fw_info->feature = 0; 246 break; 247 case AMDGPU_INFO_FW_GFX_ME: 248 fw_info->ver = adev->gfx.me_fw_version; 249 fw_info->feature = adev->gfx.me_feature_version; 250 break; 251 case AMDGPU_INFO_FW_GFX_PFP: 252 fw_info->ver = adev->gfx.pfp_fw_version; 253 fw_info->feature = adev->gfx.pfp_feature_version; 254 break; 255 case AMDGPU_INFO_FW_GFX_CE: 256 fw_info->ver = adev->gfx.ce_fw_version; 257 fw_info->feature = adev->gfx.ce_feature_version; 258 break; 259 case AMDGPU_INFO_FW_GFX_RLC: 260 fw_info->ver = adev->gfx.rlc_fw_version; 261 fw_info->feature = adev->gfx.rlc_feature_version; 262 break; 263 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL: 264 fw_info->ver = adev->gfx.rlc_srlc_fw_version; 265 fw_info->feature = adev->gfx.rlc_srlc_feature_version; 266 break; 267 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM: 268 fw_info->ver = adev->gfx.rlc_srlg_fw_version; 269 fw_info->feature = adev->gfx.rlc_srlg_feature_version; 270 break; 271 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM: 272 fw_info->ver = adev->gfx.rlc_srls_fw_version; 273 fw_info->feature = adev->gfx.rlc_srls_feature_version; 274 break; 275 case AMDGPU_INFO_FW_GFX_MEC: 276 if (query_fw->index == 0) { 277 fw_info->ver = adev->gfx.mec_fw_version; 278 fw_info->feature = adev->gfx.mec_feature_version; 279 } else if (query_fw->index == 1) { 280 fw_info->ver = adev->gfx.mec2_fw_version; 281 fw_info->feature = adev->gfx.mec2_feature_version; 282 } else 283 return -EINVAL; 284 break; 285 case AMDGPU_INFO_FW_SMC: 286 fw_info->ver = adev->pm.fw_version; 287 fw_info->feature = 0; 288 break; 289 case AMDGPU_INFO_FW_TA: 290 switch (query_fw->index) { 291 case 0: 292 fw_info->ver = adev->psp.ta_fw_version; 293 fw_info->feature = adev->psp.ta_xgmi_ucode_version; 294 break; 295 case 1: 296 fw_info->ver = adev->psp.ta_fw_version; 297 fw_info->feature = adev->psp.ta_ras_ucode_version; 298 break; 299 case 2: 300 fw_info->ver = adev->psp.ta_fw_version; 301 fw_info->feature = adev->psp.ta_hdcp_ucode_version; 302 break; 303 case 3: 304 fw_info->ver = adev->psp.ta_fw_version; 305 fw_info->feature = adev->psp.ta_dtm_ucode_version; 306 break; 307 case 4: 308 fw_info->ver = adev->psp.ta_fw_version; 309 fw_info->feature = adev->psp.ta_rap_ucode_version; 310 break; 311 default: 312 return -EINVAL; 313 } 314 break; 315 case AMDGPU_INFO_FW_SDMA: 316 if (query_fw->index >= adev->sdma.num_instances) 317 return -EINVAL; 318 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version; 319 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version; 320 break; 321 case AMDGPU_INFO_FW_SOS: 322 fw_info->ver = adev->psp.sos_fw_version; 323 fw_info->feature = adev->psp.sos_feature_version; 324 break; 325 case AMDGPU_INFO_FW_ASD: 326 fw_info->ver = adev->psp.asd_fw_version; 327 fw_info->feature = adev->psp.asd_feature_version; 328 break; 329 case AMDGPU_INFO_FW_DMCU: 330 fw_info->ver = adev->dm.dmcu_fw_version; 331 fw_info->feature = 0; 332 break; 333 case AMDGPU_INFO_FW_DMCUB: 334 fw_info->ver = adev->dm.dmcub_fw_version; 335 fw_info->feature = 0; 336 break; 337 case AMDGPU_INFO_FW_TOC: 338 fw_info->ver = adev->psp.toc_fw_version; 339 fw_info->feature = adev->psp.toc_feature_version; 340 break; 341 default: 342 return -EINVAL; 343 } 344 return 0; 345 } 346 347 static int amdgpu_hw_ip_info(struct amdgpu_device *adev, 348 struct drm_amdgpu_info *info, 349 struct drm_amdgpu_info_hw_ip *result) 350 { 351 uint32_t ib_start_alignment = 0; 352 uint32_t ib_size_alignment = 0; 353 enum amd_ip_block_type type; 354 unsigned int num_rings = 0; 355 unsigned int i, j; 356 357 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 358 return -EINVAL; 359 360 switch (info->query_hw_ip.type) { 361 case AMDGPU_HW_IP_GFX: 362 type = AMD_IP_BLOCK_TYPE_GFX; 363 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 364 if (adev->gfx.gfx_ring[i].sched.ready) 365 ++num_rings; 366 ib_start_alignment = 32; 367 ib_size_alignment = 32; 368 break; 369 case AMDGPU_HW_IP_COMPUTE: 370 type = AMD_IP_BLOCK_TYPE_GFX; 371 for (i = 0; i < adev->gfx.num_compute_rings; i++) 372 if (adev->gfx.compute_ring[i].sched.ready) 373 ++num_rings; 374 ib_start_alignment = 32; 375 ib_size_alignment = 32; 376 break; 377 case AMDGPU_HW_IP_DMA: 378 type = AMD_IP_BLOCK_TYPE_SDMA; 379 for (i = 0; i < adev->sdma.num_instances; i++) 380 if (adev->sdma.instance[i].ring.sched.ready) 381 ++num_rings; 382 ib_start_alignment = 256; 383 ib_size_alignment = 4; 384 break; 385 case AMDGPU_HW_IP_UVD: 386 type = AMD_IP_BLOCK_TYPE_UVD; 387 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 388 if (adev->uvd.harvest_config & (1 << i)) 389 continue; 390 391 if (adev->uvd.inst[i].ring.sched.ready) 392 ++num_rings; 393 } 394 ib_start_alignment = 64; 395 ib_size_alignment = 64; 396 break; 397 case AMDGPU_HW_IP_VCE: 398 type = AMD_IP_BLOCK_TYPE_VCE; 399 for (i = 0; i < adev->vce.num_rings; i++) 400 if (adev->vce.ring[i].sched.ready) 401 ++num_rings; 402 ib_start_alignment = 4; 403 ib_size_alignment = 1; 404 break; 405 case AMDGPU_HW_IP_UVD_ENC: 406 type = AMD_IP_BLOCK_TYPE_UVD; 407 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 408 if (adev->uvd.harvest_config & (1 << i)) 409 continue; 410 411 for (j = 0; j < adev->uvd.num_enc_rings; j++) 412 if (adev->uvd.inst[i].ring_enc[j].sched.ready) 413 ++num_rings; 414 } 415 ib_start_alignment = 64; 416 ib_size_alignment = 64; 417 break; 418 case AMDGPU_HW_IP_VCN_DEC: 419 type = AMD_IP_BLOCK_TYPE_VCN; 420 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 421 if (adev->uvd.harvest_config & (1 << i)) 422 continue; 423 424 if (adev->vcn.inst[i].ring_dec.sched.ready) 425 ++num_rings; 426 } 427 ib_start_alignment = 16; 428 ib_size_alignment = 16; 429 break; 430 case AMDGPU_HW_IP_VCN_ENC: 431 type = AMD_IP_BLOCK_TYPE_VCN; 432 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 433 if (adev->uvd.harvest_config & (1 << i)) 434 continue; 435 436 for (j = 0; j < adev->vcn.num_enc_rings; j++) 437 if (adev->vcn.inst[i].ring_enc[j].sched.ready) 438 ++num_rings; 439 } 440 ib_start_alignment = 64; 441 ib_size_alignment = 1; 442 break; 443 case AMDGPU_HW_IP_VCN_JPEG: 444 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 445 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 446 447 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { 448 if (adev->jpeg.harvest_config & (1 << i)) 449 continue; 450 451 if (adev->jpeg.inst[i].ring_dec.sched.ready) 452 ++num_rings; 453 } 454 ib_start_alignment = 16; 455 ib_size_alignment = 16; 456 break; 457 default: 458 return -EINVAL; 459 } 460 461 for (i = 0; i < adev->num_ip_blocks; i++) 462 if (adev->ip_blocks[i].version->type == type && 463 adev->ip_blocks[i].status.valid) 464 break; 465 466 if (i == adev->num_ip_blocks) 467 return 0; 468 469 num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type], 470 num_rings); 471 472 result->hw_ip_version_major = adev->ip_blocks[i].version->major; 473 result->hw_ip_version_minor = adev->ip_blocks[i].version->minor; 474 result->capabilities_flags = 0; 475 result->available_rings = (1 << num_rings) - 1; 476 result->ib_start_alignment = ib_start_alignment; 477 result->ib_size_alignment = ib_size_alignment; 478 return 0; 479 } 480 481 /* 482 * Userspace get information ioctl 483 */ 484 /** 485 * amdgpu_info_ioctl - answer a device specific request. 486 * 487 * @dev: drm device pointer 488 * @data: request object 489 * @filp: drm filp 490 * 491 * This function is used to pass device specific parameters to the userspace 492 * drivers. Examples include: pci device id, pipeline parms, tiling params, 493 * etc. (all asics). 494 * Returns 0 on success, -EINVAL on failure. 495 */ 496 int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 497 { 498 struct amdgpu_device *adev = drm_to_adev(dev); 499 struct drm_amdgpu_info *info = data; 500 struct amdgpu_mode_info *minfo = &adev->mode_info; 501 void __user *out = (void __user *)(uintptr_t)info->return_pointer; 502 uint32_t size = info->return_size; 503 struct drm_crtc *crtc; 504 uint32_t ui32 = 0; 505 uint64_t ui64 = 0; 506 int i, found; 507 int ui32_size = sizeof(ui32); 508 509 if (!info->return_size || !info->return_pointer) 510 return -EINVAL; 511 512 switch (info->query) { 513 case AMDGPU_INFO_ACCEL_WORKING: 514 ui32 = adev->accel_working; 515 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 516 case AMDGPU_INFO_CRTC_FROM_ID: 517 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { 518 crtc = (struct drm_crtc *)minfo->crtcs[i]; 519 if (crtc && crtc->base.id == info->mode_crtc.id) { 520 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 521 ui32 = amdgpu_crtc->crtc_id; 522 found = 1; 523 break; 524 } 525 } 526 if (!found) { 527 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); 528 return -EINVAL; 529 } 530 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 531 case AMDGPU_INFO_HW_IP_INFO: { 532 struct drm_amdgpu_info_hw_ip ip = {}; 533 int ret; 534 535 ret = amdgpu_hw_ip_info(adev, info, &ip); 536 if (ret) 537 return ret; 538 539 ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip))); 540 return ret ? -EFAULT : 0; 541 } 542 case AMDGPU_INFO_HW_IP_COUNT: { 543 enum amd_ip_block_type type; 544 uint32_t count = 0; 545 546 switch (info->query_hw_ip.type) { 547 case AMDGPU_HW_IP_GFX: 548 type = AMD_IP_BLOCK_TYPE_GFX; 549 break; 550 case AMDGPU_HW_IP_COMPUTE: 551 type = AMD_IP_BLOCK_TYPE_GFX; 552 break; 553 case AMDGPU_HW_IP_DMA: 554 type = AMD_IP_BLOCK_TYPE_SDMA; 555 break; 556 case AMDGPU_HW_IP_UVD: 557 type = AMD_IP_BLOCK_TYPE_UVD; 558 break; 559 case AMDGPU_HW_IP_VCE: 560 type = AMD_IP_BLOCK_TYPE_VCE; 561 break; 562 case AMDGPU_HW_IP_UVD_ENC: 563 type = AMD_IP_BLOCK_TYPE_UVD; 564 break; 565 case AMDGPU_HW_IP_VCN_DEC: 566 case AMDGPU_HW_IP_VCN_ENC: 567 type = AMD_IP_BLOCK_TYPE_VCN; 568 break; 569 case AMDGPU_HW_IP_VCN_JPEG: 570 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 571 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 572 break; 573 default: 574 return -EINVAL; 575 } 576 577 for (i = 0; i < adev->num_ip_blocks; i++) 578 if (adev->ip_blocks[i].version->type == type && 579 adev->ip_blocks[i].status.valid && 580 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 581 count++; 582 583 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; 584 } 585 case AMDGPU_INFO_TIMESTAMP: 586 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev); 587 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 588 case AMDGPU_INFO_FW_VERSION: { 589 struct drm_amdgpu_info_firmware fw_info; 590 int ret; 591 592 /* We only support one instance of each IP block right now. */ 593 if (info->query_fw.ip_instance != 0) 594 return -EINVAL; 595 596 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev); 597 if (ret) 598 return ret; 599 600 return copy_to_user(out, &fw_info, 601 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0; 602 } 603 case AMDGPU_INFO_NUM_BYTES_MOVED: 604 ui64 = atomic64_read(&adev->num_bytes_moved); 605 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 606 case AMDGPU_INFO_NUM_EVICTIONS: 607 ui64 = atomic64_read(&adev->num_evictions); 608 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 609 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS: 610 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults); 611 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 612 case AMDGPU_INFO_VRAM_USAGE: 613 ui64 = amdgpu_vram_mgr_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM)); 614 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 615 case AMDGPU_INFO_VIS_VRAM_USAGE: 616 ui64 = amdgpu_vram_mgr_vis_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM)); 617 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 618 case AMDGPU_INFO_GTT_USAGE: 619 ui64 = amdgpu_gtt_mgr_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)); 620 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 621 case AMDGPU_INFO_GDS_CONFIG: { 622 struct drm_amdgpu_info_gds gds_info; 623 624 memset(&gds_info, 0, sizeof(gds_info)); 625 gds_info.compute_partition_size = adev->gds.gds_size; 626 gds_info.gds_total_size = adev->gds.gds_size; 627 gds_info.gws_per_compute_partition = adev->gds.gws_size; 628 gds_info.oa_per_compute_partition = adev->gds.oa_size; 629 return copy_to_user(out, &gds_info, 630 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0; 631 } 632 case AMDGPU_INFO_VRAM_GTT: { 633 struct drm_amdgpu_info_vram_gtt vram_gtt; 634 635 vram_gtt.vram_size = adev->gmc.real_vram_size - 636 atomic64_read(&adev->vram_pin_size) - 637 AMDGPU_VM_RESERVED_VRAM; 638 vram_gtt.vram_cpu_accessible_size = 639 min(adev->gmc.visible_vram_size - 640 atomic64_read(&adev->visible_pin_size), 641 vram_gtt.vram_size); 642 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size; 643 vram_gtt.gtt_size *= PAGE_SIZE; 644 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size); 645 return copy_to_user(out, &vram_gtt, 646 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; 647 } 648 case AMDGPU_INFO_MEMORY: { 649 struct drm_amdgpu_memory_info mem; 650 struct ttm_resource_manager *vram_man = 651 ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); 652 struct ttm_resource_manager *gtt_man = 653 ttm_manager_type(&adev->mman.bdev, TTM_PL_TT); 654 memset(&mem, 0, sizeof(mem)); 655 mem.vram.total_heap_size = adev->gmc.real_vram_size; 656 mem.vram.usable_heap_size = adev->gmc.real_vram_size - 657 atomic64_read(&adev->vram_pin_size) - 658 AMDGPU_VM_RESERVED_VRAM; 659 mem.vram.heap_usage = 660 amdgpu_vram_mgr_usage(vram_man); 661 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4; 662 663 mem.cpu_accessible_vram.total_heap_size = 664 adev->gmc.visible_vram_size; 665 mem.cpu_accessible_vram.usable_heap_size = 666 min(adev->gmc.visible_vram_size - 667 atomic64_read(&adev->visible_pin_size), 668 mem.vram.usable_heap_size); 669 mem.cpu_accessible_vram.heap_usage = 670 amdgpu_vram_mgr_vis_usage(vram_man); 671 mem.cpu_accessible_vram.max_allocation = 672 mem.cpu_accessible_vram.usable_heap_size * 3 / 4; 673 674 mem.gtt.total_heap_size = gtt_man->size; 675 mem.gtt.total_heap_size *= PAGE_SIZE; 676 mem.gtt.usable_heap_size = mem.gtt.total_heap_size - 677 atomic64_read(&adev->gart_pin_size); 678 mem.gtt.heap_usage = 679 amdgpu_gtt_mgr_usage(gtt_man); 680 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4; 681 682 return copy_to_user(out, &mem, 683 min((size_t)size, sizeof(mem))) 684 ? -EFAULT : 0; 685 } 686 case AMDGPU_INFO_READ_MMR_REG: { 687 unsigned n, alloc_size; 688 uint32_t *regs; 689 unsigned se_num = (info->read_mmr_reg.instance >> 690 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & 691 AMDGPU_INFO_MMR_SE_INDEX_MASK; 692 unsigned sh_num = (info->read_mmr_reg.instance >> 693 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & 694 AMDGPU_INFO_MMR_SH_INDEX_MASK; 695 696 /* set full masks if the userspace set all bits 697 * in the bitfields */ 698 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) 699 se_num = 0xffffffff; 700 else if (se_num >= AMDGPU_GFX_MAX_SE) 701 return -EINVAL; 702 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) 703 sh_num = 0xffffffff; 704 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE) 705 return -EINVAL; 706 707 if (info->read_mmr_reg.count > 128) 708 return -EINVAL; 709 710 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL); 711 if (!regs) 712 return -ENOMEM; 713 alloc_size = info->read_mmr_reg.count * sizeof(*regs); 714 715 amdgpu_gfx_off_ctrl(adev, false); 716 for (i = 0; i < info->read_mmr_reg.count; i++) { 717 if (amdgpu_asic_read_register(adev, se_num, sh_num, 718 info->read_mmr_reg.dword_offset + i, 719 ®s[i])) { 720 DRM_DEBUG_KMS("unallowed offset %#x\n", 721 info->read_mmr_reg.dword_offset + i); 722 kfree(regs); 723 amdgpu_gfx_off_ctrl(adev, true); 724 return -EFAULT; 725 } 726 } 727 amdgpu_gfx_off_ctrl(adev, true); 728 n = copy_to_user(out, regs, min(size, alloc_size)); 729 kfree(regs); 730 return n ? -EFAULT : 0; 731 } 732 case AMDGPU_INFO_DEV_INFO: { 733 struct drm_amdgpu_info_device *dev_info; 734 uint64_t vm_size; 735 int ret; 736 737 dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL); 738 if (!dev_info) 739 return -ENOMEM; 740 741 dev_info->device_id = adev->pdev->device; 742 dev_info->chip_rev = adev->rev_id; 743 dev_info->external_rev = adev->external_rev_id; 744 dev_info->pci_rev = adev->pdev->revision; 745 dev_info->family = adev->family; 746 dev_info->num_shader_engines = adev->gfx.config.max_shader_engines; 747 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 748 /* return all clocks in KHz */ 749 dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; 750 if (adev->pm.dpm_enabled) { 751 dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10; 752 dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10; 753 } else { 754 dev_info->max_engine_clock = adev->clock.default_sclk * 10; 755 dev_info->max_memory_clock = adev->clock.default_mclk * 10; 756 } 757 dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; 758 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se * 759 adev->gfx.config.max_shader_engines; 760 dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; 761 dev_info->_pad = 0; 762 dev_info->ids_flags = 0; 763 if (adev->flags & AMD_IS_APU) 764 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION; 765 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) 766 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION; 767 if (amdgpu_is_tmz(adev)) 768 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ; 769 770 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 771 vm_size -= AMDGPU_VA_RESERVED_SIZE; 772 773 /* Older VCE FW versions are buggy and can handle only 40bits */ 774 if (adev->vce.fw_version && 775 adev->vce.fw_version < AMDGPU_VCE_FW_53_45) 776 vm_size = min(vm_size, 1ULL << 40); 777 778 dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_SIZE; 779 dev_info->virtual_address_max = 780 min(vm_size, AMDGPU_GMC_HOLE_START); 781 782 if (vm_size > AMDGPU_GMC_HOLE_START) { 783 dev_info->high_va_offset = AMDGPU_GMC_HOLE_END; 784 dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size; 785 } 786 dev_info->virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 787 dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE; 788 dev_info->gart_page_size = AMDGPU_GPU_PAGE_SIZE; 789 dev_info->cu_active_number = adev->gfx.cu_info.number; 790 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; 791 dev_info->ce_ram_size = adev->gfx.ce_ram_size; 792 memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0], 793 sizeof(adev->gfx.cu_info.ao_cu_bitmap)); 794 memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], 795 sizeof(adev->gfx.cu_info.bitmap)); 796 dev_info->vram_type = adev->gmc.vram_type; 797 dev_info->vram_bit_width = adev->gmc.vram_width; 798 dev_info->vce_harvest_config = adev->vce.harvest_config; 799 dev_info->gc_double_offchip_lds_buf = 800 adev->gfx.config.double_offchip_lds_buf; 801 dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size; 802 dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs; 803 dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh; 804 dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches; 805 dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth; 806 dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth; 807 dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads; 808 809 if (adev->family >= AMDGPU_FAMILY_NV) 810 dev_info->pa_sc_tile_steering_override = 811 adev->gfx.config.pa_sc_tile_steering_override; 812 813 dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask; 814 815 ret = copy_to_user(out, dev_info, 816 min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0; 817 kfree(dev_info); 818 return ret; 819 } 820 case AMDGPU_INFO_VCE_CLOCK_TABLE: { 821 unsigned i; 822 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {}; 823 struct amd_vce_state *vce_state; 824 825 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) { 826 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i); 827 if (vce_state) { 828 vce_clk_table.entries[i].sclk = vce_state->sclk; 829 vce_clk_table.entries[i].mclk = vce_state->mclk; 830 vce_clk_table.entries[i].eclk = vce_state->evclk; 831 vce_clk_table.num_valid_entries++; 832 } 833 } 834 835 return copy_to_user(out, &vce_clk_table, 836 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0; 837 } 838 case AMDGPU_INFO_VBIOS: { 839 uint32_t bios_size = adev->bios_size; 840 841 switch (info->vbios_info.type) { 842 case AMDGPU_INFO_VBIOS_SIZE: 843 return copy_to_user(out, &bios_size, 844 min((size_t)size, sizeof(bios_size))) 845 ? -EFAULT : 0; 846 case AMDGPU_INFO_VBIOS_IMAGE: { 847 uint8_t *bios; 848 uint32_t bios_offset = info->vbios_info.offset; 849 850 if (bios_offset >= bios_size) 851 return -EINVAL; 852 853 bios = adev->bios + bios_offset; 854 return copy_to_user(out, bios, 855 min((size_t)size, (size_t)(bios_size - bios_offset))) 856 ? -EFAULT : 0; 857 } 858 default: 859 DRM_DEBUG_KMS("Invalid request %d\n", 860 info->vbios_info.type); 861 return -EINVAL; 862 } 863 } 864 case AMDGPU_INFO_NUM_HANDLES: { 865 struct drm_amdgpu_info_num_handles handle; 866 867 switch (info->query_hw_ip.type) { 868 case AMDGPU_HW_IP_UVD: 869 /* Starting Polaris, we support unlimited UVD handles */ 870 if (adev->asic_type < CHIP_POLARIS10) { 871 handle.uvd_max_handles = adev->uvd.max_handles; 872 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev); 873 874 return copy_to_user(out, &handle, 875 min((size_t)size, sizeof(handle))) ? -EFAULT : 0; 876 } else { 877 return -ENODATA; 878 } 879 880 break; 881 default: 882 return -EINVAL; 883 } 884 } 885 case AMDGPU_INFO_SENSOR: { 886 if (!adev->pm.dpm_enabled) 887 return -ENOENT; 888 889 switch (info->sensor_info.type) { 890 case AMDGPU_INFO_SENSOR_GFX_SCLK: 891 /* get sclk in Mhz */ 892 if (amdgpu_dpm_read_sensor(adev, 893 AMDGPU_PP_SENSOR_GFX_SCLK, 894 (void *)&ui32, &ui32_size)) { 895 return -EINVAL; 896 } 897 ui32 /= 100; 898 break; 899 case AMDGPU_INFO_SENSOR_GFX_MCLK: 900 /* get mclk in Mhz */ 901 if (amdgpu_dpm_read_sensor(adev, 902 AMDGPU_PP_SENSOR_GFX_MCLK, 903 (void *)&ui32, &ui32_size)) { 904 return -EINVAL; 905 } 906 ui32 /= 100; 907 break; 908 case AMDGPU_INFO_SENSOR_GPU_TEMP: 909 /* get temperature in millidegrees C */ 910 if (amdgpu_dpm_read_sensor(adev, 911 AMDGPU_PP_SENSOR_GPU_TEMP, 912 (void *)&ui32, &ui32_size)) { 913 return -EINVAL; 914 } 915 break; 916 case AMDGPU_INFO_SENSOR_GPU_LOAD: 917 /* get GPU load */ 918 if (amdgpu_dpm_read_sensor(adev, 919 AMDGPU_PP_SENSOR_GPU_LOAD, 920 (void *)&ui32, &ui32_size)) { 921 return -EINVAL; 922 } 923 break; 924 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER: 925 /* get average GPU power */ 926 if (amdgpu_dpm_read_sensor(adev, 927 AMDGPU_PP_SENSOR_GPU_POWER, 928 (void *)&ui32, &ui32_size)) { 929 return -EINVAL; 930 } 931 ui32 >>= 8; 932 break; 933 case AMDGPU_INFO_SENSOR_VDDNB: 934 /* get VDDNB in millivolts */ 935 if (amdgpu_dpm_read_sensor(adev, 936 AMDGPU_PP_SENSOR_VDDNB, 937 (void *)&ui32, &ui32_size)) { 938 return -EINVAL; 939 } 940 break; 941 case AMDGPU_INFO_SENSOR_VDDGFX: 942 /* get VDDGFX in millivolts */ 943 if (amdgpu_dpm_read_sensor(adev, 944 AMDGPU_PP_SENSOR_VDDGFX, 945 (void *)&ui32, &ui32_size)) { 946 return -EINVAL; 947 } 948 break; 949 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK: 950 /* get stable pstate sclk in Mhz */ 951 if (amdgpu_dpm_read_sensor(adev, 952 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 953 (void *)&ui32, &ui32_size)) { 954 return -EINVAL; 955 } 956 ui32 /= 100; 957 break; 958 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK: 959 /* get stable pstate mclk in Mhz */ 960 if (amdgpu_dpm_read_sensor(adev, 961 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 962 (void *)&ui32, &ui32_size)) { 963 return -EINVAL; 964 } 965 ui32 /= 100; 966 break; 967 default: 968 DRM_DEBUG_KMS("Invalid request %d\n", 969 info->sensor_info.type); 970 return -EINVAL; 971 } 972 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 973 } 974 case AMDGPU_INFO_VRAM_LOST_COUNTER: 975 ui32 = atomic_read(&adev->vram_lost_counter); 976 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 977 case AMDGPU_INFO_RAS_ENABLED_FEATURES: { 978 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 979 uint64_t ras_mask; 980 981 if (!ras) 982 return -EINVAL; 983 ras_mask = (uint64_t)ras->supported << 32 | ras->features; 984 985 return copy_to_user(out, &ras_mask, 986 min_t(u64, size, sizeof(ras_mask))) ? 987 -EFAULT : 0; 988 } 989 case AMDGPU_INFO_VIDEO_CAPS: { 990 const struct amdgpu_video_codecs *codecs; 991 struct drm_amdgpu_info_video_caps *caps; 992 int r; 993 994 switch (info->video_cap.type) { 995 case AMDGPU_INFO_VIDEO_CAPS_DECODE: 996 r = amdgpu_asic_query_video_codecs(adev, false, &codecs); 997 if (r) 998 return -EINVAL; 999 break; 1000 case AMDGPU_INFO_VIDEO_CAPS_ENCODE: 1001 r = amdgpu_asic_query_video_codecs(adev, true, &codecs); 1002 if (r) 1003 return -EINVAL; 1004 break; 1005 default: 1006 DRM_DEBUG_KMS("Invalid request %d\n", 1007 info->video_cap.type); 1008 return -EINVAL; 1009 } 1010 1011 caps = kzalloc(sizeof(*caps), GFP_KERNEL); 1012 if (!caps) 1013 return -ENOMEM; 1014 1015 for (i = 0; i < codecs->codec_count; i++) { 1016 int idx = codecs->codec_array[i].codec_type; 1017 1018 switch (idx) { 1019 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2: 1020 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4: 1021 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1: 1022 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC: 1023 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC: 1024 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG: 1025 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9: 1026 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1: 1027 caps->codec_info[idx].valid = 1; 1028 caps->codec_info[idx].max_width = 1029 codecs->codec_array[i].max_width; 1030 caps->codec_info[idx].max_height = 1031 codecs->codec_array[i].max_height; 1032 caps->codec_info[idx].max_pixels_per_frame = 1033 codecs->codec_array[i].max_pixels_per_frame; 1034 caps->codec_info[idx].max_level = 1035 codecs->codec_array[i].max_level; 1036 break; 1037 default: 1038 break; 1039 } 1040 } 1041 r = copy_to_user(out, caps, 1042 min((size_t)size, sizeof(*caps))) ? -EFAULT : 0; 1043 kfree(caps); 1044 return r; 1045 } 1046 default: 1047 DRM_DEBUG_KMS("Invalid request %d\n", info->query); 1048 return -EINVAL; 1049 } 1050 return 0; 1051 } 1052 1053 1054 /* 1055 * Outdated mess for old drm with Xorg being in charge (void function now). 1056 */ 1057 /** 1058 * amdgpu_driver_lastclose_kms - drm callback for last close 1059 * 1060 * @dev: drm dev pointer 1061 * 1062 * Switch vga_switcheroo state after last close (all asics). 1063 */ 1064 void amdgpu_driver_lastclose_kms(struct drm_device *dev) 1065 { 1066 drm_fb_helper_lastclose(dev); 1067 vga_switcheroo_process_delayed_switch(); 1068 } 1069 1070 /** 1071 * amdgpu_driver_open_kms - drm callback for open 1072 * 1073 * @dev: drm dev pointer 1074 * @file_priv: drm file 1075 * 1076 * On device open, init vm on cayman+ (all asics). 1077 * Returns 0 on success, error on failure. 1078 */ 1079 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 1080 { 1081 struct amdgpu_device *adev = drm_to_adev(dev); 1082 struct amdgpu_fpriv *fpriv; 1083 int r, pasid; 1084 1085 /* Ensure IB tests are run on ring */ 1086 flush_delayed_work(&adev->delayed_init_work); 1087 1088 1089 if (amdgpu_ras_intr_triggered()) { 1090 DRM_ERROR("RAS Intr triggered, device disabled!!"); 1091 return -EHWPOISON; 1092 } 1093 1094 file_priv->driver_priv = NULL; 1095 1096 r = pm_runtime_get_sync(dev->dev); 1097 if (r < 0) 1098 goto pm_put; 1099 1100 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 1101 if (unlikely(!fpriv)) { 1102 r = -ENOMEM; 1103 goto out_suspend; 1104 } 1105 1106 pasid = amdgpu_pasid_alloc(16); 1107 if (pasid < 0) { 1108 dev_warn(adev->dev, "No more PASIDs available!"); 1109 pasid = 0; 1110 } 1111 r = amdgpu_vm_init(adev, &fpriv->vm, AMDGPU_VM_CONTEXT_GFX, pasid); 1112 if (r) 1113 goto error_pasid; 1114 1115 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL); 1116 if (!fpriv->prt_va) { 1117 r = -ENOMEM; 1118 goto error_vm; 1119 } 1120 1121 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { 1122 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK; 1123 1124 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj, 1125 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE); 1126 if (r) 1127 goto error_vm; 1128 } 1129 1130 mutex_init(&fpriv->bo_list_lock); 1131 idr_init(&fpriv->bo_list_handles); 1132 1133 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr); 1134 1135 file_priv->driver_priv = fpriv; 1136 goto out_suspend; 1137 1138 error_vm: 1139 amdgpu_vm_fini(adev, &fpriv->vm); 1140 1141 error_pasid: 1142 if (pasid) 1143 amdgpu_pasid_free(pasid); 1144 1145 kfree(fpriv); 1146 1147 out_suspend: 1148 pm_runtime_mark_last_busy(dev->dev); 1149 pm_put: 1150 pm_runtime_put_autosuspend(dev->dev); 1151 1152 return r; 1153 } 1154 1155 /** 1156 * amdgpu_driver_postclose_kms - drm callback for post close 1157 * 1158 * @dev: drm dev pointer 1159 * @file_priv: drm file 1160 * 1161 * On device post close, tear down vm on cayman+ (all asics). 1162 */ 1163 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1164 struct drm_file *file_priv) 1165 { 1166 struct amdgpu_device *adev = drm_to_adev(dev); 1167 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1168 struct amdgpu_bo_list *list; 1169 struct amdgpu_bo *pd; 1170 u32 pasid; 1171 int handle; 1172 1173 if (!fpriv) 1174 return; 1175 1176 pm_runtime_get_sync(dev->dev); 1177 1178 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL) 1179 amdgpu_uvd_free_handles(adev, file_priv); 1180 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL) 1181 amdgpu_vce_free_handles(adev, file_priv); 1182 1183 amdgpu_vm_bo_rmv(adev, fpriv->prt_va); 1184 1185 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { 1186 /* TODO: how to handle reserve failure */ 1187 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true)); 1188 amdgpu_vm_bo_rmv(adev, fpriv->csa_va); 1189 fpriv->csa_va = NULL; 1190 amdgpu_bo_unreserve(adev->virt.csa_obj); 1191 } 1192 1193 pasid = fpriv->vm.pasid; 1194 pd = amdgpu_bo_ref(fpriv->vm.root.base.bo); 1195 1196 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); 1197 amdgpu_vm_fini(adev, &fpriv->vm); 1198 1199 if (pasid) 1200 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid); 1201 amdgpu_bo_unref(&pd); 1202 1203 idr_for_each_entry(&fpriv->bo_list_handles, list, handle) 1204 amdgpu_bo_list_put(list); 1205 1206 idr_destroy(&fpriv->bo_list_handles); 1207 mutex_destroy(&fpriv->bo_list_lock); 1208 1209 kfree(fpriv); 1210 file_priv->driver_priv = NULL; 1211 1212 pm_runtime_mark_last_busy(dev->dev); 1213 pm_runtime_put_autosuspend(dev->dev); 1214 } 1215 1216 /* 1217 * VBlank related functions. 1218 */ 1219 /** 1220 * amdgpu_get_vblank_counter_kms - get frame count 1221 * 1222 * @crtc: crtc to get the frame count from 1223 * 1224 * Gets the frame count on the requested crtc (all asics). 1225 * Returns frame count on success, -EINVAL on failure. 1226 */ 1227 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc) 1228 { 1229 struct drm_device *dev = crtc->dev; 1230 unsigned int pipe = crtc->index; 1231 struct amdgpu_device *adev = drm_to_adev(dev); 1232 int vpos, hpos, stat; 1233 u32 count; 1234 1235 if (pipe >= adev->mode_info.num_crtc) { 1236 DRM_ERROR("Invalid crtc %u\n", pipe); 1237 return -EINVAL; 1238 } 1239 1240 /* The hw increments its frame counter at start of vsync, not at start 1241 * of vblank, as is required by DRM core vblank counter handling. 1242 * Cook the hw count here to make it appear to the caller as if it 1243 * incremented at start of vblank. We measure distance to start of 1244 * vblank in vpos. vpos therefore will be >= 0 between start of vblank 1245 * and start of vsync, so vpos >= 0 means to bump the hw frame counter 1246 * result by 1 to give the proper appearance to caller. 1247 */ 1248 if (adev->mode_info.crtcs[pipe]) { 1249 /* Repeat readout if needed to provide stable result if 1250 * we cross start of vsync during the queries. 1251 */ 1252 do { 1253 count = amdgpu_display_vblank_get_counter(adev, pipe); 1254 /* Ask amdgpu_display_get_crtc_scanoutpos to return 1255 * vpos as distance to start of vblank, instead of 1256 * regular vertical scanout pos. 1257 */ 1258 stat = amdgpu_display_get_crtc_scanoutpos( 1259 dev, pipe, GET_DISTANCE_TO_VBLANKSTART, 1260 &vpos, &hpos, NULL, NULL, 1261 &adev->mode_info.crtcs[pipe]->base.hwmode); 1262 } while (count != amdgpu_display_vblank_get_counter(adev, pipe)); 1263 1264 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 1265 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 1266 DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 1267 } else { 1268 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", 1269 pipe, vpos); 1270 1271 /* Bump counter if we are at >= leading edge of vblank, 1272 * but before vsync where vpos would turn negative and 1273 * the hw counter really increments. 1274 */ 1275 if (vpos >= 0) 1276 count++; 1277 } 1278 } else { 1279 /* Fallback to use value as is. */ 1280 count = amdgpu_display_vblank_get_counter(adev, pipe); 1281 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 1282 } 1283 1284 return count; 1285 } 1286 1287 /** 1288 * amdgpu_enable_vblank_kms - enable vblank interrupt 1289 * 1290 * @crtc: crtc to enable vblank interrupt for 1291 * 1292 * Enable the interrupt on the requested crtc (all asics). 1293 * Returns 0 on success, -EINVAL on failure. 1294 */ 1295 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc) 1296 { 1297 struct drm_device *dev = crtc->dev; 1298 unsigned int pipe = crtc->index; 1299 struct amdgpu_device *adev = drm_to_adev(dev); 1300 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1301 1302 return amdgpu_irq_get(adev, &adev->crtc_irq, idx); 1303 } 1304 1305 /** 1306 * amdgpu_disable_vblank_kms - disable vblank interrupt 1307 * 1308 * @crtc: crtc to disable vblank interrupt for 1309 * 1310 * Disable the interrupt on the requested crtc (all asics). 1311 */ 1312 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc) 1313 { 1314 struct drm_device *dev = crtc->dev; 1315 unsigned int pipe = crtc->index; 1316 struct amdgpu_device *adev = drm_to_adev(dev); 1317 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1318 1319 amdgpu_irq_put(adev, &adev->crtc_irq, idx); 1320 } 1321 1322 /* 1323 * Debugfs info 1324 */ 1325 #if defined(CONFIG_DEBUG_FS) 1326 1327 static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused) 1328 { 1329 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 1330 struct drm_amdgpu_info_firmware fw_info; 1331 struct drm_amdgpu_query_fw query_fw; 1332 struct atom_context *ctx = adev->mode_info.atom_context; 1333 int ret, i; 1334 1335 /* VCE */ 1336 query_fw.fw_type = AMDGPU_INFO_FW_VCE; 1337 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1338 if (ret) 1339 return ret; 1340 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n", 1341 fw_info.feature, fw_info.ver); 1342 1343 /* UVD */ 1344 query_fw.fw_type = AMDGPU_INFO_FW_UVD; 1345 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1346 if (ret) 1347 return ret; 1348 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n", 1349 fw_info.feature, fw_info.ver); 1350 1351 /* GMC */ 1352 query_fw.fw_type = AMDGPU_INFO_FW_GMC; 1353 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1354 if (ret) 1355 return ret; 1356 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n", 1357 fw_info.feature, fw_info.ver); 1358 1359 /* ME */ 1360 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME; 1361 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1362 if (ret) 1363 return ret; 1364 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n", 1365 fw_info.feature, fw_info.ver); 1366 1367 /* PFP */ 1368 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP; 1369 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1370 if (ret) 1371 return ret; 1372 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n", 1373 fw_info.feature, fw_info.ver); 1374 1375 /* CE */ 1376 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE; 1377 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1378 if (ret) 1379 return ret; 1380 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n", 1381 fw_info.feature, fw_info.ver); 1382 1383 /* RLC */ 1384 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC; 1385 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1386 if (ret) 1387 return ret; 1388 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n", 1389 fw_info.feature, fw_info.ver); 1390 1391 /* RLC SAVE RESTORE LIST CNTL */ 1392 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL; 1393 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1394 if (ret) 1395 return ret; 1396 seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n", 1397 fw_info.feature, fw_info.ver); 1398 1399 /* RLC SAVE RESTORE LIST GPM MEM */ 1400 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM; 1401 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1402 if (ret) 1403 return ret; 1404 seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n", 1405 fw_info.feature, fw_info.ver); 1406 1407 /* RLC SAVE RESTORE LIST SRM MEM */ 1408 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM; 1409 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1410 if (ret) 1411 return ret; 1412 seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n", 1413 fw_info.feature, fw_info.ver); 1414 1415 /* MEC */ 1416 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC; 1417 query_fw.index = 0; 1418 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1419 if (ret) 1420 return ret; 1421 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n", 1422 fw_info.feature, fw_info.ver); 1423 1424 /* MEC2 */ 1425 if (adev->gfx.mec2_fw) { 1426 query_fw.index = 1; 1427 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1428 if (ret) 1429 return ret; 1430 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n", 1431 fw_info.feature, fw_info.ver); 1432 } 1433 1434 /* PSP SOS */ 1435 query_fw.fw_type = AMDGPU_INFO_FW_SOS; 1436 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1437 if (ret) 1438 return ret; 1439 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n", 1440 fw_info.feature, fw_info.ver); 1441 1442 1443 /* PSP ASD */ 1444 query_fw.fw_type = AMDGPU_INFO_FW_ASD; 1445 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1446 if (ret) 1447 return ret; 1448 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n", 1449 fw_info.feature, fw_info.ver); 1450 1451 query_fw.fw_type = AMDGPU_INFO_FW_TA; 1452 for (i = 0; i < 5; i++) { 1453 query_fw.index = i; 1454 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1455 if (ret) 1456 continue; 1457 switch (query_fw.index) { 1458 case 0: 1459 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n", 1460 "RAS", fw_info.feature, fw_info.ver); 1461 break; 1462 case 1: 1463 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n", 1464 "XGMI", fw_info.feature, fw_info.ver); 1465 break; 1466 case 2: 1467 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n", 1468 "HDCP", fw_info.feature, fw_info.ver); 1469 break; 1470 case 3: 1471 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n", 1472 "DTM", fw_info.feature, fw_info.ver); 1473 break; 1474 case 4: 1475 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n", 1476 "RAP", fw_info.feature, fw_info.ver); 1477 break; 1478 default: 1479 return -EINVAL; 1480 } 1481 } 1482 1483 /* SMC */ 1484 query_fw.fw_type = AMDGPU_INFO_FW_SMC; 1485 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1486 if (ret) 1487 return ret; 1488 seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n", 1489 fw_info.feature, fw_info.ver); 1490 1491 /* SDMA */ 1492 query_fw.fw_type = AMDGPU_INFO_FW_SDMA; 1493 for (i = 0; i < adev->sdma.num_instances; i++) { 1494 query_fw.index = i; 1495 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1496 if (ret) 1497 return ret; 1498 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n", 1499 i, fw_info.feature, fw_info.ver); 1500 } 1501 1502 /* VCN */ 1503 query_fw.fw_type = AMDGPU_INFO_FW_VCN; 1504 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1505 if (ret) 1506 return ret; 1507 seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n", 1508 fw_info.feature, fw_info.ver); 1509 1510 /* DMCU */ 1511 query_fw.fw_type = AMDGPU_INFO_FW_DMCU; 1512 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1513 if (ret) 1514 return ret; 1515 seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n", 1516 fw_info.feature, fw_info.ver); 1517 1518 /* DMCUB */ 1519 query_fw.fw_type = AMDGPU_INFO_FW_DMCUB; 1520 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1521 if (ret) 1522 return ret; 1523 seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n", 1524 fw_info.feature, fw_info.ver); 1525 1526 /* TOC */ 1527 query_fw.fw_type = AMDGPU_INFO_FW_TOC; 1528 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1529 if (ret) 1530 return ret; 1531 seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n", 1532 fw_info.feature, fw_info.ver); 1533 1534 seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version); 1535 1536 return 0; 1537 } 1538 1539 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_firmware_info); 1540 1541 #endif 1542 1543 void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev) 1544 { 1545 #if defined(CONFIG_DEBUG_FS) 1546 struct drm_minor *minor = adev_to_drm(adev)->primary; 1547 struct dentry *root = minor->debugfs_root; 1548 1549 debugfs_create_file("amdgpu_firmware_info", 0444, root, 1550 adev, &amdgpu_debugfs_firmware_info_fops); 1551 1552 #endif 1553 } 1554