1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include "amdgpu.h" 30 #include <drm/amdgpu_drm.h> 31 #include <drm/drm_drv.h> 32 #include <drm/drm_fb_helper.h> 33 #include "amdgpu_uvd.h" 34 #include "amdgpu_vce.h" 35 #include "atom.h" 36 37 #include <linux/vga_switcheroo.h> 38 #include <linux/slab.h> 39 #include <linux/uaccess.h> 40 #include <linux/pci.h> 41 #include <linux/pm_runtime.h> 42 #include "amdgpu_amdkfd.h" 43 #include "amdgpu_gem.h" 44 #include "amdgpu_display.h" 45 #include "amdgpu_ras.h" 46 #include "amd_pcie.h" 47 48 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev) 49 { 50 struct amdgpu_gpu_instance *gpu_instance; 51 int i; 52 53 mutex_lock(&mgpu_info.mutex); 54 55 for (i = 0; i < mgpu_info.num_gpu; i++) { 56 gpu_instance = &(mgpu_info.gpu_ins[i]); 57 if (gpu_instance->adev == adev) { 58 mgpu_info.gpu_ins[i] = 59 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1]; 60 mgpu_info.num_gpu--; 61 if (adev->flags & AMD_IS_APU) 62 mgpu_info.num_apu--; 63 else 64 mgpu_info.num_dgpu--; 65 break; 66 } 67 } 68 69 mutex_unlock(&mgpu_info.mutex); 70 } 71 72 /** 73 * amdgpu_driver_unload_kms - Main unload function for KMS. 74 * 75 * @dev: drm dev pointer 76 * 77 * This is the main unload function for KMS (all asics). 78 * Returns 0 on success. 79 */ 80 void amdgpu_driver_unload_kms(struct drm_device *dev) 81 { 82 struct amdgpu_device *adev = drm_to_adev(dev); 83 84 if (adev == NULL) 85 return; 86 87 amdgpu_unregister_gpu_instance(adev); 88 89 if (adev->rmmio == NULL) 90 return; 91 92 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_UNLOAD)) 93 DRM_WARN("smart shift update failed\n"); 94 95 amdgpu_acpi_fini(adev); 96 amdgpu_device_fini_hw(adev); 97 } 98 99 void amdgpu_register_gpu_instance(struct amdgpu_device *adev) 100 { 101 struct amdgpu_gpu_instance *gpu_instance; 102 103 mutex_lock(&mgpu_info.mutex); 104 105 if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) { 106 DRM_ERROR("Cannot register more gpu instance\n"); 107 mutex_unlock(&mgpu_info.mutex); 108 return; 109 } 110 111 gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]); 112 gpu_instance->adev = adev; 113 gpu_instance->mgpu_fan_enabled = 0; 114 115 mgpu_info.num_gpu++; 116 if (adev->flags & AMD_IS_APU) 117 mgpu_info.num_apu++; 118 else 119 mgpu_info.num_dgpu++; 120 121 mutex_unlock(&mgpu_info.mutex); 122 } 123 124 /** 125 * amdgpu_driver_load_kms - Main load function for KMS. 126 * 127 * @adev: pointer to struct amdgpu_device 128 * @flags: device flags 129 * 130 * This is the main load function for KMS (all asics). 131 * Returns 0 on success, error on failure. 132 */ 133 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags) 134 { 135 struct drm_device *dev; 136 int r, acpi_status; 137 138 dev = adev_to_drm(adev); 139 140 /* amdgpu_device_init should report only fatal error 141 * like memory allocation failure or iomapping failure, 142 * or memory manager initialization failure, it must 143 * properly initialize the GPU MC controller and permit 144 * VRAM allocation 145 */ 146 r = amdgpu_device_init(adev, flags); 147 if (r) { 148 dev_err(dev->dev, "Fatal error during GPU init\n"); 149 goto out; 150 } 151 152 adev->pm.rpm_mode = AMDGPU_RUNPM_NONE; 153 if (amdgpu_device_supports_px(dev) && 154 (amdgpu_runtime_pm != 0)) { /* enable PX as runtime mode */ 155 adev->pm.rpm_mode = AMDGPU_RUNPM_PX; 156 dev_info(adev->dev, "Using ATPX for runtime pm\n"); 157 } else if (amdgpu_device_supports_boco(dev) && 158 (amdgpu_runtime_pm != 0)) { /* enable boco as runtime mode */ 159 adev->pm.rpm_mode = AMDGPU_RUNPM_BOCO; 160 dev_info(adev->dev, "Using BOCO for runtime pm\n"); 161 } else if (amdgpu_device_supports_baco(dev) && 162 (amdgpu_runtime_pm != 0)) { 163 switch (adev->asic_type) { 164 case CHIP_VEGA20: 165 case CHIP_ARCTURUS: 166 /* enable BACO as runpm mode if runpm=1 */ 167 if (amdgpu_runtime_pm > 0) 168 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO; 169 break; 170 case CHIP_VEGA10: 171 /* enable BACO as runpm mode if noretry=0 */ 172 if (!adev->gmc.noretry) 173 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO; 174 break; 175 default: 176 /* enable BACO as runpm mode on CI+ */ 177 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO; 178 break; 179 } 180 181 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) 182 dev_info(adev->dev, "Using BACO for runtime pm\n"); 183 } 184 185 /* Call ACPI methods: require modeset init 186 * but failure is not fatal 187 */ 188 189 acpi_status = amdgpu_acpi_init(adev); 190 if (acpi_status) 191 dev_dbg(dev->dev, "Error during ACPI methods call\n"); 192 193 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_LOAD)) 194 DRM_WARN("smart shift update failed\n"); 195 196 out: 197 if (r) 198 amdgpu_driver_unload_kms(dev); 199 200 return r; 201 } 202 203 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, 204 struct drm_amdgpu_query_fw *query_fw, 205 struct amdgpu_device *adev) 206 { 207 switch (query_fw->fw_type) { 208 case AMDGPU_INFO_FW_VCE: 209 fw_info->ver = adev->vce.fw_version; 210 fw_info->feature = adev->vce.fb_version; 211 break; 212 case AMDGPU_INFO_FW_UVD: 213 fw_info->ver = adev->uvd.fw_version; 214 fw_info->feature = 0; 215 break; 216 case AMDGPU_INFO_FW_VCN: 217 fw_info->ver = adev->vcn.fw_version; 218 fw_info->feature = 0; 219 break; 220 case AMDGPU_INFO_FW_GMC: 221 fw_info->ver = adev->gmc.fw_version; 222 fw_info->feature = 0; 223 break; 224 case AMDGPU_INFO_FW_GFX_ME: 225 fw_info->ver = adev->gfx.me_fw_version; 226 fw_info->feature = adev->gfx.me_feature_version; 227 break; 228 case AMDGPU_INFO_FW_GFX_PFP: 229 fw_info->ver = adev->gfx.pfp_fw_version; 230 fw_info->feature = adev->gfx.pfp_feature_version; 231 break; 232 case AMDGPU_INFO_FW_GFX_CE: 233 fw_info->ver = adev->gfx.ce_fw_version; 234 fw_info->feature = adev->gfx.ce_feature_version; 235 break; 236 case AMDGPU_INFO_FW_GFX_RLC: 237 fw_info->ver = adev->gfx.rlc_fw_version; 238 fw_info->feature = adev->gfx.rlc_feature_version; 239 break; 240 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL: 241 fw_info->ver = adev->gfx.rlc_srlc_fw_version; 242 fw_info->feature = adev->gfx.rlc_srlc_feature_version; 243 break; 244 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM: 245 fw_info->ver = adev->gfx.rlc_srlg_fw_version; 246 fw_info->feature = adev->gfx.rlc_srlg_feature_version; 247 break; 248 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM: 249 fw_info->ver = adev->gfx.rlc_srls_fw_version; 250 fw_info->feature = adev->gfx.rlc_srls_feature_version; 251 break; 252 case AMDGPU_INFO_FW_GFX_RLCP: 253 fw_info->ver = adev->gfx.rlcp_ucode_version; 254 fw_info->feature = adev->gfx.rlcp_ucode_feature_version; 255 break; 256 case AMDGPU_INFO_FW_GFX_RLCV: 257 fw_info->ver = adev->gfx.rlcv_ucode_version; 258 fw_info->feature = adev->gfx.rlcv_ucode_feature_version; 259 break; 260 case AMDGPU_INFO_FW_GFX_MEC: 261 if (query_fw->index == 0) { 262 fw_info->ver = adev->gfx.mec_fw_version; 263 fw_info->feature = adev->gfx.mec_feature_version; 264 } else if (query_fw->index == 1) { 265 fw_info->ver = adev->gfx.mec2_fw_version; 266 fw_info->feature = adev->gfx.mec2_feature_version; 267 } else 268 return -EINVAL; 269 break; 270 case AMDGPU_INFO_FW_SMC: 271 fw_info->ver = adev->pm.fw_version; 272 fw_info->feature = 0; 273 break; 274 case AMDGPU_INFO_FW_TA: 275 switch (query_fw->index) { 276 case TA_FW_TYPE_PSP_XGMI: 277 fw_info->ver = adev->psp.xgmi_context.context.bin_desc.fw_version; 278 fw_info->feature = adev->psp.xgmi_context.context 279 .bin_desc.feature_version; 280 break; 281 case TA_FW_TYPE_PSP_RAS: 282 fw_info->ver = adev->psp.ras_context.context.bin_desc.fw_version; 283 fw_info->feature = adev->psp.ras_context.context 284 .bin_desc.feature_version; 285 break; 286 case TA_FW_TYPE_PSP_HDCP: 287 fw_info->ver = adev->psp.hdcp_context.context.bin_desc.fw_version; 288 fw_info->feature = adev->psp.hdcp_context.context 289 .bin_desc.feature_version; 290 break; 291 case TA_FW_TYPE_PSP_DTM: 292 fw_info->ver = adev->psp.dtm_context.context.bin_desc.fw_version; 293 fw_info->feature = adev->psp.dtm_context.context 294 .bin_desc.feature_version; 295 break; 296 case TA_FW_TYPE_PSP_RAP: 297 fw_info->ver = adev->psp.rap_context.context.bin_desc.fw_version; 298 fw_info->feature = adev->psp.rap_context.context 299 .bin_desc.feature_version; 300 break; 301 case TA_FW_TYPE_PSP_SECUREDISPLAY: 302 fw_info->ver = adev->psp.securedisplay_context.context.bin_desc.fw_version; 303 fw_info->feature = 304 adev->psp.securedisplay_context.context.bin_desc 305 .feature_version; 306 break; 307 default: 308 return -EINVAL; 309 } 310 break; 311 case AMDGPU_INFO_FW_SDMA: 312 if (query_fw->index >= adev->sdma.num_instances) 313 return -EINVAL; 314 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version; 315 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version; 316 break; 317 case AMDGPU_INFO_FW_SOS: 318 fw_info->ver = adev->psp.sos.fw_version; 319 fw_info->feature = adev->psp.sos.feature_version; 320 break; 321 case AMDGPU_INFO_FW_ASD: 322 fw_info->ver = adev->psp.asd_context.bin_desc.fw_version; 323 fw_info->feature = adev->psp.asd_context.bin_desc.feature_version; 324 break; 325 case AMDGPU_INFO_FW_DMCU: 326 fw_info->ver = adev->dm.dmcu_fw_version; 327 fw_info->feature = 0; 328 break; 329 case AMDGPU_INFO_FW_DMCUB: 330 fw_info->ver = adev->dm.dmcub_fw_version; 331 fw_info->feature = 0; 332 break; 333 case AMDGPU_INFO_FW_TOC: 334 fw_info->ver = adev->psp.toc.fw_version; 335 fw_info->feature = adev->psp.toc.feature_version; 336 break; 337 case AMDGPU_INFO_FW_CAP: 338 fw_info->ver = adev->psp.cap_fw_version; 339 fw_info->feature = adev->psp.cap_feature_version; 340 break; 341 case AMDGPU_INFO_FW_MES_KIQ: 342 fw_info->ver = adev->mes.kiq_version & AMDGPU_MES_VERSION_MASK; 343 fw_info->feature = (adev->mes.kiq_version & AMDGPU_MES_FEAT_VERSION_MASK) 344 >> AMDGPU_MES_FEAT_VERSION_SHIFT; 345 break; 346 case AMDGPU_INFO_FW_MES: 347 fw_info->ver = adev->mes.sched_version & AMDGPU_MES_VERSION_MASK; 348 fw_info->feature = (adev->mes.sched_version & AMDGPU_MES_FEAT_VERSION_MASK) 349 >> AMDGPU_MES_FEAT_VERSION_SHIFT; 350 break; 351 case AMDGPU_INFO_FW_IMU: 352 fw_info->ver = adev->gfx.imu_fw_version; 353 fw_info->feature = 0; 354 break; 355 case AMDGPU_INFO_FW_VPE: 356 fw_info->ver = adev->vpe.fw_version; 357 fw_info->feature = adev->vpe.feature_version; 358 break; 359 default: 360 return -EINVAL; 361 } 362 return 0; 363 } 364 365 static int amdgpu_hw_ip_info(struct amdgpu_device *adev, 366 struct drm_amdgpu_info *info, 367 struct drm_amdgpu_info_hw_ip *result) 368 { 369 uint32_t ib_start_alignment = 0; 370 uint32_t ib_size_alignment = 0; 371 enum amd_ip_block_type type; 372 unsigned int num_rings = 0; 373 unsigned int i, j; 374 375 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 376 return -EINVAL; 377 378 switch (info->query_hw_ip.type) { 379 case AMDGPU_HW_IP_GFX: 380 type = AMD_IP_BLOCK_TYPE_GFX; 381 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 382 if (adev->gfx.gfx_ring[i].sched.ready) 383 ++num_rings; 384 ib_start_alignment = 32; 385 ib_size_alignment = 32; 386 break; 387 case AMDGPU_HW_IP_COMPUTE: 388 type = AMD_IP_BLOCK_TYPE_GFX; 389 for (i = 0; i < adev->gfx.num_compute_rings; i++) 390 if (adev->gfx.compute_ring[i].sched.ready) 391 ++num_rings; 392 ib_start_alignment = 32; 393 ib_size_alignment = 32; 394 break; 395 case AMDGPU_HW_IP_DMA: 396 type = AMD_IP_BLOCK_TYPE_SDMA; 397 for (i = 0; i < adev->sdma.num_instances; i++) 398 if (adev->sdma.instance[i].ring.sched.ready) 399 ++num_rings; 400 ib_start_alignment = 256; 401 ib_size_alignment = 4; 402 break; 403 case AMDGPU_HW_IP_UVD: 404 type = AMD_IP_BLOCK_TYPE_UVD; 405 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 406 if (adev->uvd.harvest_config & (1 << i)) 407 continue; 408 409 if (adev->uvd.inst[i].ring.sched.ready) 410 ++num_rings; 411 } 412 ib_start_alignment = 64; 413 ib_size_alignment = 64; 414 break; 415 case AMDGPU_HW_IP_VCE: 416 type = AMD_IP_BLOCK_TYPE_VCE; 417 for (i = 0; i < adev->vce.num_rings; i++) 418 if (adev->vce.ring[i].sched.ready) 419 ++num_rings; 420 ib_start_alignment = 4; 421 ib_size_alignment = 1; 422 break; 423 case AMDGPU_HW_IP_UVD_ENC: 424 type = AMD_IP_BLOCK_TYPE_UVD; 425 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 426 if (adev->uvd.harvest_config & (1 << i)) 427 continue; 428 429 for (j = 0; j < adev->uvd.num_enc_rings; j++) 430 if (adev->uvd.inst[i].ring_enc[j].sched.ready) 431 ++num_rings; 432 } 433 ib_start_alignment = 64; 434 ib_size_alignment = 64; 435 break; 436 case AMDGPU_HW_IP_VCN_DEC: 437 type = AMD_IP_BLOCK_TYPE_VCN; 438 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 439 if (adev->vcn.harvest_config & (1 << i)) 440 continue; 441 442 if (adev->vcn.inst[i].ring_dec.sched.ready) 443 ++num_rings; 444 } 445 ib_start_alignment = 16; 446 ib_size_alignment = 16; 447 break; 448 case AMDGPU_HW_IP_VCN_ENC: 449 type = AMD_IP_BLOCK_TYPE_VCN; 450 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 451 if (adev->vcn.harvest_config & (1 << i)) 452 continue; 453 454 for (j = 0; j < adev->vcn.num_enc_rings; j++) 455 if (adev->vcn.inst[i].ring_enc[j].sched.ready) 456 ++num_rings; 457 } 458 ib_start_alignment = 64; 459 ib_size_alignment = 1; 460 break; 461 case AMDGPU_HW_IP_VCN_JPEG: 462 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 463 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 464 465 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { 466 if (adev->jpeg.harvest_config & (1 << i)) 467 continue; 468 469 for (j = 0; j < adev->jpeg.num_jpeg_rings; j++) 470 if (adev->jpeg.inst[i].ring_dec[j].sched.ready) 471 ++num_rings; 472 } 473 ib_start_alignment = 16; 474 ib_size_alignment = 16; 475 break; 476 case AMDGPU_HW_IP_VPE: 477 type = AMD_IP_BLOCK_TYPE_VPE; 478 if (adev->vpe.ring.sched.ready) 479 ++num_rings; 480 ib_start_alignment = 256; 481 ib_size_alignment = 4; 482 break; 483 default: 484 return -EINVAL; 485 } 486 487 for (i = 0; i < adev->num_ip_blocks; i++) 488 if (adev->ip_blocks[i].version->type == type && 489 adev->ip_blocks[i].status.valid) 490 break; 491 492 if (i == adev->num_ip_blocks) 493 return 0; 494 495 num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type], 496 num_rings); 497 498 result->hw_ip_version_major = adev->ip_blocks[i].version->major; 499 result->hw_ip_version_minor = adev->ip_blocks[i].version->minor; 500 501 if (adev->asic_type >= CHIP_VEGA10) { 502 switch (type) { 503 case AMD_IP_BLOCK_TYPE_GFX: 504 result->ip_discovery_version = 505 amdgpu_ip_version(adev, GC_HWIP, 0); 506 break; 507 case AMD_IP_BLOCK_TYPE_SDMA: 508 result->ip_discovery_version = 509 amdgpu_ip_version(adev, SDMA0_HWIP, 0); 510 break; 511 case AMD_IP_BLOCK_TYPE_UVD: 512 case AMD_IP_BLOCK_TYPE_VCN: 513 case AMD_IP_BLOCK_TYPE_JPEG: 514 result->ip_discovery_version = 515 amdgpu_ip_version(adev, UVD_HWIP, 0); 516 break; 517 case AMD_IP_BLOCK_TYPE_VCE: 518 result->ip_discovery_version = 519 amdgpu_ip_version(adev, VCE_HWIP, 0); 520 break; 521 case AMD_IP_BLOCK_TYPE_VPE: 522 result->ip_discovery_version = 523 amdgpu_ip_version(adev, VPE_HWIP, 0); 524 break; 525 default: 526 result->ip_discovery_version = 0; 527 break; 528 } 529 } else { 530 result->ip_discovery_version = 0; 531 } 532 result->capabilities_flags = 0; 533 result->available_rings = (1 << num_rings) - 1; 534 result->ib_start_alignment = ib_start_alignment; 535 result->ib_size_alignment = ib_size_alignment; 536 return 0; 537 } 538 539 /* 540 * Userspace get information ioctl 541 */ 542 /** 543 * amdgpu_info_ioctl - answer a device specific request. 544 * 545 * @dev: drm device pointer 546 * @data: request object 547 * @filp: drm filp 548 * 549 * This function is used to pass device specific parameters to the userspace 550 * drivers. Examples include: pci device id, pipeline parms, tiling params, 551 * etc. (all asics). 552 * Returns 0 on success, -EINVAL on failure. 553 */ 554 int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 555 { 556 struct amdgpu_device *adev = drm_to_adev(dev); 557 struct drm_amdgpu_info *info = data; 558 struct amdgpu_mode_info *minfo = &adev->mode_info; 559 void __user *out = (void __user *)(uintptr_t)info->return_pointer; 560 uint32_t size = info->return_size; 561 struct drm_crtc *crtc; 562 uint32_t ui32 = 0; 563 uint64_t ui64 = 0; 564 int i, found; 565 int ui32_size = sizeof(ui32); 566 567 if (!info->return_size || !info->return_pointer) 568 return -EINVAL; 569 570 switch (info->query) { 571 case AMDGPU_INFO_ACCEL_WORKING: 572 ui32 = adev->accel_working; 573 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 574 case AMDGPU_INFO_CRTC_FROM_ID: 575 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { 576 crtc = (struct drm_crtc *)minfo->crtcs[i]; 577 if (crtc && crtc->base.id == info->mode_crtc.id) { 578 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 579 580 ui32 = amdgpu_crtc->crtc_id; 581 found = 1; 582 break; 583 } 584 } 585 if (!found) { 586 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); 587 return -EINVAL; 588 } 589 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 590 case AMDGPU_INFO_HW_IP_INFO: { 591 struct drm_amdgpu_info_hw_ip ip = {}; 592 int ret; 593 594 ret = amdgpu_hw_ip_info(adev, info, &ip); 595 if (ret) 596 return ret; 597 598 ret = copy_to_user(out, &ip, min_t(size_t, size, sizeof(ip))); 599 return ret ? -EFAULT : 0; 600 } 601 case AMDGPU_INFO_HW_IP_COUNT: { 602 enum amd_ip_block_type type; 603 uint32_t count = 0; 604 605 switch (info->query_hw_ip.type) { 606 case AMDGPU_HW_IP_GFX: 607 type = AMD_IP_BLOCK_TYPE_GFX; 608 break; 609 case AMDGPU_HW_IP_COMPUTE: 610 type = AMD_IP_BLOCK_TYPE_GFX; 611 break; 612 case AMDGPU_HW_IP_DMA: 613 type = AMD_IP_BLOCK_TYPE_SDMA; 614 break; 615 case AMDGPU_HW_IP_UVD: 616 type = AMD_IP_BLOCK_TYPE_UVD; 617 break; 618 case AMDGPU_HW_IP_VCE: 619 type = AMD_IP_BLOCK_TYPE_VCE; 620 break; 621 case AMDGPU_HW_IP_UVD_ENC: 622 type = AMD_IP_BLOCK_TYPE_UVD; 623 break; 624 case AMDGPU_HW_IP_VCN_DEC: 625 case AMDGPU_HW_IP_VCN_ENC: 626 type = AMD_IP_BLOCK_TYPE_VCN; 627 break; 628 case AMDGPU_HW_IP_VCN_JPEG: 629 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 630 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 631 break; 632 default: 633 return -EINVAL; 634 } 635 636 for (i = 0; i < adev->num_ip_blocks; i++) 637 if (adev->ip_blocks[i].version->type == type && 638 adev->ip_blocks[i].status.valid && 639 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 640 count++; 641 642 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; 643 } 644 case AMDGPU_INFO_TIMESTAMP: 645 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev); 646 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 647 case AMDGPU_INFO_FW_VERSION: { 648 struct drm_amdgpu_info_firmware fw_info; 649 int ret; 650 651 /* We only support one instance of each IP block right now. */ 652 if (info->query_fw.ip_instance != 0) 653 return -EINVAL; 654 655 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev); 656 if (ret) 657 return ret; 658 659 return copy_to_user(out, &fw_info, 660 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0; 661 } 662 case AMDGPU_INFO_NUM_BYTES_MOVED: 663 ui64 = atomic64_read(&adev->num_bytes_moved); 664 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 665 case AMDGPU_INFO_NUM_EVICTIONS: 666 ui64 = atomic64_read(&adev->num_evictions); 667 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 668 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS: 669 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults); 670 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 671 case AMDGPU_INFO_VRAM_USAGE: 672 ui64 = ttm_resource_manager_usage(&adev->mman.vram_mgr.manager); 673 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 674 case AMDGPU_INFO_VIS_VRAM_USAGE: 675 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr); 676 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 677 case AMDGPU_INFO_GTT_USAGE: 678 ui64 = ttm_resource_manager_usage(&adev->mman.gtt_mgr.manager); 679 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 680 case AMDGPU_INFO_GDS_CONFIG: { 681 struct drm_amdgpu_info_gds gds_info; 682 683 memset(&gds_info, 0, sizeof(gds_info)); 684 gds_info.compute_partition_size = adev->gds.gds_size; 685 gds_info.gds_total_size = adev->gds.gds_size; 686 gds_info.gws_per_compute_partition = adev->gds.gws_size; 687 gds_info.oa_per_compute_partition = adev->gds.oa_size; 688 return copy_to_user(out, &gds_info, 689 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0; 690 } 691 case AMDGPU_INFO_VRAM_GTT: { 692 struct drm_amdgpu_info_vram_gtt vram_gtt; 693 694 vram_gtt.vram_size = adev->gmc.real_vram_size - 695 atomic64_read(&adev->vram_pin_size) - 696 AMDGPU_VM_RESERVED_VRAM; 697 vram_gtt.vram_cpu_accessible_size = 698 min(adev->gmc.visible_vram_size - 699 atomic64_read(&adev->visible_pin_size), 700 vram_gtt.vram_size); 701 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size; 702 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size); 703 return copy_to_user(out, &vram_gtt, 704 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; 705 } 706 case AMDGPU_INFO_MEMORY: { 707 struct drm_amdgpu_memory_info mem; 708 struct ttm_resource_manager *gtt_man = 709 &adev->mman.gtt_mgr.manager; 710 struct ttm_resource_manager *vram_man = 711 &adev->mman.vram_mgr.manager; 712 713 memset(&mem, 0, sizeof(mem)); 714 mem.vram.total_heap_size = adev->gmc.real_vram_size; 715 mem.vram.usable_heap_size = adev->gmc.real_vram_size - 716 atomic64_read(&adev->vram_pin_size) - 717 AMDGPU_VM_RESERVED_VRAM; 718 mem.vram.heap_usage = 719 ttm_resource_manager_usage(vram_man); 720 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4; 721 722 mem.cpu_accessible_vram.total_heap_size = 723 adev->gmc.visible_vram_size; 724 mem.cpu_accessible_vram.usable_heap_size = 725 min(adev->gmc.visible_vram_size - 726 atomic64_read(&adev->visible_pin_size), 727 mem.vram.usable_heap_size); 728 mem.cpu_accessible_vram.heap_usage = 729 amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr); 730 mem.cpu_accessible_vram.max_allocation = 731 mem.cpu_accessible_vram.usable_heap_size * 3 / 4; 732 733 mem.gtt.total_heap_size = gtt_man->size; 734 mem.gtt.usable_heap_size = mem.gtt.total_heap_size - 735 atomic64_read(&adev->gart_pin_size); 736 mem.gtt.heap_usage = ttm_resource_manager_usage(gtt_man); 737 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4; 738 739 return copy_to_user(out, &mem, 740 min((size_t)size, sizeof(mem))) 741 ? -EFAULT : 0; 742 } 743 case AMDGPU_INFO_READ_MMR_REG: { 744 unsigned int n, alloc_size; 745 uint32_t *regs; 746 unsigned int se_num = (info->read_mmr_reg.instance >> 747 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & 748 AMDGPU_INFO_MMR_SE_INDEX_MASK; 749 unsigned int sh_num = (info->read_mmr_reg.instance >> 750 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & 751 AMDGPU_INFO_MMR_SH_INDEX_MASK; 752 753 /* set full masks if the userspace set all bits 754 * in the bitfields 755 */ 756 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) 757 se_num = 0xffffffff; 758 else if (se_num >= AMDGPU_GFX_MAX_SE) 759 return -EINVAL; 760 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) 761 sh_num = 0xffffffff; 762 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE) 763 return -EINVAL; 764 765 if (info->read_mmr_reg.count > 128) 766 return -EINVAL; 767 768 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL); 769 if (!regs) 770 return -ENOMEM; 771 alloc_size = info->read_mmr_reg.count * sizeof(*regs); 772 773 amdgpu_gfx_off_ctrl(adev, false); 774 for (i = 0; i < info->read_mmr_reg.count; i++) { 775 if (amdgpu_asic_read_register(adev, se_num, sh_num, 776 info->read_mmr_reg.dword_offset + i, 777 ®s[i])) { 778 DRM_DEBUG_KMS("unallowed offset %#x\n", 779 info->read_mmr_reg.dword_offset + i); 780 kfree(regs); 781 amdgpu_gfx_off_ctrl(adev, true); 782 return -EFAULT; 783 } 784 } 785 amdgpu_gfx_off_ctrl(adev, true); 786 n = copy_to_user(out, regs, min(size, alloc_size)); 787 kfree(regs); 788 return n ? -EFAULT : 0; 789 } 790 case AMDGPU_INFO_DEV_INFO: { 791 struct drm_amdgpu_info_device *dev_info; 792 uint64_t vm_size; 793 uint32_t pcie_gen_mask; 794 int ret; 795 796 dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL); 797 if (!dev_info) 798 return -ENOMEM; 799 800 dev_info->device_id = adev->pdev->device; 801 dev_info->chip_rev = adev->rev_id; 802 dev_info->external_rev = adev->external_rev_id; 803 dev_info->pci_rev = adev->pdev->revision; 804 dev_info->family = adev->family; 805 dev_info->num_shader_engines = adev->gfx.config.max_shader_engines; 806 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 807 /* return all clocks in KHz */ 808 dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; 809 if (adev->pm.dpm_enabled) { 810 dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10; 811 dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10; 812 dev_info->min_engine_clock = amdgpu_dpm_get_sclk(adev, true) * 10; 813 dev_info->min_memory_clock = amdgpu_dpm_get_mclk(adev, true) * 10; 814 } else { 815 dev_info->max_engine_clock = 816 dev_info->min_engine_clock = 817 adev->clock.default_sclk * 10; 818 dev_info->max_memory_clock = 819 dev_info->min_memory_clock = 820 adev->clock.default_mclk * 10; 821 } 822 dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; 823 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se * 824 adev->gfx.config.max_shader_engines; 825 dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; 826 dev_info->ids_flags = 0; 827 if (adev->flags & AMD_IS_APU) 828 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION; 829 if (adev->gfx.mcbp) 830 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION; 831 if (amdgpu_is_tmz(adev)) 832 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ; 833 if (adev->gfx.config.ta_cntl2_truncate_coord_mode) 834 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD; 835 836 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 837 vm_size -= AMDGPU_VA_RESERVED_SIZE; 838 839 /* Older VCE FW versions are buggy and can handle only 40bits */ 840 if (adev->vce.fw_version && 841 adev->vce.fw_version < AMDGPU_VCE_FW_53_45) 842 vm_size = min(vm_size, 1ULL << 40); 843 844 dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_SIZE; 845 dev_info->virtual_address_max = 846 min(vm_size, AMDGPU_GMC_HOLE_START); 847 848 if (vm_size > AMDGPU_GMC_HOLE_START) { 849 dev_info->high_va_offset = AMDGPU_GMC_HOLE_END; 850 dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size; 851 } 852 dev_info->virtual_address_alignment = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 853 dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE; 854 dev_info->gart_page_size = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 855 dev_info->cu_active_number = adev->gfx.cu_info.number; 856 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; 857 dev_info->ce_ram_size = adev->gfx.ce_ram_size; 858 memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0], 859 sizeof(adev->gfx.cu_info.ao_cu_bitmap)); 860 memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], 861 sizeof(dev_info->cu_bitmap)); 862 dev_info->vram_type = adev->gmc.vram_type; 863 dev_info->vram_bit_width = adev->gmc.vram_width; 864 dev_info->vce_harvest_config = adev->vce.harvest_config; 865 dev_info->gc_double_offchip_lds_buf = 866 adev->gfx.config.double_offchip_lds_buf; 867 dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size; 868 dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs; 869 dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh; 870 dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches; 871 dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth; 872 dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth; 873 dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads; 874 875 if (adev->family >= AMDGPU_FAMILY_NV) 876 dev_info->pa_sc_tile_steering_override = 877 adev->gfx.config.pa_sc_tile_steering_override; 878 879 dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask; 880 881 /* Combine the chip gen mask with the platform (CPU/mobo) mask. */ 882 pcie_gen_mask = adev->pm.pcie_gen_mask & (adev->pm.pcie_gen_mask >> 16); 883 dev_info->pcie_gen = fls(pcie_gen_mask); 884 dev_info->pcie_num_lanes = 885 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 ? 32 : 886 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 ? 16 : 887 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 ? 12 : 888 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 ? 8 : 889 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 ? 4 : 890 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 ? 2 : 1; 891 892 dev_info->tcp_cache_size = adev->gfx.config.gc_tcp_l1_size; 893 dev_info->num_sqc_per_wgp = adev->gfx.config.gc_num_sqc_per_wgp; 894 dev_info->sqc_data_cache_size = adev->gfx.config.gc_l1_data_cache_size_per_sqc; 895 dev_info->sqc_inst_cache_size = adev->gfx.config.gc_l1_instruction_cache_size_per_sqc; 896 dev_info->gl1c_cache_size = adev->gfx.config.gc_gl1c_size_per_instance * 897 adev->gfx.config.gc_gl1c_per_sa; 898 dev_info->gl2c_cache_size = adev->gfx.config.gc_gl2c_per_gpu; 899 dev_info->mall_size = adev->gmc.mall_size; 900 901 902 if (adev->gfx.funcs->get_gfx_shadow_info) { 903 struct amdgpu_gfx_shadow_info shadow_info; 904 905 ret = amdgpu_gfx_get_gfx_shadow_info(adev, &shadow_info); 906 if (!ret) { 907 dev_info->shadow_size = shadow_info.shadow_size; 908 dev_info->shadow_alignment = shadow_info.shadow_alignment; 909 dev_info->csa_size = shadow_info.csa_size; 910 dev_info->csa_alignment = shadow_info.csa_alignment; 911 } 912 } 913 914 ret = copy_to_user(out, dev_info, 915 min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0; 916 kfree(dev_info); 917 return ret; 918 } 919 case AMDGPU_INFO_VCE_CLOCK_TABLE: { 920 unsigned int i; 921 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {}; 922 struct amd_vce_state *vce_state; 923 924 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) { 925 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i); 926 if (vce_state) { 927 vce_clk_table.entries[i].sclk = vce_state->sclk; 928 vce_clk_table.entries[i].mclk = vce_state->mclk; 929 vce_clk_table.entries[i].eclk = vce_state->evclk; 930 vce_clk_table.num_valid_entries++; 931 } 932 } 933 934 return copy_to_user(out, &vce_clk_table, 935 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0; 936 } 937 case AMDGPU_INFO_VBIOS: { 938 uint32_t bios_size = adev->bios_size; 939 940 switch (info->vbios_info.type) { 941 case AMDGPU_INFO_VBIOS_SIZE: 942 return copy_to_user(out, &bios_size, 943 min((size_t)size, sizeof(bios_size))) 944 ? -EFAULT : 0; 945 case AMDGPU_INFO_VBIOS_IMAGE: { 946 uint8_t *bios; 947 uint32_t bios_offset = info->vbios_info.offset; 948 949 if (bios_offset >= bios_size) 950 return -EINVAL; 951 952 bios = adev->bios + bios_offset; 953 return copy_to_user(out, bios, 954 min((size_t)size, (size_t)(bios_size - bios_offset))) 955 ? -EFAULT : 0; 956 } 957 case AMDGPU_INFO_VBIOS_INFO: { 958 struct drm_amdgpu_info_vbios vbios_info = {}; 959 struct atom_context *atom_context; 960 961 atom_context = adev->mode_info.atom_context; 962 if (atom_context) { 963 memcpy(vbios_info.name, atom_context->name, 964 sizeof(atom_context->name)); 965 memcpy(vbios_info.vbios_pn, atom_context->vbios_pn, 966 sizeof(atom_context->vbios_pn)); 967 vbios_info.version = atom_context->version; 968 memcpy(vbios_info.vbios_ver_str, atom_context->vbios_ver_str, 969 sizeof(atom_context->vbios_ver_str)); 970 memcpy(vbios_info.date, atom_context->date, 971 sizeof(atom_context->date)); 972 } 973 974 return copy_to_user(out, &vbios_info, 975 min((size_t)size, sizeof(vbios_info))) ? -EFAULT : 0; 976 } 977 default: 978 DRM_DEBUG_KMS("Invalid request %d\n", 979 info->vbios_info.type); 980 return -EINVAL; 981 } 982 } 983 case AMDGPU_INFO_NUM_HANDLES: { 984 struct drm_amdgpu_info_num_handles handle; 985 986 switch (info->query_hw_ip.type) { 987 case AMDGPU_HW_IP_UVD: 988 /* Starting Polaris, we support unlimited UVD handles */ 989 if (adev->asic_type < CHIP_POLARIS10) { 990 handle.uvd_max_handles = adev->uvd.max_handles; 991 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev); 992 993 return copy_to_user(out, &handle, 994 min((size_t)size, sizeof(handle))) ? -EFAULT : 0; 995 } else { 996 return -ENODATA; 997 } 998 999 break; 1000 default: 1001 return -EINVAL; 1002 } 1003 } 1004 case AMDGPU_INFO_SENSOR: { 1005 if (!adev->pm.dpm_enabled) 1006 return -ENOENT; 1007 1008 switch (info->sensor_info.type) { 1009 case AMDGPU_INFO_SENSOR_GFX_SCLK: 1010 /* get sclk in Mhz */ 1011 if (amdgpu_dpm_read_sensor(adev, 1012 AMDGPU_PP_SENSOR_GFX_SCLK, 1013 (void *)&ui32, &ui32_size)) { 1014 return -EINVAL; 1015 } 1016 ui32 /= 100; 1017 break; 1018 case AMDGPU_INFO_SENSOR_GFX_MCLK: 1019 /* get mclk in Mhz */ 1020 if (amdgpu_dpm_read_sensor(adev, 1021 AMDGPU_PP_SENSOR_GFX_MCLK, 1022 (void *)&ui32, &ui32_size)) { 1023 return -EINVAL; 1024 } 1025 ui32 /= 100; 1026 break; 1027 case AMDGPU_INFO_SENSOR_GPU_TEMP: 1028 /* get temperature in millidegrees C */ 1029 if (amdgpu_dpm_read_sensor(adev, 1030 AMDGPU_PP_SENSOR_GPU_TEMP, 1031 (void *)&ui32, &ui32_size)) { 1032 return -EINVAL; 1033 } 1034 break; 1035 case AMDGPU_INFO_SENSOR_GPU_LOAD: 1036 /* get GPU load */ 1037 if (amdgpu_dpm_read_sensor(adev, 1038 AMDGPU_PP_SENSOR_GPU_LOAD, 1039 (void *)&ui32, &ui32_size)) { 1040 return -EINVAL; 1041 } 1042 break; 1043 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER: 1044 /* get average GPU power */ 1045 if (amdgpu_dpm_read_sensor(adev, 1046 AMDGPU_PP_SENSOR_GPU_AVG_POWER, 1047 (void *)&ui32, &ui32_size)) { 1048 return -EINVAL; 1049 } 1050 ui32 >>= 8; 1051 break; 1052 case AMDGPU_INFO_SENSOR_VDDNB: 1053 /* get VDDNB in millivolts */ 1054 if (amdgpu_dpm_read_sensor(adev, 1055 AMDGPU_PP_SENSOR_VDDNB, 1056 (void *)&ui32, &ui32_size)) { 1057 return -EINVAL; 1058 } 1059 break; 1060 case AMDGPU_INFO_SENSOR_VDDGFX: 1061 /* get VDDGFX in millivolts */ 1062 if (amdgpu_dpm_read_sensor(adev, 1063 AMDGPU_PP_SENSOR_VDDGFX, 1064 (void *)&ui32, &ui32_size)) { 1065 return -EINVAL; 1066 } 1067 break; 1068 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK: 1069 /* get stable pstate sclk in Mhz */ 1070 if (amdgpu_dpm_read_sensor(adev, 1071 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 1072 (void *)&ui32, &ui32_size)) { 1073 return -EINVAL; 1074 } 1075 ui32 /= 100; 1076 break; 1077 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK: 1078 /* get stable pstate mclk in Mhz */ 1079 if (amdgpu_dpm_read_sensor(adev, 1080 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 1081 (void *)&ui32, &ui32_size)) { 1082 return -EINVAL; 1083 } 1084 ui32 /= 100; 1085 break; 1086 case AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK: 1087 /* get peak pstate sclk in Mhz */ 1088 if (amdgpu_dpm_read_sensor(adev, 1089 AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK, 1090 (void *)&ui32, &ui32_size)) { 1091 return -EINVAL; 1092 } 1093 ui32 /= 100; 1094 break; 1095 case AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK: 1096 /* get peak pstate mclk in Mhz */ 1097 if (amdgpu_dpm_read_sensor(adev, 1098 AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK, 1099 (void *)&ui32, &ui32_size)) { 1100 return -EINVAL; 1101 } 1102 ui32 /= 100; 1103 break; 1104 default: 1105 DRM_DEBUG_KMS("Invalid request %d\n", 1106 info->sensor_info.type); 1107 return -EINVAL; 1108 } 1109 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 1110 } 1111 case AMDGPU_INFO_VRAM_LOST_COUNTER: 1112 ui32 = atomic_read(&adev->vram_lost_counter); 1113 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 1114 case AMDGPU_INFO_RAS_ENABLED_FEATURES: { 1115 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1116 uint64_t ras_mask; 1117 1118 if (!ras) 1119 return -EINVAL; 1120 ras_mask = (uint64_t)adev->ras_enabled << 32 | ras->features; 1121 1122 return copy_to_user(out, &ras_mask, 1123 min_t(u64, size, sizeof(ras_mask))) ? 1124 -EFAULT : 0; 1125 } 1126 case AMDGPU_INFO_VIDEO_CAPS: { 1127 const struct amdgpu_video_codecs *codecs; 1128 struct drm_amdgpu_info_video_caps *caps; 1129 int r; 1130 1131 if (!adev->asic_funcs->query_video_codecs) 1132 return -EINVAL; 1133 1134 switch (info->video_cap.type) { 1135 case AMDGPU_INFO_VIDEO_CAPS_DECODE: 1136 r = amdgpu_asic_query_video_codecs(adev, false, &codecs); 1137 if (r) 1138 return -EINVAL; 1139 break; 1140 case AMDGPU_INFO_VIDEO_CAPS_ENCODE: 1141 r = amdgpu_asic_query_video_codecs(adev, true, &codecs); 1142 if (r) 1143 return -EINVAL; 1144 break; 1145 default: 1146 DRM_DEBUG_KMS("Invalid request %d\n", 1147 info->video_cap.type); 1148 return -EINVAL; 1149 } 1150 1151 caps = kzalloc(sizeof(*caps), GFP_KERNEL); 1152 if (!caps) 1153 return -ENOMEM; 1154 1155 for (i = 0; i < codecs->codec_count; i++) { 1156 int idx = codecs->codec_array[i].codec_type; 1157 1158 switch (idx) { 1159 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2: 1160 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4: 1161 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1: 1162 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC: 1163 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC: 1164 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG: 1165 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9: 1166 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1: 1167 caps->codec_info[idx].valid = 1; 1168 caps->codec_info[idx].max_width = 1169 codecs->codec_array[i].max_width; 1170 caps->codec_info[idx].max_height = 1171 codecs->codec_array[i].max_height; 1172 caps->codec_info[idx].max_pixels_per_frame = 1173 codecs->codec_array[i].max_pixels_per_frame; 1174 caps->codec_info[idx].max_level = 1175 codecs->codec_array[i].max_level; 1176 break; 1177 default: 1178 break; 1179 } 1180 } 1181 r = copy_to_user(out, caps, 1182 min((size_t)size, sizeof(*caps))) ? -EFAULT : 0; 1183 kfree(caps); 1184 return r; 1185 } 1186 case AMDGPU_INFO_MAX_IBS: { 1187 uint32_t max_ibs[AMDGPU_HW_IP_NUM]; 1188 1189 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) 1190 max_ibs[i] = amdgpu_ring_max_ibs(i); 1191 1192 return copy_to_user(out, max_ibs, 1193 min((size_t)size, sizeof(max_ibs))) ? -EFAULT : 0; 1194 } 1195 default: 1196 DRM_DEBUG_KMS("Invalid request %d\n", info->query); 1197 return -EINVAL; 1198 } 1199 return 0; 1200 } 1201 1202 1203 /* 1204 * Outdated mess for old drm with Xorg being in charge (void function now). 1205 */ 1206 /** 1207 * amdgpu_driver_lastclose_kms - drm callback for last close 1208 * 1209 * @dev: drm dev pointer 1210 * 1211 * Switch vga_switcheroo state after last close (all asics). 1212 */ 1213 void amdgpu_driver_lastclose_kms(struct drm_device *dev) 1214 { 1215 drm_fb_helper_lastclose(dev); 1216 vga_switcheroo_process_delayed_switch(); 1217 } 1218 1219 /** 1220 * amdgpu_driver_open_kms - drm callback for open 1221 * 1222 * @dev: drm dev pointer 1223 * @file_priv: drm file 1224 * 1225 * On device open, init vm on cayman+ (all asics). 1226 * Returns 0 on success, error on failure. 1227 */ 1228 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 1229 { 1230 struct amdgpu_device *adev = drm_to_adev(dev); 1231 struct amdgpu_fpriv *fpriv; 1232 int r, pasid; 1233 1234 /* Ensure IB tests are run on ring */ 1235 flush_delayed_work(&adev->delayed_init_work); 1236 1237 1238 if (amdgpu_ras_intr_triggered()) { 1239 DRM_ERROR("RAS Intr triggered, device disabled!!"); 1240 return -EHWPOISON; 1241 } 1242 1243 file_priv->driver_priv = NULL; 1244 1245 r = pm_runtime_get_sync(dev->dev); 1246 if (r < 0) 1247 goto pm_put; 1248 1249 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 1250 if (unlikely(!fpriv)) { 1251 r = -ENOMEM; 1252 goto out_suspend; 1253 } 1254 1255 pasid = amdgpu_pasid_alloc(16); 1256 if (pasid < 0) { 1257 dev_warn(adev->dev, "No more PASIDs available!"); 1258 pasid = 0; 1259 } 1260 1261 r = amdgpu_xcp_open_device(adev, fpriv, file_priv); 1262 if (r) 1263 goto error_pasid; 1264 1265 r = amdgpu_vm_init(adev, &fpriv->vm, fpriv->xcp_id); 1266 if (r) 1267 goto error_pasid; 1268 1269 r = amdgpu_vm_set_pasid(adev, &fpriv->vm, pasid); 1270 if (r) 1271 goto error_vm; 1272 1273 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL); 1274 if (!fpriv->prt_va) { 1275 r = -ENOMEM; 1276 goto error_vm; 1277 } 1278 1279 if (adev->gfx.mcbp) { 1280 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK; 1281 1282 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj, 1283 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE); 1284 if (r) 1285 goto error_vm; 1286 } 1287 1288 mutex_init(&fpriv->bo_list_lock); 1289 idr_init_base(&fpriv->bo_list_handles, 1); 1290 1291 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr, adev); 1292 1293 file_priv->driver_priv = fpriv; 1294 goto out_suspend; 1295 1296 error_vm: 1297 amdgpu_vm_fini(adev, &fpriv->vm); 1298 1299 error_pasid: 1300 if (pasid) { 1301 amdgpu_pasid_free(pasid); 1302 amdgpu_vm_set_pasid(adev, &fpriv->vm, 0); 1303 } 1304 1305 kfree(fpriv); 1306 1307 out_suspend: 1308 pm_runtime_mark_last_busy(dev->dev); 1309 pm_put: 1310 pm_runtime_put_autosuspend(dev->dev); 1311 1312 return r; 1313 } 1314 1315 /** 1316 * amdgpu_driver_postclose_kms - drm callback for post close 1317 * 1318 * @dev: drm dev pointer 1319 * @file_priv: drm file 1320 * 1321 * On device post close, tear down vm on cayman+ (all asics). 1322 */ 1323 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1324 struct drm_file *file_priv) 1325 { 1326 struct amdgpu_device *adev = drm_to_adev(dev); 1327 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1328 struct amdgpu_bo_list *list; 1329 struct amdgpu_bo *pd; 1330 u32 pasid; 1331 int handle; 1332 1333 if (!fpriv) 1334 return; 1335 1336 pm_runtime_get_sync(dev->dev); 1337 1338 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL) 1339 amdgpu_uvd_free_handles(adev, file_priv); 1340 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL) 1341 amdgpu_vce_free_handles(adev, file_priv); 1342 1343 if (fpriv->csa_va) { 1344 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK; 1345 1346 WARN_ON(amdgpu_unmap_static_csa(adev, &fpriv->vm, adev->virt.csa_obj, 1347 fpriv->csa_va, csa_addr)); 1348 fpriv->csa_va = NULL; 1349 } 1350 1351 pasid = fpriv->vm.pasid; 1352 pd = amdgpu_bo_ref(fpriv->vm.root.bo); 1353 if (!WARN_ON(amdgpu_bo_reserve(pd, true))) { 1354 amdgpu_vm_bo_del(adev, fpriv->prt_va); 1355 amdgpu_bo_unreserve(pd); 1356 } 1357 1358 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); 1359 amdgpu_vm_fini(adev, &fpriv->vm); 1360 1361 if (pasid) 1362 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid); 1363 amdgpu_bo_unref(&pd); 1364 1365 idr_for_each_entry(&fpriv->bo_list_handles, list, handle) 1366 amdgpu_bo_list_put(list); 1367 1368 idr_destroy(&fpriv->bo_list_handles); 1369 mutex_destroy(&fpriv->bo_list_lock); 1370 1371 kfree(fpriv); 1372 file_priv->driver_priv = NULL; 1373 1374 pm_runtime_mark_last_busy(dev->dev); 1375 pm_runtime_put_autosuspend(dev->dev); 1376 } 1377 1378 1379 void amdgpu_driver_release_kms(struct drm_device *dev) 1380 { 1381 struct amdgpu_device *adev = drm_to_adev(dev); 1382 1383 amdgpu_device_fini_sw(adev); 1384 pci_set_drvdata(adev->pdev, NULL); 1385 } 1386 1387 /* 1388 * VBlank related functions. 1389 */ 1390 /** 1391 * amdgpu_get_vblank_counter_kms - get frame count 1392 * 1393 * @crtc: crtc to get the frame count from 1394 * 1395 * Gets the frame count on the requested crtc (all asics). 1396 * Returns frame count on success, -EINVAL on failure. 1397 */ 1398 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc) 1399 { 1400 struct drm_device *dev = crtc->dev; 1401 unsigned int pipe = crtc->index; 1402 struct amdgpu_device *adev = drm_to_adev(dev); 1403 int vpos, hpos, stat; 1404 u32 count; 1405 1406 if (pipe >= adev->mode_info.num_crtc) { 1407 DRM_ERROR("Invalid crtc %u\n", pipe); 1408 return -EINVAL; 1409 } 1410 1411 /* The hw increments its frame counter at start of vsync, not at start 1412 * of vblank, as is required by DRM core vblank counter handling. 1413 * Cook the hw count here to make it appear to the caller as if it 1414 * incremented at start of vblank. We measure distance to start of 1415 * vblank in vpos. vpos therefore will be >= 0 between start of vblank 1416 * and start of vsync, so vpos >= 0 means to bump the hw frame counter 1417 * result by 1 to give the proper appearance to caller. 1418 */ 1419 if (adev->mode_info.crtcs[pipe]) { 1420 /* Repeat readout if needed to provide stable result if 1421 * we cross start of vsync during the queries. 1422 */ 1423 do { 1424 count = amdgpu_display_vblank_get_counter(adev, pipe); 1425 /* Ask amdgpu_display_get_crtc_scanoutpos to return 1426 * vpos as distance to start of vblank, instead of 1427 * regular vertical scanout pos. 1428 */ 1429 stat = amdgpu_display_get_crtc_scanoutpos( 1430 dev, pipe, GET_DISTANCE_TO_VBLANKSTART, 1431 &vpos, &hpos, NULL, NULL, 1432 &adev->mode_info.crtcs[pipe]->base.hwmode); 1433 } while (count != amdgpu_display_vblank_get_counter(adev, pipe)); 1434 1435 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 1436 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 1437 DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 1438 } else { 1439 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", 1440 pipe, vpos); 1441 1442 /* Bump counter if we are at >= leading edge of vblank, 1443 * but before vsync where vpos would turn negative and 1444 * the hw counter really increments. 1445 */ 1446 if (vpos >= 0) 1447 count++; 1448 } 1449 } else { 1450 /* Fallback to use value as is. */ 1451 count = amdgpu_display_vblank_get_counter(adev, pipe); 1452 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 1453 } 1454 1455 return count; 1456 } 1457 1458 /** 1459 * amdgpu_enable_vblank_kms - enable vblank interrupt 1460 * 1461 * @crtc: crtc to enable vblank interrupt for 1462 * 1463 * Enable the interrupt on the requested crtc (all asics). 1464 * Returns 0 on success, -EINVAL on failure. 1465 */ 1466 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc) 1467 { 1468 struct drm_device *dev = crtc->dev; 1469 unsigned int pipe = crtc->index; 1470 struct amdgpu_device *adev = drm_to_adev(dev); 1471 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1472 1473 return amdgpu_irq_get(adev, &adev->crtc_irq, idx); 1474 } 1475 1476 /** 1477 * amdgpu_disable_vblank_kms - disable vblank interrupt 1478 * 1479 * @crtc: crtc to disable vblank interrupt for 1480 * 1481 * Disable the interrupt on the requested crtc (all asics). 1482 */ 1483 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc) 1484 { 1485 struct drm_device *dev = crtc->dev; 1486 unsigned int pipe = crtc->index; 1487 struct amdgpu_device *adev = drm_to_adev(dev); 1488 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1489 1490 amdgpu_irq_put(adev, &adev->crtc_irq, idx); 1491 } 1492 1493 /* 1494 * Debugfs info 1495 */ 1496 #if defined(CONFIG_DEBUG_FS) 1497 1498 static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused) 1499 { 1500 struct amdgpu_device *adev = m->private; 1501 struct drm_amdgpu_info_firmware fw_info; 1502 struct drm_amdgpu_query_fw query_fw; 1503 struct atom_context *ctx = adev->mode_info.atom_context; 1504 uint8_t smu_program, smu_major, smu_minor, smu_debug; 1505 int ret, i; 1506 1507 static const char *ta_fw_name[TA_FW_TYPE_MAX_INDEX] = { 1508 #define TA_FW_NAME(type)[TA_FW_TYPE_PSP_##type] = #type 1509 TA_FW_NAME(XGMI), 1510 TA_FW_NAME(RAS), 1511 TA_FW_NAME(HDCP), 1512 TA_FW_NAME(DTM), 1513 TA_FW_NAME(RAP), 1514 TA_FW_NAME(SECUREDISPLAY), 1515 #undef TA_FW_NAME 1516 }; 1517 1518 /* VCE */ 1519 query_fw.fw_type = AMDGPU_INFO_FW_VCE; 1520 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1521 if (ret) 1522 return ret; 1523 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n", 1524 fw_info.feature, fw_info.ver); 1525 1526 /* UVD */ 1527 query_fw.fw_type = AMDGPU_INFO_FW_UVD; 1528 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1529 if (ret) 1530 return ret; 1531 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n", 1532 fw_info.feature, fw_info.ver); 1533 1534 /* GMC */ 1535 query_fw.fw_type = AMDGPU_INFO_FW_GMC; 1536 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1537 if (ret) 1538 return ret; 1539 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n", 1540 fw_info.feature, fw_info.ver); 1541 1542 /* ME */ 1543 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME; 1544 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1545 if (ret) 1546 return ret; 1547 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n", 1548 fw_info.feature, fw_info.ver); 1549 1550 /* PFP */ 1551 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP; 1552 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1553 if (ret) 1554 return ret; 1555 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n", 1556 fw_info.feature, fw_info.ver); 1557 1558 /* CE */ 1559 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE; 1560 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1561 if (ret) 1562 return ret; 1563 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n", 1564 fw_info.feature, fw_info.ver); 1565 1566 /* RLC */ 1567 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC; 1568 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1569 if (ret) 1570 return ret; 1571 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n", 1572 fw_info.feature, fw_info.ver); 1573 1574 /* RLC SAVE RESTORE LIST CNTL */ 1575 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL; 1576 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1577 if (ret) 1578 return ret; 1579 seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n", 1580 fw_info.feature, fw_info.ver); 1581 1582 /* RLC SAVE RESTORE LIST GPM MEM */ 1583 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM; 1584 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1585 if (ret) 1586 return ret; 1587 seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n", 1588 fw_info.feature, fw_info.ver); 1589 1590 /* RLC SAVE RESTORE LIST SRM MEM */ 1591 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM; 1592 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1593 if (ret) 1594 return ret; 1595 seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n", 1596 fw_info.feature, fw_info.ver); 1597 1598 /* RLCP */ 1599 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCP; 1600 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1601 if (ret) 1602 return ret; 1603 seq_printf(m, "RLCP feature version: %u, firmware version: 0x%08x\n", 1604 fw_info.feature, fw_info.ver); 1605 1606 /* RLCV */ 1607 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCV; 1608 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1609 if (ret) 1610 return ret; 1611 seq_printf(m, "RLCV feature version: %u, firmware version: 0x%08x\n", 1612 fw_info.feature, fw_info.ver); 1613 1614 /* MEC */ 1615 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC; 1616 query_fw.index = 0; 1617 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1618 if (ret) 1619 return ret; 1620 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n", 1621 fw_info.feature, fw_info.ver); 1622 1623 /* MEC2 */ 1624 if (adev->gfx.mec2_fw) { 1625 query_fw.index = 1; 1626 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1627 if (ret) 1628 return ret; 1629 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n", 1630 fw_info.feature, fw_info.ver); 1631 } 1632 1633 /* IMU */ 1634 query_fw.fw_type = AMDGPU_INFO_FW_IMU; 1635 query_fw.index = 0; 1636 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1637 if (ret) 1638 return ret; 1639 seq_printf(m, "IMU feature version: %u, firmware version: 0x%08x\n", 1640 fw_info.feature, fw_info.ver); 1641 1642 /* PSP SOS */ 1643 query_fw.fw_type = AMDGPU_INFO_FW_SOS; 1644 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1645 if (ret) 1646 return ret; 1647 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n", 1648 fw_info.feature, fw_info.ver); 1649 1650 1651 /* PSP ASD */ 1652 query_fw.fw_type = AMDGPU_INFO_FW_ASD; 1653 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1654 if (ret) 1655 return ret; 1656 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n", 1657 fw_info.feature, fw_info.ver); 1658 1659 query_fw.fw_type = AMDGPU_INFO_FW_TA; 1660 for (i = TA_FW_TYPE_PSP_XGMI; i < TA_FW_TYPE_MAX_INDEX; i++) { 1661 query_fw.index = i; 1662 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1663 if (ret) 1664 continue; 1665 1666 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n", 1667 ta_fw_name[i], fw_info.feature, fw_info.ver); 1668 } 1669 1670 /* SMC */ 1671 query_fw.fw_type = AMDGPU_INFO_FW_SMC; 1672 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1673 if (ret) 1674 return ret; 1675 smu_program = (fw_info.ver >> 24) & 0xff; 1676 smu_major = (fw_info.ver >> 16) & 0xff; 1677 smu_minor = (fw_info.ver >> 8) & 0xff; 1678 smu_debug = (fw_info.ver >> 0) & 0xff; 1679 seq_printf(m, "SMC feature version: %u, program: %d, firmware version: 0x%08x (%d.%d.%d)\n", 1680 fw_info.feature, smu_program, fw_info.ver, smu_major, smu_minor, smu_debug); 1681 1682 /* SDMA */ 1683 query_fw.fw_type = AMDGPU_INFO_FW_SDMA; 1684 for (i = 0; i < adev->sdma.num_instances; i++) { 1685 query_fw.index = i; 1686 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1687 if (ret) 1688 return ret; 1689 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n", 1690 i, fw_info.feature, fw_info.ver); 1691 } 1692 1693 /* VCN */ 1694 query_fw.fw_type = AMDGPU_INFO_FW_VCN; 1695 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1696 if (ret) 1697 return ret; 1698 seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n", 1699 fw_info.feature, fw_info.ver); 1700 1701 /* DMCU */ 1702 query_fw.fw_type = AMDGPU_INFO_FW_DMCU; 1703 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1704 if (ret) 1705 return ret; 1706 seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n", 1707 fw_info.feature, fw_info.ver); 1708 1709 /* DMCUB */ 1710 query_fw.fw_type = AMDGPU_INFO_FW_DMCUB; 1711 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1712 if (ret) 1713 return ret; 1714 seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n", 1715 fw_info.feature, fw_info.ver); 1716 1717 /* TOC */ 1718 query_fw.fw_type = AMDGPU_INFO_FW_TOC; 1719 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1720 if (ret) 1721 return ret; 1722 seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n", 1723 fw_info.feature, fw_info.ver); 1724 1725 /* CAP */ 1726 if (adev->psp.cap_fw) { 1727 query_fw.fw_type = AMDGPU_INFO_FW_CAP; 1728 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1729 if (ret) 1730 return ret; 1731 seq_printf(m, "CAP feature version: %u, firmware version: 0x%08x\n", 1732 fw_info.feature, fw_info.ver); 1733 } 1734 1735 /* MES_KIQ */ 1736 query_fw.fw_type = AMDGPU_INFO_FW_MES_KIQ; 1737 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1738 if (ret) 1739 return ret; 1740 seq_printf(m, "MES_KIQ feature version: %u, firmware version: 0x%08x\n", 1741 fw_info.feature, fw_info.ver); 1742 1743 /* MES */ 1744 query_fw.fw_type = AMDGPU_INFO_FW_MES; 1745 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1746 if (ret) 1747 return ret; 1748 seq_printf(m, "MES feature version: %u, firmware version: 0x%08x\n", 1749 fw_info.feature, fw_info.ver); 1750 1751 /* VPE */ 1752 query_fw.fw_type = AMDGPU_INFO_FW_VPE; 1753 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1754 if (ret) 1755 return ret; 1756 seq_printf(m, "VPE feature version: %u, firmware version: 0x%08x\n", 1757 fw_info.feature, fw_info.ver); 1758 1759 seq_printf(m, "VBIOS version: %s\n", ctx->vbios_pn); 1760 1761 return 0; 1762 } 1763 1764 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_firmware_info); 1765 1766 #endif 1767 1768 void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev) 1769 { 1770 #if defined(CONFIG_DEBUG_FS) 1771 struct drm_minor *minor = adev_to_drm(adev)->primary; 1772 struct dentry *root = minor->debugfs_root; 1773 1774 debugfs_create_file("amdgpu_firmware_info", 0444, root, 1775 adev, &amdgpu_debugfs_firmware_info_fops); 1776 1777 #endif 1778 } 1779