1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include "amdgpu.h" 30 #include <drm/amdgpu_drm.h> 31 #include <drm/drm_drv.h> 32 #include <drm/drm_fb_helper.h> 33 #include "amdgpu_uvd.h" 34 #include "amdgpu_vce.h" 35 #include "atom.h" 36 37 #include <linux/vga_switcheroo.h> 38 #include <linux/slab.h> 39 #include <linux/uaccess.h> 40 #include <linux/pci.h> 41 #include <linux/pm_runtime.h> 42 #include "amdgpu_amdkfd.h" 43 #include "amdgpu_gem.h" 44 #include "amdgpu_display.h" 45 #include "amdgpu_ras.h" 46 #include "amd_pcie.h" 47 48 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev) 49 { 50 struct amdgpu_gpu_instance *gpu_instance; 51 int i; 52 53 mutex_lock(&mgpu_info.mutex); 54 55 for (i = 0; i < mgpu_info.num_gpu; i++) { 56 gpu_instance = &(mgpu_info.gpu_ins[i]); 57 if (gpu_instance->adev == adev) { 58 mgpu_info.gpu_ins[i] = 59 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1]; 60 mgpu_info.num_gpu--; 61 if (adev->flags & AMD_IS_APU) 62 mgpu_info.num_apu--; 63 else 64 mgpu_info.num_dgpu--; 65 break; 66 } 67 } 68 69 mutex_unlock(&mgpu_info.mutex); 70 } 71 72 /** 73 * amdgpu_driver_unload_kms - Main unload function for KMS. 74 * 75 * @dev: drm dev pointer 76 * 77 * This is the main unload function for KMS (all asics). 78 * Returns 0 on success. 79 */ 80 void amdgpu_driver_unload_kms(struct drm_device *dev) 81 { 82 struct amdgpu_device *adev = drm_to_adev(dev); 83 84 if (adev == NULL) 85 return; 86 87 amdgpu_unregister_gpu_instance(adev); 88 89 if (adev->rmmio == NULL) 90 return; 91 92 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_UNLOAD)) 93 DRM_WARN("smart shift update failed\n"); 94 95 amdgpu_acpi_fini(adev); 96 amdgpu_device_fini_hw(adev); 97 } 98 99 void amdgpu_register_gpu_instance(struct amdgpu_device *adev) 100 { 101 struct amdgpu_gpu_instance *gpu_instance; 102 103 mutex_lock(&mgpu_info.mutex); 104 105 if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) { 106 DRM_ERROR("Cannot register more gpu instance\n"); 107 mutex_unlock(&mgpu_info.mutex); 108 return; 109 } 110 111 gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]); 112 gpu_instance->adev = adev; 113 gpu_instance->mgpu_fan_enabled = 0; 114 115 mgpu_info.num_gpu++; 116 if (adev->flags & AMD_IS_APU) 117 mgpu_info.num_apu++; 118 else 119 mgpu_info.num_dgpu++; 120 121 mutex_unlock(&mgpu_info.mutex); 122 } 123 124 /** 125 * amdgpu_driver_load_kms - Main load function for KMS. 126 * 127 * @adev: pointer to struct amdgpu_device 128 * @flags: device flags 129 * 130 * This is the main load function for KMS (all asics). 131 * Returns 0 on success, error on failure. 132 */ 133 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags) 134 { 135 struct drm_device *dev; 136 int bamaco_support = 0; 137 int r, acpi_status; 138 139 dev = adev_to_drm(adev); 140 141 /* amdgpu_device_init should report only fatal error 142 * like memory allocation failure or iomapping failure, 143 * or memory manager initialization failure, it must 144 * properly initialize the GPU MC controller and permit 145 * VRAM allocation 146 */ 147 r = amdgpu_device_init(adev, flags); 148 if (r) { 149 dev_err(dev->dev, "Fatal error during GPU init\n"); 150 goto out; 151 } 152 153 adev->pm.rpm_mode = AMDGPU_RUNPM_NONE; 154 if (amdgpu_device_supports_px(dev) && 155 (amdgpu_runtime_pm != 0)) { /* enable PX as runtime mode */ 156 adev->pm.rpm_mode = AMDGPU_RUNPM_PX; 157 dev_info(adev->dev, "Using ATPX for runtime pm\n"); 158 } else if (amdgpu_device_supports_boco(dev) && 159 (amdgpu_runtime_pm != 0)) { /* enable boco as runtime mode */ 160 adev->pm.rpm_mode = AMDGPU_RUNPM_BOCO; 161 dev_info(adev->dev, "Using BOCO for runtime pm\n"); 162 } else if (amdgpu_runtime_pm != 0) { 163 bamaco_support = amdgpu_device_supports_baco(dev); 164 165 if (!bamaco_support) 166 goto no_runtime_pm; 167 168 switch (adev->asic_type) { 169 case CHIP_VEGA20: 170 case CHIP_ARCTURUS: 171 /* enable BACO as runpm mode if runpm=1 */ 172 if (amdgpu_runtime_pm > 0) 173 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO; 174 break; 175 case CHIP_VEGA10: 176 /* enable BACO as runpm mode if noretry=0 */ 177 if (!adev->gmc.noretry) 178 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO; 179 break; 180 default: 181 /* enable BACO as runpm mode on CI+ */ 182 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO; 183 break; 184 } 185 186 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) { 187 if (bamaco_support & MACO_SUPPORT) { 188 adev->pm.rpm_mode = AMDGPU_RUNPM_BAMACO; 189 dev_info(adev->dev, "Using BAMACO for runtime pm\n"); 190 } else { 191 dev_info(adev->dev, "Using BACO for runtime pm\n"); 192 } 193 } 194 } 195 196 no_runtime_pm: 197 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) 198 dev_info(adev->dev, "NO pm mode for runtime pm\n"); 199 200 /* Call ACPI methods: require modeset init 201 * but failure is not fatal 202 */ 203 204 acpi_status = amdgpu_acpi_init(adev); 205 if (acpi_status) 206 dev_dbg(dev->dev, "Error during ACPI methods call\n"); 207 208 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_LOAD)) 209 DRM_WARN("smart shift update failed\n"); 210 211 out: 212 if (r) 213 amdgpu_driver_unload_kms(dev); 214 215 return r; 216 } 217 218 static enum amd_ip_block_type 219 amdgpu_ip_get_block_type(struct amdgpu_device *adev, uint32_t ip) 220 { 221 enum amd_ip_block_type type; 222 223 switch (ip) { 224 case AMDGPU_HW_IP_GFX: 225 type = AMD_IP_BLOCK_TYPE_GFX; 226 break; 227 case AMDGPU_HW_IP_COMPUTE: 228 type = AMD_IP_BLOCK_TYPE_GFX; 229 break; 230 case AMDGPU_HW_IP_DMA: 231 type = AMD_IP_BLOCK_TYPE_SDMA; 232 break; 233 case AMDGPU_HW_IP_UVD: 234 case AMDGPU_HW_IP_UVD_ENC: 235 type = AMD_IP_BLOCK_TYPE_UVD; 236 break; 237 case AMDGPU_HW_IP_VCE: 238 type = AMD_IP_BLOCK_TYPE_VCE; 239 break; 240 case AMDGPU_HW_IP_VCN_DEC: 241 case AMDGPU_HW_IP_VCN_ENC: 242 type = AMD_IP_BLOCK_TYPE_VCN; 243 break; 244 case AMDGPU_HW_IP_VCN_JPEG: 245 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 246 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 247 break; 248 default: 249 type = AMD_IP_BLOCK_TYPE_NUM; 250 break; 251 } 252 253 return type; 254 } 255 256 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, 257 struct drm_amdgpu_query_fw *query_fw, 258 struct amdgpu_device *adev) 259 { 260 switch (query_fw->fw_type) { 261 case AMDGPU_INFO_FW_VCE: 262 fw_info->ver = adev->vce.fw_version; 263 fw_info->feature = adev->vce.fb_version; 264 break; 265 case AMDGPU_INFO_FW_UVD: 266 fw_info->ver = adev->uvd.fw_version; 267 fw_info->feature = 0; 268 break; 269 case AMDGPU_INFO_FW_VCN: 270 fw_info->ver = adev->vcn.fw_version; 271 fw_info->feature = 0; 272 break; 273 case AMDGPU_INFO_FW_GMC: 274 fw_info->ver = adev->gmc.fw_version; 275 fw_info->feature = 0; 276 break; 277 case AMDGPU_INFO_FW_GFX_ME: 278 fw_info->ver = adev->gfx.me_fw_version; 279 fw_info->feature = adev->gfx.me_feature_version; 280 break; 281 case AMDGPU_INFO_FW_GFX_PFP: 282 fw_info->ver = adev->gfx.pfp_fw_version; 283 fw_info->feature = adev->gfx.pfp_feature_version; 284 break; 285 case AMDGPU_INFO_FW_GFX_CE: 286 fw_info->ver = adev->gfx.ce_fw_version; 287 fw_info->feature = adev->gfx.ce_feature_version; 288 break; 289 case AMDGPU_INFO_FW_GFX_RLC: 290 fw_info->ver = adev->gfx.rlc_fw_version; 291 fw_info->feature = adev->gfx.rlc_feature_version; 292 break; 293 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL: 294 fw_info->ver = adev->gfx.rlc_srlc_fw_version; 295 fw_info->feature = adev->gfx.rlc_srlc_feature_version; 296 break; 297 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM: 298 fw_info->ver = adev->gfx.rlc_srlg_fw_version; 299 fw_info->feature = adev->gfx.rlc_srlg_feature_version; 300 break; 301 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM: 302 fw_info->ver = adev->gfx.rlc_srls_fw_version; 303 fw_info->feature = adev->gfx.rlc_srls_feature_version; 304 break; 305 case AMDGPU_INFO_FW_GFX_RLCP: 306 fw_info->ver = adev->gfx.rlcp_ucode_version; 307 fw_info->feature = adev->gfx.rlcp_ucode_feature_version; 308 break; 309 case AMDGPU_INFO_FW_GFX_RLCV: 310 fw_info->ver = adev->gfx.rlcv_ucode_version; 311 fw_info->feature = adev->gfx.rlcv_ucode_feature_version; 312 break; 313 case AMDGPU_INFO_FW_GFX_MEC: 314 if (query_fw->index == 0) { 315 fw_info->ver = adev->gfx.mec_fw_version; 316 fw_info->feature = adev->gfx.mec_feature_version; 317 } else if (query_fw->index == 1) { 318 fw_info->ver = adev->gfx.mec2_fw_version; 319 fw_info->feature = adev->gfx.mec2_feature_version; 320 } else 321 return -EINVAL; 322 break; 323 case AMDGPU_INFO_FW_SMC: 324 fw_info->ver = adev->pm.fw_version; 325 fw_info->feature = 0; 326 break; 327 case AMDGPU_INFO_FW_TA: 328 switch (query_fw->index) { 329 case TA_FW_TYPE_PSP_XGMI: 330 fw_info->ver = adev->psp.xgmi_context.context.bin_desc.fw_version; 331 fw_info->feature = adev->psp.xgmi_context.context 332 .bin_desc.feature_version; 333 break; 334 case TA_FW_TYPE_PSP_RAS: 335 fw_info->ver = adev->psp.ras_context.context.bin_desc.fw_version; 336 fw_info->feature = adev->psp.ras_context.context 337 .bin_desc.feature_version; 338 break; 339 case TA_FW_TYPE_PSP_HDCP: 340 fw_info->ver = adev->psp.hdcp_context.context.bin_desc.fw_version; 341 fw_info->feature = adev->psp.hdcp_context.context 342 .bin_desc.feature_version; 343 break; 344 case TA_FW_TYPE_PSP_DTM: 345 fw_info->ver = adev->psp.dtm_context.context.bin_desc.fw_version; 346 fw_info->feature = adev->psp.dtm_context.context 347 .bin_desc.feature_version; 348 break; 349 case TA_FW_TYPE_PSP_RAP: 350 fw_info->ver = adev->psp.rap_context.context.bin_desc.fw_version; 351 fw_info->feature = adev->psp.rap_context.context 352 .bin_desc.feature_version; 353 break; 354 case TA_FW_TYPE_PSP_SECUREDISPLAY: 355 fw_info->ver = adev->psp.securedisplay_context.context.bin_desc.fw_version; 356 fw_info->feature = 357 adev->psp.securedisplay_context.context.bin_desc 358 .feature_version; 359 break; 360 default: 361 return -EINVAL; 362 } 363 break; 364 case AMDGPU_INFO_FW_SDMA: 365 if (query_fw->index >= adev->sdma.num_instances) 366 return -EINVAL; 367 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version; 368 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version; 369 break; 370 case AMDGPU_INFO_FW_SOS: 371 fw_info->ver = adev->psp.sos.fw_version; 372 fw_info->feature = adev->psp.sos.feature_version; 373 break; 374 case AMDGPU_INFO_FW_ASD: 375 fw_info->ver = adev->psp.asd_context.bin_desc.fw_version; 376 fw_info->feature = adev->psp.asd_context.bin_desc.feature_version; 377 break; 378 case AMDGPU_INFO_FW_DMCU: 379 fw_info->ver = adev->dm.dmcu_fw_version; 380 fw_info->feature = 0; 381 break; 382 case AMDGPU_INFO_FW_DMCUB: 383 fw_info->ver = adev->dm.dmcub_fw_version; 384 fw_info->feature = 0; 385 break; 386 case AMDGPU_INFO_FW_TOC: 387 fw_info->ver = adev->psp.toc.fw_version; 388 fw_info->feature = adev->psp.toc.feature_version; 389 break; 390 case AMDGPU_INFO_FW_CAP: 391 fw_info->ver = adev->psp.cap_fw_version; 392 fw_info->feature = adev->psp.cap_feature_version; 393 break; 394 case AMDGPU_INFO_FW_MES_KIQ: 395 fw_info->ver = adev->mes.kiq_version & AMDGPU_MES_VERSION_MASK; 396 fw_info->feature = (adev->mes.kiq_version & AMDGPU_MES_FEAT_VERSION_MASK) 397 >> AMDGPU_MES_FEAT_VERSION_SHIFT; 398 break; 399 case AMDGPU_INFO_FW_MES: 400 fw_info->ver = adev->mes.sched_version & AMDGPU_MES_VERSION_MASK; 401 fw_info->feature = (adev->mes.sched_version & AMDGPU_MES_FEAT_VERSION_MASK) 402 >> AMDGPU_MES_FEAT_VERSION_SHIFT; 403 break; 404 case AMDGPU_INFO_FW_IMU: 405 fw_info->ver = adev->gfx.imu_fw_version; 406 fw_info->feature = 0; 407 break; 408 case AMDGPU_INFO_FW_VPE: 409 fw_info->ver = adev->vpe.fw_version; 410 fw_info->feature = adev->vpe.feature_version; 411 break; 412 default: 413 return -EINVAL; 414 } 415 return 0; 416 } 417 418 static int amdgpu_hw_ip_info(struct amdgpu_device *adev, 419 struct drm_amdgpu_info *info, 420 struct drm_amdgpu_info_hw_ip *result) 421 { 422 uint32_t ib_start_alignment = 0; 423 uint32_t ib_size_alignment = 0; 424 enum amd_ip_block_type type; 425 unsigned int num_rings = 0; 426 unsigned int i, j; 427 428 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 429 return -EINVAL; 430 431 switch (info->query_hw_ip.type) { 432 case AMDGPU_HW_IP_GFX: 433 type = AMD_IP_BLOCK_TYPE_GFX; 434 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 435 if (adev->gfx.gfx_ring[i].sched.ready) 436 ++num_rings; 437 ib_start_alignment = 32; 438 ib_size_alignment = 32; 439 break; 440 case AMDGPU_HW_IP_COMPUTE: 441 type = AMD_IP_BLOCK_TYPE_GFX; 442 for (i = 0; i < adev->gfx.num_compute_rings; i++) 443 if (adev->gfx.compute_ring[i].sched.ready) 444 ++num_rings; 445 ib_start_alignment = 32; 446 ib_size_alignment = 32; 447 break; 448 case AMDGPU_HW_IP_DMA: 449 type = AMD_IP_BLOCK_TYPE_SDMA; 450 for (i = 0; i < adev->sdma.num_instances; i++) 451 if (adev->sdma.instance[i].ring.sched.ready) 452 ++num_rings; 453 ib_start_alignment = 256; 454 ib_size_alignment = 4; 455 break; 456 case AMDGPU_HW_IP_UVD: 457 type = AMD_IP_BLOCK_TYPE_UVD; 458 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 459 if (adev->uvd.harvest_config & (1 << i)) 460 continue; 461 462 if (adev->uvd.inst[i].ring.sched.ready) 463 ++num_rings; 464 } 465 ib_start_alignment = 256; 466 ib_size_alignment = 64; 467 break; 468 case AMDGPU_HW_IP_VCE: 469 type = AMD_IP_BLOCK_TYPE_VCE; 470 for (i = 0; i < adev->vce.num_rings; i++) 471 if (adev->vce.ring[i].sched.ready) 472 ++num_rings; 473 ib_start_alignment = 256; 474 ib_size_alignment = 4; 475 break; 476 case AMDGPU_HW_IP_UVD_ENC: 477 type = AMD_IP_BLOCK_TYPE_UVD; 478 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 479 if (adev->uvd.harvest_config & (1 << i)) 480 continue; 481 482 for (j = 0; j < adev->uvd.num_enc_rings; j++) 483 if (adev->uvd.inst[i].ring_enc[j].sched.ready) 484 ++num_rings; 485 } 486 ib_start_alignment = 256; 487 ib_size_alignment = 4; 488 break; 489 case AMDGPU_HW_IP_VCN_DEC: 490 type = AMD_IP_BLOCK_TYPE_VCN; 491 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 492 if (adev->vcn.harvest_config & (1 << i)) 493 continue; 494 495 if (adev->vcn.inst[i].ring_dec.sched.ready) 496 ++num_rings; 497 } 498 ib_start_alignment = 256; 499 ib_size_alignment = 64; 500 break; 501 case AMDGPU_HW_IP_VCN_ENC: 502 type = AMD_IP_BLOCK_TYPE_VCN; 503 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 504 if (adev->vcn.harvest_config & (1 << i)) 505 continue; 506 507 for (j = 0; j < adev->vcn.num_enc_rings; j++) 508 if (adev->vcn.inst[i].ring_enc[j].sched.ready) 509 ++num_rings; 510 } 511 ib_start_alignment = 256; 512 ib_size_alignment = 4; 513 break; 514 case AMDGPU_HW_IP_VCN_JPEG: 515 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 516 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 517 518 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { 519 if (adev->jpeg.harvest_config & (1 << i)) 520 continue; 521 522 for (j = 0; j < adev->jpeg.num_jpeg_rings; j++) 523 if (adev->jpeg.inst[i].ring_dec[j].sched.ready) 524 ++num_rings; 525 } 526 ib_start_alignment = 256; 527 ib_size_alignment = 64; 528 break; 529 case AMDGPU_HW_IP_VPE: 530 type = AMD_IP_BLOCK_TYPE_VPE; 531 if (adev->vpe.ring.sched.ready) 532 ++num_rings; 533 ib_start_alignment = 256; 534 ib_size_alignment = 4; 535 break; 536 default: 537 return -EINVAL; 538 } 539 540 for (i = 0; i < adev->num_ip_blocks; i++) 541 if (adev->ip_blocks[i].version->type == type && 542 adev->ip_blocks[i].status.valid) 543 break; 544 545 if (i == adev->num_ip_blocks) 546 return 0; 547 548 num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type], 549 num_rings); 550 551 result->hw_ip_version_major = adev->ip_blocks[i].version->major; 552 result->hw_ip_version_minor = adev->ip_blocks[i].version->minor; 553 554 if (adev->asic_type >= CHIP_VEGA10) { 555 switch (type) { 556 case AMD_IP_BLOCK_TYPE_GFX: 557 result->ip_discovery_version = 558 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, GC_HWIP, 0)); 559 break; 560 case AMD_IP_BLOCK_TYPE_SDMA: 561 result->ip_discovery_version = 562 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, SDMA0_HWIP, 0)); 563 break; 564 case AMD_IP_BLOCK_TYPE_UVD: 565 case AMD_IP_BLOCK_TYPE_VCN: 566 case AMD_IP_BLOCK_TYPE_JPEG: 567 result->ip_discovery_version = 568 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, UVD_HWIP, 0)); 569 break; 570 case AMD_IP_BLOCK_TYPE_VCE: 571 result->ip_discovery_version = 572 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, VCE_HWIP, 0)); 573 break; 574 case AMD_IP_BLOCK_TYPE_VPE: 575 result->ip_discovery_version = 576 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, VPE_HWIP, 0)); 577 break; 578 default: 579 result->ip_discovery_version = 0; 580 break; 581 } 582 } else { 583 result->ip_discovery_version = 0; 584 } 585 result->capabilities_flags = 0; 586 result->available_rings = (1 << num_rings) - 1; 587 result->ib_start_alignment = ib_start_alignment; 588 result->ib_size_alignment = ib_size_alignment; 589 return 0; 590 } 591 592 /* 593 * Userspace get information ioctl 594 */ 595 /** 596 * amdgpu_info_ioctl - answer a device specific request. 597 * 598 * @dev: drm device pointer 599 * @data: request object 600 * @filp: drm filp 601 * 602 * This function is used to pass device specific parameters to the userspace 603 * drivers. Examples include: pci device id, pipeline parms, tiling params, 604 * etc. (all asics). 605 * Returns 0 on success, -EINVAL on failure. 606 */ 607 int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 608 { 609 struct amdgpu_device *adev = drm_to_adev(dev); 610 struct drm_amdgpu_info *info = data; 611 struct amdgpu_mode_info *minfo = &adev->mode_info; 612 void __user *out = (void __user *)(uintptr_t)info->return_pointer; 613 struct amdgpu_fpriv *fpriv; 614 struct amdgpu_ip_block *ip_block; 615 enum amd_ip_block_type type; 616 struct amdgpu_xcp *xcp; 617 u32 count, inst_mask; 618 uint32_t size = info->return_size; 619 struct drm_crtc *crtc; 620 uint32_t ui32 = 0; 621 uint64_t ui64 = 0; 622 int i, found, ret; 623 int ui32_size = sizeof(ui32); 624 625 if (!info->return_size || !info->return_pointer) 626 return -EINVAL; 627 628 switch (info->query) { 629 case AMDGPU_INFO_ACCEL_WORKING: 630 ui32 = adev->accel_working; 631 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 632 case AMDGPU_INFO_CRTC_FROM_ID: 633 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { 634 crtc = (struct drm_crtc *)minfo->crtcs[i]; 635 if (crtc && crtc->base.id == info->mode_crtc.id) { 636 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 637 638 ui32 = amdgpu_crtc->crtc_id; 639 found = 1; 640 break; 641 } 642 } 643 if (!found) { 644 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); 645 return -EINVAL; 646 } 647 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 648 case AMDGPU_INFO_HW_IP_INFO: { 649 struct drm_amdgpu_info_hw_ip ip = {}; 650 651 ret = amdgpu_hw_ip_info(adev, info, &ip); 652 if (ret) 653 return ret; 654 655 ret = copy_to_user(out, &ip, min_t(size_t, size, sizeof(ip))); 656 return ret ? -EFAULT : 0; 657 } 658 case AMDGPU_INFO_HW_IP_COUNT: { 659 fpriv = (struct amdgpu_fpriv *)filp->driver_priv; 660 type = amdgpu_ip_get_block_type(adev, info->query_hw_ip.type); 661 ip_block = amdgpu_device_ip_get_ip_block(adev, type); 662 663 if (!ip_block || !ip_block->status.valid) 664 return -EINVAL; 665 666 if (adev->xcp_mgr && adev->xcp_mgr->num_xcps > 0 && 667 fpriv->xcp_id >= 0 && fpriv->xcp_id < adev->xcp_mgr->num_xcps) { 668 xcp = &adev->xcp_mgr->xcp[fpriv->xcp_id]; 669 switch (type) { 670 case AMD_IP_BLOCK_TYPE_GFX: 671 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &inst_mask); 672 count = hweight32(inst_mask); 673 break; 674 case AMD_IP_BLOCK_TYPE_SDMA: 675 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_SDMA, &inst_mask); 676 count = hweight32(inst_mask); 677 break; 678 case AMD_IP_BLOCK_TYPE_JPEG: 679 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask); 680 count = hweight32(inst_mask) * adev->jpeg.num_jpeg_rings; 681 break; 682 case AMD_IP_BLOCK_TYPE_VCN: 683 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask); 684 count = hweight32(inst_mask); 685 break; 686 default: 687 return -EINVAL; 688 } 689 if (ret) 690 return ret; 691 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; 692 } 693 694 switch (type) { 695 case AMD_IP_BLOCK_TYPE_GFX: 696 case AMD_IP_BLOCK_TYPE_VCE: 697 count = 1; 698 break; 699 case AMD_IP_BLOCK_TYPE_SDMA: 700 count = adev->sdma.num_instances; 701 break; 702 case AMD_IP_BLOCK_TYPE_JPEG: 703 count = adev->jpeg.num_jpeg_inst * adev->jpeg.num_jpeg_rings; 704 break; 705 case AMD_IP_BLOCK_TYPE_VCN: 706 count = adev->vcn.num_vcn_inst; 707 break; 708 case AMD_IP_BLOCK_TYPE_UVD: 709 count = adev->uvd.num_uvd_inst; 710 break; 711 /* For all other IP block types not listed in the switch statement 712 * the ip status is valid here and the instance count is one. 713 */ 714 default: 715 count = 1; 716 break; 717 } 718 719 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; 720 } 721 case AMDGPU_INFO_TIMESTAMP: 722 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev); 723 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 724 case AMDGPU_INFO_FW_VERSION: { 725 struct drm_amdgpu_info_firmware fw_info; 726 727 /* We only support one instance of each IP block right now. */ 728 if (info->query_fw.ip_instance != 0) 729 return -EINVAL; 730 731 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev); 732 if (ret) 733 return ret; 734 735 return copy_to_user(out, &fw_info, 736 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0; 737 } 738 case AMDGPU_INFO_NUM_BYTES_MOVED: 739 ui64 = atomic64_read(&adev->num_bytes_moved); 740 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 741 case AMDGPU_INFO_NUM_EVICTIONS: 742 ui64 = atomic64_read(&adev->num_evictions); 743 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 744 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS: 745 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults); 746 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 747 case AMDGPU_INFO_VRAM_USAGE: 748 ui64 = ttm_resource_manager_usage(&adev->mman.vram_mgr.manager); 749 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 750 case AMDGPU_INFO_VIS_VRAM_USAGE: 751 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr); 752 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 753 case AMDGPU_INFO_GTT_USAGE: 754 ui64 = ttm_resource_manager_usage(&adev->mman.gtt_mgr.manager); 755 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 756 case AMDGPU_INFO_GDS_CONFIG: { 757 struct drm_amdgpu_info_gds gds_info; 758 759 memset(&gds_info, 0, sizeof(gds_info)); 760 gds_info.compute_partition_size = adev->gds.gds_size; 761 gds_info.gds_total_size = adev->gds.gds_size; 762 gds_info.gws_per_compute_partition = adev->gds.gws_size; 763 gds_info.oa_per_compute_partition = adev->gds.oa_size; 764 return copy_to_user(out, &gds_info, 765 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0; 766 } 767 case AMDGPU_INFO_VRAM_GTT: { 768 struct drm_amdgpu_info_vram_gtt vram_gtt; 769 770 vram_gtt.vram_size = adev->gmc.real_vram_size - 771 atomic64_read(&adev->vram_pin_size) - 772 AMDGPU_VM_RESERVED_VRAM; 773 vram_gtt.vram_cpu_accessible_size = 774 min(adev->gmc.visible_vram_size - 775 atomic64_read(&adev->visible_pin_size), 776 vram_gtt.vram_size); 777 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size; 778 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size); 779 return copy_to_user(out, &vram_gtt, 780 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; 781 } 782 case AMDGPU_INFO_MEMORY: { 783 struct drm_amdgpu_memory_info mem; 784 struct ttm_resource_manager *gtt_man = 785 &adev->mman.gtt_mgr.manager; 786 struct ttm_resource_manager *vram_man = 787 &adev->mman.vram_mgr.manager; 788 789 memset(&mem, 0, sizeof(mem)); 790 mem.vram.total_heap_size = adev->gmc.real_vram_size; 791 mem.vram.usable_heap_size = adev->gmc.real_vram_size - 792 atomic64_read(&adev->vram_pin_size) - 793 AMDGPU_VM_RESERVED_VRAM; 794 mem.vram.heap_usage = 795 ttm_resource_manager_usage(vram_man); 796 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4; 797 798 mem.cpu_accessible_vram.total_heap_size = 799 adev->gmc.visible_vram_size; 800 mem.cpu_accessible_vram.usable_heap_size = 801 min(adev->gmc.visible_vram_size - 802 atomic64_read(&adev->visible_pin_size), 803 mem.vram.usable_heap_size); 804 mem.cpu_accessible_vram.heap_usage = 805 amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr); 806 mem.cpu_accessible_vram.max_allocation = 807 mem.cpu_accessible_vram.usable_heap_size * 3 / 4; 808 809 mem.gtt.total_heap_size = gtt_man->size; 810 mem.gtt.usable_heap_size = mem.gtt.total_heap_size - 811 atomic64_read(&adev->gart_pin_size); 812 mem.gtt.heap_usage = ttm_resource_manager_usage(gtt_man); 813 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4; 814 815 return copy_to_user(out, &mem, 816 min((size_t)size, sizeof(mem))) 817 ? -EFAULT : 0; 818 } 819 case AMDGPU_INFO_READ_MMR_REG: { 820 unsigned int n, alloc_size; 821 uint32_t *regs; 822 unsigned int se_num = (info->read_mmr_reg.instance >> 823 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & 824 AMDGPU_INFO_MMR_SE_INDEX_MASK; 825 unsigned int sh_num = (info->read_mmr_reg.instance >> 826 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & 827 AMDGPU_INFO_MMR_SH_INDEX_MASK; 828 829 /* set full masks if the userspace set all bits 830 * in the bitfields 831 */ 832 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) 833 se_num = 0xffffffff; 834 else if (se_num >= AMDGPU_GFX_MAX_SE) 835 return -EINVAL; 836 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) 837 sh_num = 0xffffffff; 838 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE) 839 return -EINVAL; 840 841 if (info->read_mmr_reg.count > 128) 842 return -EINVAL; 843 844 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL); 845 if (!regs) 846 return -ENOMEM; 847 alloc_size = info->read_mmr_reg.count * sizeof(*regs); 848 849 amdgpu_gfx_off_ctrl(adev, false); 850 for (i = 0; i < info->read_mmr_reg.count; i++) { 851 if (amdgpu_asic_read_register(adev, se_num, sh_num, 852 info->read_mmr_reg.dword_offset + i, 853 ®s[i])) { 854 DRM_DEBUG_KMS("unallowed offset %#x\n", 855 info->read_mmr_reg.dword_offset + i); 856 kfree(regs); 857 amdgpu_gfx_off_ctrl(adev, true); 858 return -EFAULT; 859 } 860 } 861 amdgpu_gfx_off_ctrl(adev, true); 862 n = copy_to_user(out, regs, min(size, alloc_size)); 863 kfree(regs); 864 return n ? -EFAULT : 0; 865 } 866 case AMDGPU_INFO_DEV_INFO: { 867 struct drm_amdgpu_info_device *dev_info; 868 uint64_t vm_size; 869 uint32_t pcie_gen_mask; 870 871 dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL); 872 if (!dev_info) 873 return -ENOMEM; 874 875 dev_info->device_id = adev->pdev->device; 876 dev_info->chip_rev = adev->rev_id; 877 dev_info->external_rev = adev->external_rev_id; 878 dev_info->pci_rev = adev->pdev->revision; 879 dev_info->family = adev->family; 880 dev_info->num_shader_engines = adev->gfx.config.max_shader_engines; 881 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 882 /* return all clocks in KHz */ 883 dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; 884 if (adev->pm.dpm_enabled) { 885 dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10; 886 dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10; 887 dev_info->min_engine_clock = amdgpu_dpm_get_sclk(adev, true) * 10; 888 dev_info->min_memory_clock = amdgpu_dpm_get_mclk(adev, true) * 10; 889 } else { 890 dev_info->max_engine_clock = 891 dev_info->min_engine_clock = 892 adev->clock.default_sclk * 10; 893 dev_info->max_memory_clock = 894 dev_info->min_memory_clock = 895 adev->clock.default_mclk * 10; 896 } 897 dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; 898 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se * 899 adev->gfx.config.max_shader_engines; 900 dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; 901 dev_info->ids_flags = 0; 902 if (adev->flags & AMD_IS_APU) 903 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION; 904 if (adev->gfx.mcbp) 905 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION; 906 if (amdgpu_is_tmz(adev)) 907 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ; 908 if (adev->gfx.config.ta_cntl2_truncate_coord_mode) 909 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD; 910 911 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 912 vm_size -= AMDGPU_VA_RESERVED_TOP; 913 914 /* Older VCE FW versions are buggy and can handle only 40bits */ 915 if (adev->vce.fw_version && 916 adev->vce.fw_version < AMDGPU_VCE_FW_53_45) 917 vm_size = min(vm_size, 1ULL << 40); 918 919 dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_BOTTOM; 920 dev_info->virtual_address_max = 921 min(vm_size, AMDGPU_GMC_HOLE_START); 922 923 if (vm_size > AMDGPU_GMC_HOLE_START) { 924 dev_info->high_va_offset = AMDGPU_GMC_HOLE_END; 925 dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size; 926 } 927 dev_info->virtual_address_alignment = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 928 dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE; 929 dev_info->gart_page_size = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 930 dev_info->cu_active_number = adev->gfx.cu_info.number; 931 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; 932 dev_info->ce_ram_size = adev->gfx.ce_ram_size; 933 memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0], 934 sizeof(adev->gfx.cu_info.ao_cu_bitmap)); 935 memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], 936 sizeof(dev_info->cu_bitmap)); 937 dev_info->vram_type = adev->gmc.vram_type; 938 dev_info->vram_bit_width = adev->gmc.vram_width; 939 dev_info->vce_harvest_config = adev->vce.harvest_config; 940 dev_info->gc_double_offchip_lds_buf = 941 adev->gfx.config.double_offchip_lds_buf; 942 dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size; 943 dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs; 944 dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh; 945 dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches; 946 dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth; 947 dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth; 948 dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads; 949 950 if (adev->family >= AMDGPU_FAMILY_NV) 951 dev_info->pa_sc_tile_steering_override = 952 adev->gfx.config.pa_sc_tile_steering_override; 953 954 dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask; 955 956 /* Combine the chip gen mask with the platform (CPU/mobo) mask. */ 957 pcie_gen_mask = adev->pm.pcie_gen_mask & (adev->pm.pcie_gen_mask >> 16); 958 dev_info->pcie_gen = fls(pcie_gen_mask); 959 dev_info->pcie_num_lanes = 960 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 ? 32 : 961 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 ? 16 : 962 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 ? 12 : 963 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 ? 8 : 964 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 ? 4 : 965 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 ? 2 : 1; 966 967 dev_info->tcp_cache_size = adev->gfx.config.gc_tcp_l1_size; 968 dev_info->num_sqc_per_wgp = adev->gfx.config.gc_num_sqc_per_wgp; 969 dev_info->sqc_data_cache_size = adev->gfx.config.gc_l1_data_cache_size_per_sqc; 970 dev_info->sqc_inst_cache_size = adev->gfx.config.gc_l1_instruction_cache_size_per_sqc; 971 dev_info->gl1c_cache_size = adev->gfx.config.gc_gl1c_size_per_instance * 972 adev->gfx.config.gc_gl1c_per_sa; 973 dev_info->gl2c_cache_size = adev->gfx.config.gc_gl2c_per_gpu; 974 dev_info->mall_size = adev->gmc.mall_size; 975 976 977 if (adev->gfx.funcs->get_gfx_shadow_info) { 978 struct amdgpu_gfx_shadow_info shadow_info; 979 980 ret = amdgpu_gfx_get_gfx_shadow_info(adev, &shadow_info); 981 if (!ret) { 982 dev_info->shadow_size = shadow_info.shadow_size; 983 dev_info->shadow_alignment = shadow_info.shadow_alignment; 984 dev_info->csa_size = shadow_info.csa_size; 985 dev_info->csa_alignment = shadow_info.csa_alignment; 986 } 987 } 988 989 ret = copy_to_user(out, dev_info, 990 min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0; 991 kfree(dev_info); 992 return ret; 993 } 994 case AMDGPU_INFO_VCE_CLOCK_TABLE: { 995 unsigned int i; 996 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {}; 997 struct amd_vce_state *vce_state; 998 999 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) { 1000 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i); 1001 if (vce_state) { 1002 vce_clk_table.entries[i].sclk = vce_state->sclk; 1003 vce_clk_table.entries[i].mclk = vce_state->mclk; 1004 vce_clk_table.entries[i].eclk = vce_state->evclk; 1005 vce_clk_table.num_valid_entries++; 1006 } 1007 } 1008 1009 return copy_to_user(out, &vce_clk_table, 1010 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0; 1011 } 1012 case AMDGPU_INFO_VBIOS: { 1013 uint32_t bios_size = adev->bios_size; 1014 1015 switch (info->vbios_info.type) { 1016 case AMDGPU_INFO_VBIOS_SIZE: 1017 return copy_to_user(out, &bios_size, 1018 min((size_t)size, sizeof(bios_size))) 1019 ? -EFAULT : 0; 1020 case AMDGPU_INFO_VBIOS_IMAGE: { 1021 uint8_t *bios; 1022 uint32_t bios_offset = info->vbios_info.offset; 1023 1024 if (bios_offset >= bios_size) 1025 return -EINVAL; 1026 1027 bios = adev->bios + bios_offset; 1028 return copy_to_user(out, bios, 1029 min((size_t)size, (size_t)(bios_size - bios_offset))) 1030 ? -EFAULT : 0; 1031 } 1032 case AMDGPU_INFO_VBIOS_INFO: { 1033 struct drm_amdgpu_info_vbios vbios_info = {}; 1034 struct atom_context *atom_context; 1035 1036 atom_context = adev->mode_info.atom_context; 1037 if (atom_context) { 1038 memcpy(vbios_info.name, atom_context->name, 1039 sizeof(atom_context->name)); 1040 memcpy(vbios_info.vbios_pn, atom_context->vbios_pn, 1041 sizeof(atom_context->vbios_pn)); 1042 vbios_info.version = atom_context->version; 1043 memcpy(vbios_info.vbios_ver_str, atom_context->vbios_ver_str, 1044 sizeof(atom_context->vbios_ver_str)); 1045 memcpy(vbios_info.date, atom_context->date, 1046 sizeof(atom_context->date)); 1047 } 1048 1049 return copy_to_user(out, &vbios_info, 1050 min((size_t)size, sizeof(vbios_info))) ? -EFAULT : 0; 1051 } 1052 default: 1053 DRM_DEBUG_KMS("Invalid request %d\n", 1054 info->vbios_info.type); 1055 return -EINVAL; 1056 } 1057 } 1058 case AMDGPU_INFO_NUM_HANDLES: { 1059 struct drm_amdgpu_info_num_handles handle; 1060 1061 switch (info->query_hw_ip.type) { 1062 case AMDGPU_HW_IP_UVD: 1063 /* Starting Polaris, we support unlimited UVD handles */ 1064 if (adev->asic_type < CHIP_POLARIS10) { 1065 handle.uvd_max_handles = adev->uvd.max_handles; 1066 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev); 1067 1068 return copy_to_user(out, &handle, 1069 min((size_t)size, sizeof(handle))) ? -EFAULT : 0; 1070 } else { 1071 return -ENODATA; 1072 } 1073 1074 break; 1075 default: 1076 return -EINVAL; 1077 } 1078 } 1079 case AMDGPU_INFO_SENSOR: { 1080 if (!adev->pm.dpm_enabled) 1081 return -ENOENT; 1082 1083 switch (info->sensor_info.type) { 1084 case AMDGPU_INFO_SENSOR_GFX_SCLK: 1085 /* get sclk in Mhz */ 1086 if (amdgpu_dpm_read_sensor(adev, 1087 AMDGPU_PP_SENSOR_GFX_SCLK, 1088 (void *)&ui32, &ui32_size)) { 1089 return -EINVAL; 1090 } 1091 ui32 /= 100; 1092 break; 1093 case AMDGPU_INFO_SENSOR_GFX_MCLK: 1094 /* get mclk in Mhz */ 1095 if (amdgpu_dpm_read_sensor(adev, 1096 AMDGPU_PP_SENSOR_GFX_MCLK, 1097 (void *)&ui32, &ui32_size)) { 1098 return -EINVAL; 1099 } 1100 ui32 /= 100; 1101 break; 1102 case AMDGPU_INFO_SENSOR_GPU_TEMP: 1103 /* get temperature in millidegrees C */ 1104 if (amdgpu_dpm_read_sensor(adev, 1105 AMDGPU_PP_SENSOR_GPU_TEMP, 1106 (void *)&ui32, &ui32_size)) { 1107 return -EINVAL; 1108 } 1109 break; 1110 case AMDGPU_INFO_SENSOR_GPU_LOAD: 1111 /* get GPU load */ 1112 if (amdgpu_dpm_read_sensor(adev, 1113 AMDGPU_PP_SENSOR_GPU_LOAD, 1114 (void *)&ui32, &ui32_size)) { 1115 return -EINVAL; 1116 } 1117 break; 1118 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER: 1119 /* get average GPU power */ 1120 if (amdgpu_dpm_read_sensor(adev, 1121 AMDGPU_PP_SENSOR_GPU_AVG_POWER, 1122 (void *)&ui32, &ui32_size)) { 1123 /* fall back to input power for backwards compat */ 1124 if (amdgpu_dpm_read_sensor(adev, 1125 AMDGPU_PP_SENSOR_GPU_INPUT_POWER, 1126 (void *)&ui32, &ui32_size)) { 1127 return -EINVAL; 1128 } 1129 } 1130 ui32 >>= 8; 1131 break; 1132 case AMDGPU_INFO_SENSOR_GPU_INPUT_POWER: 1133 /* get input GPU power */ 1134 if (amdgpu_dpm_read_sensor(adev, 1135 AMDGPU_PP_SENSOR_GPU_INPUT_POWER, 1136 (void *)&ui32, &ui32_size)) { 1137 return -EINVAL; 1138 } 1139 ui32 >>= 8; 1140 break; 1141 case AMDGPU_INFO_SENSOR_VDDNB: 1142 /* get VDDNB in millivolts */ 1143 if (amdgpu_dpm_read_sensor(adev, 1144 AMDGPU_PP_SENSOR_VDDNB, 1145 (void *)&ui32, &ui32_size)) { 1146 return -EINVAL; 1147 } 1148 break; 1149 case AMDGPU_INFO_SENSOR_VDDGFX: 1150 /* get VDDGFX in millivolts */ 1151 if (amdgpu_dpm_read_sensor(adev, 1152 AMDGPU_PP_SENSOR_VDDGFX, 1153 (void *)&ui32, &ui32_size)) { 1154 return -EINVAL; 1155 } 1156 break; 1157 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK: 1158 /* get stable pstate sclk in Mhz */ 1159 if (amdgpu_dpm_read_sensor(adev, 1160 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 1161 (void *)&ui32, &ui32_size)) { 1162 return -EINVAL; 1163 } 1164 ui32 /= 100; 1165 break; 1166 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK: 1167 /* get stable pstate mclk in Mhz */ 1168 if (amdgpu_dpm_read_sensor(adev, 1169 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 1170 (void *)&ui32, &ui32_size)) { 1171 return -EINVAL; 1172 } 1173 ui32 /= 100; 1174 break; 1175 case AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK: 1176 /* get peak pstate sclk in Mhz */ 1177 if (amdgpu_dpm_read_sensor(adev, 1178 AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK, 1179 (void *)&ui32, &ui32_size)) { 1180 return -EINVAL; 1181 } 1182 ui32 /= 100; 1183 break; 1184 case AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK: 1185 /* get peak pstate mclk in Mhz */ 1186 if (amdgpu_dpm_read_sensor(adev, 1187 AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK, 1188 (void *)&ui32, &ui32_size)) { 1189 return -EINVAL; 1190 } 1191 ui32 /= 100; 1192 break; 1193 default: 1194 DRM_DEBUG_KMS("Invalid request %d\n", 1195 info->sensor_info.type); 1196 return -EINVAL; 1197 } 1198 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 1199 } 1200 case AMDGPU_INFO_VRAM_LOST_COUNTER: 1201 ui32 = atomic_read(&adev->vram_lost_counter); 1202 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 1203 case AMDGPU_INFO_RAS_ENABLED_FEATURES: { 1204 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1205 uint64_t ras_mask; 1206 1207 if (!ras) 1208 return -EINVAL; 1209 ras_mask = (uint64_t)adev->ras_enabled << 32 | ras->features; 1210 1211 return copy_to_user(out, &ras_mask, 1212 min_t(u64, size, sizeof(ras_mask))) ? 1213 -EFAULT : 0; 1214 } 1215 case AMDGPU_INFO_VIDEO_CAPS: { 1216 const struct amdgpu_video_codecs *codecs; 1217 struct drm_amdgpu_info_video_caps *caps; 1218 int r; 1219 1220 if (!adev->asic_funcs->query_video_codecs) 1221 return -EINVAL; 1222 1223 switch (info->video_cap.type) { 1224 case AMDGPU_INFO_VIDEO_CAPS_DECODE: 1225 r = amdgpu_asic_query_video_codecs(adev, false, &codecs); 1226 if (r) 1227 return -EINVAL; 1228 break; 1229 case AMDGPU_INFO_VIDEO_CAPS_ENCODE: 1230 r = amdgpu_asic_query_video_codecs(adev, true, &codecs); 1231 if (r) 1232 return -EINVAL; 1233 break; 1234 default: 1235 DRM_DEBUG_KMS("Invalid request %d\n", 1236 info->video_cap.type); 1237 return -EINVAL; 1238 } 1239 1240 caps = kzalloc(sizeof(*caps), GFP_KERNEL); 1241 if (!caps) 1242 return -ENOMEM; 1243 1244 for (i = 0; i < codecs->codec_count; i++) { 1245 int idx = codecs->codec_array[i].codec_type; 1246 1247 switch (idx) { 1248 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2: 1249 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4: 1250 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1: 1251 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC: 1252 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC: 1253 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG: 1254 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9: 1255 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1: 1256 caps->codec_info[idx].valid = 1; 1257 caps->codec_info[idx].max_width = 1258 codecs->codec_array[i].max_width; 1259 caps->codec_info[idx].max_height = 1260 codecs->codec_array[i].max_height; 1261 caps->codec_info[idx].max_pixels_per_frame = 1262 codecs->codec_array[i].max_pixels_per_frame; 1263 caps->codec_info[idx].max_level = 1264 codecs->codec_array[i].max_level; 1265 break; 1266 default: 1267 break; 1268 } 1269 } 1270 r = copy_to_user(out, caps, 1271 min((size_t)size, sizeof(*caps))) ? -EFAULT : 0; 1272 kfree(caps); 1273 return r; 1274 } 1275 case AMDGPU_INFO_MAX_IBS: { 1276 uint32_t max_ibs[AMDGPU_HW_IP_NUM]; 1277 1278 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) 1279 max_ibs[i] = amdgpu_ring_max_ibs(i); 1280 1281 return copy_to_user(out, max_ibs, 1282 min((size_t)size, sizeof(max_ibs))) ? -EFAULT : 0; 1283 } 1284 case AMDGPU_INFO_GPUVM_FAULT: { 1285 struct amdgpu_fpriv *fpriv = filp->driver_priv; 1286 struct amdgpu_vm *vm = &fpriv->vm; 1287 struct drm_amdgpu_info_gpuvm_fault gpuvm_fault; 1288 unsigned long flags; 1289 1290 if (!vm) 1291 return -EINVAL; 1292 1293 memset(&gpuvm_fault, 0, sizeof(gpuvm_fault)); 1294 1295 xa_lock_irqsave(&adev->vm_manager.pasids, flags); 1296 gpuvm_fault.addr = vm->fault_info.addr; 1297 gpuvm_fault.status = vm->fault_info.status; 1298 gpuvm_fault.vmhub = vm->fault_info.vmhub; 1299 xa_unlock_irqrestore(&adev->vm_manager.pasids, flags); 1300 1301 return copy_to_user(out, &gpuvm_fault, 1302 min((size_t)size, sizeof(gpuvm_fault))) ? -EFAULT : 0; 1303 } 1304 default: 1305 DRM_DEBUG_KMS("Invalid request %d\n", info->query); 1306 return -EINVAL; 1307 } 1308 return 0; 1309 } 1310 1311 1312 /* 1313 * Outdated mess for old drm with Xorg being in charge (void function now). 1314 */ 1315 /** 1316 * amdgpu_driver_lastclose_kms - drm callback for last close 1317 * 1318 * @dev: drm dev pointer 1319 * 1320 * Switch vga_switcheroo state after last close (all asics). 1321 */ 1322 void amdgpu_driver_lastclose_kms(struct drm_device *dev) 1323 { 1324 drm_fb_helper_lastclose(dev); 1325 vga_switcheroo_process_delayed_switch(); 1326 } 1327 1328 /** 1329 * amdgpu_driver_open_kms - drm callback for open 1330 * 1331 * @dev: drm dev pointer 1332 * @file_priv: drm file 1333 * 1334 * On device open, init vm on cayman+ (all asics). 1335 * Returns 0 on success, error on failure. 1336 */ 1337 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 1338 { 1339 struct amdgpu_device *adev = drm_to_adev(dev); 1340 struct amdgpu_fpriv *fpriv; 1341 int r, pasid; 1342 1343 /* Ensure IB tests are run on ring */ 1344 flush_delayed_work(&adev->delayed_init_work); 1345 1346 1347 if (amdgpu_ras_intr_triggered()) { 1348 DRM_ERROR("RAS Intr triggered, device disabled!!"); 1349 return -EHWPOISON; 1350 } 1351 1352 file_priv->driver_priv = NULL; 1353 1354 r = pm_runtime_get_sync(dev->dev); 1355 if (r < 0) 1356 goto pm_put; 1357 1358 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 1359 if (unlikely(!fpriv)) { 1360 r = -ENOMEM; 1361 goto out_suspend; 1362 } 1363 1364 pasid = amdgpu_pasid_alloc(16); 1365 if (pasid < 0) { 1366 dev_warn(adev->dev, "No more PASIDs available!"); 1367 pasid = 0; 1368 } 1369 1370 r = amdgpu_xcp_open_device(adev, fpriv, file_priv); 1371 if (r) 1372 goto error_pasid; 1373 1374 r = amdgpu_vm_init(adev, &fpriv->vm, fpriv->xcp_id); 1375 if (r) 1376 goto error_pasid; 1377 1378 r = amdgpu_vm_set_pasid(adev, &fpriv->vm, pasid); 1379 if (r) 1380 goto error_vm; 1381 1382 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL); 1383 if (!fpriv->prt_va) { 1384 r = -ENOMEM; 1385 goto error_vm; 1386 } 1387 1388 if (adev->gfx.mcbp) { 1389 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK; 1390 1391 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj, 1392 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE); 1393 if (r) 1394 goto error_vm; 1395 } 1396 1397 r = amdgpu_seq64_map(adev, &fpriv->vm, &fpriv->seq64_va); 1398 if (r) 1399 goto error_vm; 1400 1401 mutex_init(&fpriv->bo_list_lock); 1402 idr_init_base(&fpriv->bo_list_handles, 1); 1403 1404 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr, adev); 1405 1406 file_priv->driver_priv = fpriv; 1407 goto out_suspend; 1408 1409 error_vm: 1410 amdgpu_vm_fini(adev, &fpriv->vm); 1411 1412 error_pasid: 1413 if (pasid) { 1414 amdgpu_pasid_free(pasid); 1415 amdgpu_vm_set_pasid(adev, &fpriv->vm, 0); 1416 } 1417 1418 kfree(fpriv); 1419 1420 out_suspend: 1421 pm_runtime_mark_last_busy(dev->dev); 1422 pm_put: 1423 pm_runtime_put_autosuspend(dev->dev); 1424 1425 return r; 1426 } 1427 1428 /** 1429 * amdgpu_driver_postclose_kms - drm callback for post close 1430 * 1431 * @dev: drm dev pointer 1432 * @file_priv: drm file 1433 * 1434 * On device post close, tear down vm on cayman+ (all asics). 1435 */ 1436 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1437 struct drm_file *file_priv) 1438 { 1439 struct amdgpu_device *adev = drm_to_adev(dev); 1440 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1441 struct amdgpu_bo_list *list; 1442 struct amdgpu_bo *pd; 1443 u32 pasid; 1444 int handle; 1445 1446 if (!fpriv) 1447 return; 1448 1449 pm_runtime_get_sync(dev->dev); 1450 1451 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL) 1452 amdgpu_uvd_free_handles(adev, file_priv); 1453 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL) 1454 amdgpu_vce_free_handles(adev, file_priv); 1455 1456 if (fpriv->csa_va) { 1457 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK; 1458 1459 WARN_ON(amdgpu_unmap_static_csa(adev, &fpriv->vm, adev->virt.csa_obj, 1460 fpriv->csa_va, csa_addr)); 1461 fpriv->csa_va = NULL; 1462 } 1463 1464 amdgpu_seq64_unmap(adev, fpriv); 1465 1466 pasid = fpriv->vm.pasid; 1467 pd = amdgpu_bo_ref(fpriv->vm.root.bo); 1468 if (!WARN_ON(amdgpu_bo_reserve(pd, true))) { 1469 amdgpu_vm_bo_del(adev, fpriv->prt_va); 1470 amdgpu_bo_unreserve(pd); 1471 } 1472 1473 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); 1474 amdgpu_vm_fini(adev, &fpriv->vm); 1475 1476 if (pasid) 1477 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid); 1478 amdgpu_bo_unref(&pd); 1479 1480 idr_for_each_entry(&fpriv->bo_list_handles, list, handle) 1481 amdgpu_bo_list_put(list); 1482 1483 idr_destroy(&fpriv->bo_list_handles); 1484 mutex_destroy(&fpriv->bo_list_lock); 1485 1486 kfree(fpriv); 1487 file_priv->driver_priv = NULL; 1488 1489 pm_runtime_mark_last_busy(dev->dev); 1490 pm_runtime_put_autosuspend(dev->dev); 1491 } 1492 1493 1494 void amdgpu_driver_release_kms(struct drm_device *dev) 1495 { 1496 struct amdgpu_device *adev = drm_to_adev(dev); 1497 1498 amdgpu_device_fini_sw(adev); 1499 pci_set_drvdata(adev->pdev, NULL); 1500 } 1501 1502 /* 1503 * VBlank related functions. 1504 */ 1505 /** 1506 * amdgpu_get_vblank_counter_kms - get frame count 1507 * 1508 * @crtc: crtc to get the frame count from 1509 * 1510 * Gets the frame count on the requested crtc (all asics). 1511 * Returns frame count on success, -EINVAL on failure. 1512 */ 1513 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc) 1514 { 1515 struct drm_device *dev = crtc->dev; 1516 unsigned int pipe = crtc->index; 1517 struct amdgpu_device *adev = drm_to_adev(dev); 1518 int vpos, hpos, stat; 1519 u32 count; 1520 1521 if (pipe >= adev->mode_info.num_crtc) { 1522 DRM_ERROR("Invalid crtc %u\n", pipe); 1523 return -EINVAL; 1524 } 1525 1526 /* The hw increments its frame counter at start of vsync, not at start 1527 * of vblank, as is required by DRM core vblank counter handling. 1528 * Cook the hw count here to make it appear to the caller as if it 1529 * incremented at start of vblank. We measure distance to start of 1530 * vblank in vpos. vpos therefore will be >= 0 between start of vblank 1531 * and start of vsync, so vpos >= 0 means to bump the hw frame counter 1532 * result by 1 to give the proper appearance to caller. 1533 */ 1534 if (adev->mode_info.crtcs[pipe]) { 1535 /* Repeat readout if needed to provide stable result if 1536 * we cross start of vsync during the queries. 1537 */ 1538 do { 1539 count = amdgpu_display_vblank_get_counter(adev, pipe); 1540 /* Ask amdgpu_display_get_crtc_scanoutpos to return 1541 * vpos as distance to start of vblank, instead of 1542 * regular vertical scanout pos. 1543 */ 1544 stat = amdgpu_display_get_crtc_scanoutpos( 1545 dev, pipe, GET_DISTANCE_TO_VBLANKSTART, 1546 &vpos, &hpos, NULL, NULL, 1547 &adev->mode_info.crtcs[pipe]->base.hwmode); 1548 } while (count != amdgpu_display_vblank_get_counter(adev, pipe)); 1549 1550 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 1551 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 1552 DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 1553 } else { 1554 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", 1555 pipe, vpos); 1556 1557 /* Bump counter if we are at >= leading edge of vblank, 1558 * but before vsync where vpos would turn negative and 1559 * the hw counter really increments. 1560 */ 1561 if (vpos >= 0) 1562 count++; 1563 } 1564 } else { 1565 /* Fallback to use value as is. */ 1566 count = amdgpu_display_vblank_get_counter(adev, pipe); 1567 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 1568 } 1569 1570 return count; 1571 } 1572 1573 /** 1574 * amdgpu_enable_vblank_kms - enable vblank interrupt 1575 * 1576 * @crtc: crtc to enable vblank interrupt for 1577 * 1578 * Enable the interrupt on the requested crtc (all asics). 1579 * Returns 0 on success, -EINVAL on failure. 1580 */ 1581 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc) 1582 { 1583 struct drm_device *dev = crtc->dev; 1584 unsigned int pipe = crtc->index; 1585 struct amdgpu_device *adev = drm_to_adev(dev); 1586 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1587 1588 return amdgpu_irq_get(adev, &adev->crtc_irq, idx); 1589 } 1590 1591 /** 1592 * amdgpu_disable_vblank_kms - disable vblank interrupt 1593 * 1594 * @crtc: crtc to disable vblank interrupt for 1595 * 1596 * Disable the interrupt on the requested crtc (all asics). 1597 */ 1598 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc) 1599 { 1600 struct drm_device *dev = crtc->dev; 1601 unsigned int pipe = crtc->index; 1602 struct amdgpu_device *adev = drm_to_adev(dev); 1603 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1604 1605 amdgpu_irq_put(adev, &adev->crtc_irq, idx); 1606 } 1607 1608 /* 1609 * Debugfs info 1610 */ 1611 #if defined(CONFIG_DEBUG_FS) 1612 1613 static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused) 1614 { 1615 struct amdgpu_device *adev = m->private; 1616 struct drm_amdgpu_info_firmware fw_info; 1617 struct drm_amdgpu_query_fw query_fw; 1618 struct atom_context *ctx = adev->mode_info.atom_context; 1619 uint8_t smu_program, smu_major, smu_minor, smu_debug; 1620 int ret, i; 1621 1622 static const char *ta_fw_name[TA_FW_TYPE_MAX_INDEX] = { 1623 #define TA_FW_NAME(type)[TA_FW_TYPE_PSP_##type] = #type 1624 TA_FW_NAME(XGMI), 1625 TA_FW_NAME(RAS), 1626 TA_FW_NAME(HDCP), 1627 TA_FW_NAME(DTM), 1628 TA_FW_NAME(RAP), 1629 TA_FW_NAME(SECUREDISPLAY), 1630 #undef TA_FW_NAME 1631 }; 1632 1633 /* VCE */ 1634 query_fw.fw_type = AMDGPU_INFO_FW_VCE; 1635 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1636 if (ret) 1637 return ret; 1638 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n", 1639 fw_info.feature, fw_info.ver); 1640 1641 /* UVD */ 1642 query_fw.fw_type = AMDGPU_INFO_FW_UVD; 1643 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1644 if (ret) 1645 return ret; 1646 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n", 1647 fw_info.feature, fw_info.ver); 1648 1649 /* GMC */ 1650 query_fw.fw_type = AMDGPU_INFO_FW_GMC; 1651 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1652 if (ret) 1653 return ret; 1654 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n", 1655 fw_info.feature, fw_info.ver); 1656 1657 /* ME */ 1658 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME; 1659 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1660 if (ret) 1661 return ret; 1662 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n", 1663 fw_info.feature, fw_info.ver); 1664 1665 /* PFP */ 1666 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP; 1667 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1668 if (ret) 1669 return ret; 1670 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n", 1671 fw_info.feature, fw_info.ver); 1672 1673 /* CE */ 1674 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE; 1675 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1676 if (ret) 1677 return ret; 1678 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n", 1679 fw_info.feature, fw_info.ver); 1680 1681 /* RLC */ 1682 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC; 1683 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1684 if (ret) 1685 return ret; 1686 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n", 1687 fw_info.feature, fw_info.ver); 1688 1689 /* RLC SAVE RESTORE LIST CNTL */ 1690 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL; 1691 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1692 if (ret) 1693 return ret; 1694 seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n", 1695 fw_info.feature, fw_info.ver); 1696 1697 /* RLC SAVE RESTORE LIST GPM MEM */ 1698 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM; 1699 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1700 if (ret) 1701 return ret; 1702 seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n", 1703 fw_info.feature, fw_info.ver); 1704 1705 /* RLC SAVE RESTORE LIST SRM MEM */ 1706 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM; 1707 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1708 if (ret) 1709 return ret; 1710 seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n", 1711 fw_info.feature, fw_info.ver); 1712 1713 /* RLCP */ 1714 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCP; 1715 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1716 if (ret) 1717 return ret; 1718 seq_printf(m, "RLCP feature version: %u, firmware version: 0x%08x\n", 1719 fw_info.feature, fw_info.ver); 1720 1721 /* RLCV */ 1722 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCV; 1723 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1724 if (ret) 1725 return ret; 1726 seq_printf(m, "RLCV feature version: %u, firmware version: 0x%08x\n", 1727 fw_info.feature, fw_info.ver); 1728 1729 /* MEC */ 1730 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC; 1731 query_fw.index = 0; 1732 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1733 if (ret) 1734 return ret; 1735 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n", 1736 fw_info.feature, fw_info.ver); 1737 1738 /* MEC2 */ 1739 if (adev->gfx.mec2_fw) { 1740 query_fw.index = 1; 1741 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1742 if (ret) 1743 return ret; 1744 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n", 1745 fw_info.feature, fw_info.ver); 1746 } 1747 1748 /* IMU */ 1749 query_fw.fw_type = AMDGPU_INFO_FW_IMU; 1750 query_fw.index = 0; 1751 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1752 if (ret) 1753 return ret; 1754 seq_printf(m, "IMU feature version: %u, firmware version: 0x%08x\n", 1755 fw_info.feature, fw_info.ver); 1756 1757 /* PSP SOS */ 1758 query_fw.fw_type = AMDGPU_INFO_FW_SOS; 1759 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1760 if (ret) 1761 return ret; 1762 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n", 1763 fw_info.feature, fw_info.ver); 1764 1765 1766 /* PSP ASD */ 1767 query_fw.fw_type = AMDGPU_INFO_FW_ASD; 1768 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1769 if (ret) 1770 return ret; 1771 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n", 1772 fw_info.feature, fw_info.ver); 1773 1774 query_fw.fw_type = AMDGPU_INFO_FW_TA; 1775 for (i = TA_FW_TYPE_PSP_XGMI; i < TA_FW_TYPE_MAX_INDEX; i++) { 1776 query_fw.index = i; 1777 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1778 if (ret) 1779 continue; 1780 1781 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n", 1782 ta_fw_name[i], fw_info.feature, fw_info.ver); 1783 } 1784 1785 /* SMC */ 1786 query_fw.fw_type = AMDGPU_INFO_FW_SMC; 1787 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1788 if (ret) 1789 return ret; 1790 smu_program = (fw_info.ver >> 24) & 0xff; 1791 smu_major = (fw_info.ver >> 16) & 0xff; 1792 smu_minor = (fw_info.ver >> 8) & 0xff; 1793 smu_debug = (fw_info.ver >> 0) & 0xff; 1794 seq_printf(m, "SMC feature version: %u, program: %d, firmware version: 0x%08x (%d.%d.%d)\n", 1795 fw_info.feature, smu_program, fw_info.ver, smu_major, smu_minor, smu_debug); 1796 1797 /* SDMA */ 1798 query_fw.fw_type = AMDGPU_INFO_FW_SDMA; 1799 for (i = 0; i < adev->sdma.num_instances; i++) { 1800 query_fw.index = i; 1801 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1802 if (ret) 1803 return ret; 1804 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n", 1805 i, fw_info.feature, fw_info.ver); 1806 } 1807 1808 /* VCN */ 1809 query_fw.fw_type = AMDGPU_INFO_FW_VCN; 1810 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1811 if (ret) 1812 return ret; 1813 seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n", 1814 fw_info.feature, fw_info.ver); 1815 1816 /* DMCU */ 1817 query_fw.fw_type = AMDGPU_INFO_FW_DMCU; 1818 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1819 if (ret) 1820 return ret; 1821 seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n", 1822 fw_info.feature, fw_info.ver); 1823 1824 /* DMCUB */ 1825 query_fw.fw_type = AMDGPU_INFO_FW_DMCUB; 1826 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1827 if (ret) 1828 return ret; 1829 seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n", 1830 fw_info.feature, fw_info.ver); 1831 1832 /* TOC */ 1833 query_fw.fw_type = AMDGPU_INFO_FW_TOC; 1834 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1835 if (ret) 1836 return ret; 1837 seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n", 1838 fw_info.feature, fw_info.ver); 1839 1840 /* CAP */ 1841 if (adev->psp.cap_fw) { 1842 query_fw.fw_type = AMDGPU_INFO_FW_CAP; 1843 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1844 if (ret) 1845 return ret; 1846 seq_printf(m, "CAP feature version: %u, firmware version: 0x%08x\n", 1847 fw_info.feature, fw_info.ver); 1848 } 1849 1850 /* MES_KIQ */ 1851 query_fw.fw_type = AMDGPU_INFO_FW_MES_KIQ; 1852 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1853 if (ret) 1854 return ret; 1855 seq_printf(m, "MES_KIQ feature version: %u, firmware version: 0x%08x\n", 1856 fw_info.feature, fw_info.ver); 1857 1858 /* MES */ 1859 query_fw.fw_type = AMDGPU_INFO_FW_MES; 1860 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1861 if (ret) 1862 return ret; 1863 seq_printf(m, "MES feature version: %u, firmware version: 0x%08x\n", 1864 fw_info.feature, fw_info.ver); 1865 1866 /* VPE */ 1867 query_fw.fw_type = AMDGPU_INFO_FW_VPE; 1868 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1869 if (ret) 1870 return ret; 1871 seq_printf(m, "VPE feature version: %u, firmware version: 0x%08x\n", 1872 fw_info.feature, fw_info.ver); 1873 1874 seq_printf(m, "VBIOS version: %s\n", ctx->vbios_pn); 1875 1876 return 0; 1877 } 1878 1879 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_firmware_info); 1880 1881 #endif 1882 1883 void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev) 1884 { 1885 #if defined(CONFIG_DEBUG_FS) 1886 struct drm_minor *minor = adev_to_drm(adev)->primary; 1887 struct dentry *root = minor->debugfs_root; 1888 1889 debugfs_create_file("amdgpu_firmware_info", 0444, root, 1890 adev, &amdgpu_debugfs_firmware_info_fops); 1891 1892 #endif 1893 } 1894