1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include "amdgpu.h" 30 #include <drm/amdgpu_drm.h> 31 #include <drm/drm_drv.h> 32 #include <drm/drm_fb_helper.h> 33 #include <drm/drm_vblank.h> 34 #include "amdgpu_uvd.h" 35 #include "amdgpu_vce.h" 36 #include "atom.h" 37 38 #include <linux/vga_switcheroo.h> 39 #include <linux/slab.h> 40 #include <linux/uaccess.h> 41 #include <linux/pci.h> 42 #include <linux/pm_runtime.h> 43 #include "amdgpu_amdkfd.h" 44 #include "amdgpu_gem.h" 45 #include "amdgpu_display.h" 46 #include "amdgpu_ras.h" 47 #include "amdgpu_reset.h" 48 #include "amd_pcie.h" 49 #include "amdgpu_userq.h" 50 #include "amdgpu_video_codecs.h" 51 52 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev) 53 { 54 struct amdgpu_gpu_instance *gpu_instance; 55 int i; 56 57 mutex_lock(&mgpu_info.mutex); 58 59 for (i = 0; i < mgpu_info.num_gpu; i++) { 60 gpu_instance = &(mgpu_info.gpu_ins[i]); 61 if (gpu_instance->adev == adev) { 62 mgpu_info.gpu_ins[i] = 63 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1]; 64 mgpu_info.num_gpu--; 65 if (adev->flags & AMD_IS_APU) 66 mgpu_info.num_apu--; 67 else 68 mgpu_info.num_dgpu--; 69 break; 70 } 71 } 72 73 mutex_unlock(&mgpu_info.mutex); 74 } 75 76 /** 77 * amdgpu_driver_unload_kms - Main unload function for KMS. 78 * 79 * @dev: drm dev pointer 80 * 81 * This is the main unload function for KMS (all asics). 82 * Returns 0 on success. 83 */ 84 void amdgpu_driver_unload_kms(struct drm_device *dev) 85 { 86 struct amdgpu_device *adev = drm_to_adev(dev); 87 88 if (adev == NULL || !adev->num_ip_blocks) 89 return; 90 91 amdgpu_unregister_gpu_instance(adev); 92 93 if (adev->rmmio == NULL) 94 return; 95 96 if (amdgpu_acpi_smart_shift_update(adev, AMDGPU_SS_DRV_UNLOAD)) 97 drm_warn(dev, "smart shift update failed\n"); 98 99 amdgpu_acpi_fini(adev); 100 amdgpu_device_fini_hw(adev); 101 } 102 103 void amdgpu_register_gpu_instance(struct amdgpu_device *adev) 104 { 105 struct amdgpu_gpu_instance *gpu_instance; 106 107 mutex_lock(&mgpu_info.mutex); 108 109 if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) { 110 drm_err(adev_to_drm(adev), "Cannot register more gpu instance\n"); 111 mutex_unlock(&mgpu_info.mutex); 112 return; 113 } 114 115 gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]); 116 gpu_instance->adev = adev; 117 gpu_instance->mgpu_fan_enabled = 0; 118 119 mgpu_info.num_gpu++; 120 if (adev->flags & AMD_IS_APU) 121 mgpu_info.num_apu++; 122 else 123 mgpu_info.num_dgpu++; 124 125 mutex_unlock(&mgpu_info.mutex); 126 } 127 128 /** 129 * amdgpu_driver_load_kms - Main load function for KMS. 130 * 131 * @adev: pointer to struct amdgpu_device 132 * @flags: device flags 133 * 134 * This is the main load function for KMS (all asics). 135 * Returns 0 on success, error on failure. 136 */ 137 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags) 138 { 139 struct drm_device *dev; 140 int r, acpi_status; 141 142 dev = adev_to_drm(adev); 143 144 /* amdgpu_device_init should report only fatal error 145 * like memory allocation failure or iomapping failure, 146 * or memory manager initialization failure, it must 147 * properly initialize the GPU MC controller and permit 148 * VRAM allocation 149 */ 150 r = amdgpu_device_init(adev, flags); 151 if (r) { 152 dev_err(dev->dev, "Fatal error during GPU init\n"); 153 goto out; 154 } 155 156 amdgpu_device_detect_runtime_pm_mode(adev); 157 158 /* Call ACPI methods: require modeset init 159 * but failure is not fatal 160 */ 161 162 acpi_status = amdgpu_acpi_init(adev); 163 if (acpi_status) 164 dev_dbg(dev->dev, "Error during ACPI methods call\n"); 165 166 if (amdgpu_acpi_smart_shift_update(adev, AMDGPU_SS_DRV_LOAD)) 167 drm_warn(dev, "smart shift update failed\n"); 168 169 out: 170 if (r) 171 amdgpu_driver_unload_kms(dev); 172 173 return r; 174 } 175 176 static enum amd_ip_block_type 177 amdgpu_ip_get_block_type(struct amdgpu_device *adev, uint32_t ip) 178 { 179 enum amd_ip_block_type type; 180 181 switch (ip) { 182 case AMDGPU_HW_IP_GFX: 183 type = AMD_IP_BLOCK_TYPE_GFX; 184 break; 185 case AMDGPU_HW_IP_COMPUTE: 186 type = AMD_IP_BLOCK_TYPE_GFX; 187 break; 188 case AMDGPU_HW_IP_DMA: 189 type = AMD_IP_BLOCK_TYPE_SDMA; 190 break; 191 case AMDGPU_HW_IP_UVD: 192 case AMDGPU_HW_IP_UVD_ENC: 193 type = AMD_IP_BLOCK_TYPE_UVD; 194 break; 195 case AMDGPU_HW_IP_VCE: 196 type = AMD_IP_BLOCK_TYPE_VCE; 197 break; 198 case AMDGPU_HW_IP_VCN_DEC: 199 case AMDGPU_HW_IP_VCN_ENC: 200 type = AMD_IP_BLOCK_TYPE_VCN; 201 break; 202 case AMDGPU_HW_IP_VCN_JPEG: 203 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 204 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 205 break; 206 case AMDGPU_HW_IP_VPE: 207 type = AMD_IP_BLOCK_TYPE_VPE; 208 break; 209 default: 210 type = AMD_IP_BLOCK_TYPE_NUM; 211 break; 212 } 213 214 return type; 215 } 216 217 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, 218 struct drm_amdgpu_query_fw *query_fw, 219 struct amdgpu_device *adev) 220 { 221 switch (query_fw->fw_type) { 222 case AMDGPU_INFO_FW_VCE: 223 fw_info->ver = adev->vce.fw_version; 224 fw_info->feature = adev->vce.fb_version; 225 break; 226 case AMDGPU_INFO_FW_UVD: 227 fw_info->ver = adev->uvd.fw_version; 228 fw_info->feature = 0; 229 break; 230 case AMDGPU_INFO_FW_VCN: 231 fw_info->ver = adev->vcn.fw_version; 232 fw_info->feature = 0; 233 break; 234 case AMDGPU_INFO_FW_GMC: 235 fw_info->ver = adev->gmc.fw_version; 236 fw_info->feature = 0; 237 break; 238 case AMDGPU_INFO_FW_GFX_ME: 239 fw_info->ver = adev->gfx.me_fw_version; 240 fw_info->feature = adev->gfx.me_feature_version; 241 break; 242 case AMDGPU_INFO_FW_GFX_PFP: 243 fw_info->ver = adev->gfx.pfp_fw_version; 244 fw_info->feature = adev->gfx.pfp_feature_version; 245 break; 246 case AMDGPU_INFO_FW_GFX_CE: 247 fw_info->ver = adev->gfx.ce_fw_version; 248 fw_info->feature = adev->gfx.ce_feature_version; 249 break; 250 case AMDGPU_INFO_FW_GFX_RLC: 251 fw_info->ver = adev->gfx.rlc_fw_version; 252 fw_info->feature = adev->gfx.rlc_feature_version; 253 break; 254 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL: 255 fw_info->ver = adev->gfx.rlc_srlc_fw_version; 256 fw_info->feature = adev->gfx.rlc_srlc_feature_version; 257 break; 258 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM: 259 fw_info->ver = adev->gfx.rlc_srlg_fw_version; 260 fw_info->feature = adev->gfx.rlc_srlg_feature_version; 261 break; 262 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM: 263 fw_info->ver = adev->gfx.rlc_srls_fw_version; 264 fw_info->feature = adev->gfx.rlc_srls_feature_version; 265 break; 266 case AMDGPU_INFO_FW_GFX_RLCP: 267 fw_info->ver = adev->gfx.rlcp_ucode_version; 268 fw_info->feature = adev->gfx.rlcp_ucode_feature_version; 269 break; 270 case AMDGPU_INFO_FW_GFX_RLCV: 271 fw_info->ver = adev->gfx.rlcv_ucode_version; 272 fw_info->feature = adev->gfx.rlcv_ucode_feature_version; 273 break; 274 case AMDGPU_INFO_FW_GFX_MEC: 275 if (query_fw->index == 0) { 276 fw_info->ver = adev->gfx.mec_fw_version; 277 fw_info->feature = adev->gfx.mec_feature_version; 278 } else if (query_fw->index == 1) { 279 fw_info->ver = adev->gfx.mec2_fw_version; 280 fw_info->feature = adev->gfx.mec2_feature_version; 281 } else 282 return -EINVAL; 283 break; 284 case AMDGPU_INFO_FW_SMC: 285 fw_info->ver = adev->pm.fw_version; 286 fw_info->feature = 0; 287 break; 288 case AMDGPU_INFO_FW_TA: 289 switch (query_fw->index) { 290 case TA_FW_TYPE_PSP_XGMI: 291 fw_info->ver = adev->psp.xgmi_context.context.bin_desc.fw_version; 292 fw_info->feature = adev->psp.xgmi_context.context 293 .bin_desc.feature_version; 294 break; 295 case TA_FW_TYPE_PSP_RAS: 296 fw_info->ver = adev->psp.ras_context.context.bin_desc.fw_version; 297 fw_info->feature = adev->psp.ras_context.context 298 .bin_desc.feature_version; 299 break; 300 case TA_FW_TYPE_PSP_HDCP: 301 fw_info->ver = adev->psp.hdcp_context.context.bin_desc.fw_version; 302 fw_info->feature = adev->psp.hdcp_context.context 303 .bin_desc.feature_version; 304 break; 305 case TA_FW_TYPE_PSP_DTM: 306 fw_info->ver = adev->psp.dtm_context.context.bin_desc.fw_version; 307 fw_info->feature = adev->psp.dtm_context.context 308 .bin_desc.feature_version; 309 break; 310 case TA_FW_TYPE_PSP_RAP: 311 fw_info->ver = adev->psp.rap_context.context.bin_desc.fw_version; 312 fw_info->feature = adev->psp.rap_context.context 313 .bin_desc.feature_version; 314 break; 315 case TA_FW_TYPE_PSP_SECUREDISPLAY: 316 fw_info->ver = adev->psp.securedisplay_context.context.bin_desc.fw_version; 317 fw_info->feature = 318 adev->psp.securedisplay_context.context.bin_desc 319 .feature_version; 320 break; 321 default: 322 return -EINVAL; 323 } 324 break; 325 case AMDGPU_INFO_FW_SDMA: 326 if (query_fw->index >= adev->sdma.num_instances) 327 return -EINVAL; 328 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version; 329 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version; 330 break; 331 case AMDGPU_INFO_FW_SOS: 332 fw_info->ver = adev->psp.sos.fw_version; 333 fw_info->feature = adev->psp.sos.feature_version; 334 break; 335 case AMDGPU_INFO_FW_ASD: 336 fw_info->ver = adev->psp.asd_context.bin_desc.fw_version; 337 fw_info->feature = adev->psp.asd_context.bin_desc.feature_version; 338 break; 339 case AMDGPU_INFO_FW_DMCU: 340 fw_info->ver = adev->dm.dmcu_fw_version; 341 fw_info->feature = 0; 342 break; 343 case AMDGPU_INFO_FW_DMCUB: 344 fw_info->ver = adev->dm.dmcub_fw_version; 345 fw_info->feature = 0; 346 break; 347 case AMDGPU_INFO_FW_TOC: 348 fw_info->ver = adev->psp.toc.fw_version; 349 fw_info->feature = adev->psp.toc.feature_version; 350 break; 351 case AMDGPU_INFO_FW_CAP: 352 fw_info->ver = adev->psp.cap_fw_version; 353 fw_info->feature = adev->psp.cap_feature_version; 354 break; 355 case AMDGPU_INFO_FW_MES_KIQ: 356 fw_info->ver = adev->mes.kiq_version & AMDGPU_MES_VERSION_MASK; 357 fw_info->feature = (adev->mes.kiq_version & AMDGPU_MES_FEAT_VERSION_MASK) 358 >> AMDGPU_MES_FEAT_VERSION_SHIFT; 359 break; 360 case AMDGPU_INFO_FW_MES: 361 fw_info->ver = adev->mes.sched_version & AMDGPU_MES_VERSION_MASK; 362 fw_info->feature = (adev->mes.sched_version & AMDGPU_MES_FEAT_VERSION_MASK) 363 >> AMDGPU_MES_FEAT_VERSION_SHIFT; 364 break; 365 case AMDGPU_INFO_FW_IMU: 366 fw_info->ver = adev->gfx.imu_fw_version; 367 fw_info->feature = 0; 368 break; 369 case AMDGPU_INFO_FW_VPE: 370 fw_info->ver = adev->vpe.fw_version; 371 fw_info->feature = adev->vpe.feature_version; 372 break; 373 default: 374 return -EINVAL; 375 } 376 return 0; 377 } 378 379 static int amdgpu_userq_metadata_info_gfx(struct amdgpu_device *adev, 380 struct drm_amdgpu_info *info, 381 struct drm_amdgpu_info_uq_metadata_gfx *meta) 382 { 383 int ret = -EOPNOTSUPP; 384 385 if (adev->gfx.funcs->get_gfx_shadow_info) { 386 struct amdgpu_gfx_shadow_info shadow = {}; 387 388 adev->gfx.funcs->get_gfx_shadow_info(adev, &shadow, true); 389 meta->shadow_size = shadow.shadow_size; 390 meta->shadow_alignment = shadow.shadow_alignment; 391 meta->csa_size = shadow.csa_size; 392 meta->csa_alignment = shadow.csa_alignment; 393 ret = 0; 394 } 395 396 return ret; 397 } 398 399 static int amdgpu_userq_metadata_info_compute(struct amdgpu_device *adev, 400 struct drm_amdgpu_info *info, 401 struct drm_amdgpu_info_uq_metadata_compute *meta) 402 { 403 int ret = -EOPNOTSUPP; 404 405 if (adev->gfx.funcs->get_gfx_shadow_info) { 406 struct amdgpu_gfx_shadow_info shadow = {}; 407 408 adev->gfx.funcs->get_gfx_shadow_info(adev, &shadow, true); 409 meta->eop_size = shadow.eop_size; 410 meta->eop_alignment = shadow.eop_alignment; 411 ret = 0; 412 } 413 414 return ret; 415 } 416 417 static int amdgpu_userq_metadata_info_sdma(struct amdgpu_device *adev, 418 struct drm_amdgpu_info *info, 419 struct drm_amdgpu_info_uq_metadata_sdma *meta) 420 { 421 int ret = -EOPNOTSUPP; 422 423 if (adev->sdma.get_csa_info) { 424 struct amdgpu_sdma_csa_info csa = {}; 425 426 adev->sdma.get_csa_info(adev, &csa); 427 meta->csa_size = csa.size; 428 meta->csa_alignment = csa.alignment; 429 ret = 0; 430 } 431 432 return ret; 433 } 434 435 static int amdgpu_hw_ip_info(struct amdgpu_device *adev, 436 struct drm_amdgpu_info *info, 437 struct drm_amdgpu_info_hw_ip *result) 438 { 439 uint32_t ib_start_alignment = 0; 440 uint32_t ib_size_alignment = 0; 441 enum amd_ip_block_type type; 442 unsigned int num_rings = 0; 443 uint32_t num_slots = 0; 444 unsigned int i, j; 445 446 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 447 return -EINVAL; 448 449 switch (info->query_hw_ip.type) { 450 case AMDGPU_HW_IP_GFX: 451 type = AMD_IP_BLOCK_TYPE_GFX; 452 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 453 if (adev->gfx.gfx_ring[i].sched.ready && 454 !adev->gfx.gfx_ring[i].no_user_submission) 455 ++num_rings; 456 457 if (!adev->gfx.disable_uq) { 458 for (i = 0; i < AMDGPU_MES_MAX_GFX_PIPES; i++) 459 num_slots += hweight32(adev->mes.gfx_hqd_mask[i]); 460 } 461 462 ib_start_alignment = 32; 463 ib_size_alignment = 32; 464 break; 465 case AMDGPU_HW_IP_COMPUTE: 466 type = AMD_IP_BLOCK_TYPE_GFX; 467 for (i = 0; i < adev->gfx.num_compute_rings; i++) 468 if (adev->gfx.compute_ring[i].sched.ready && 469 !adev->gfx.compute_ring[i].no_user_submission) 470 ++num_rings; 471 472 if (!adev->sdma.disable_uq) { 473 for (i = 0; i < AMDGPU_MES_MAX_COMPUTE_PIPES; i++) 474 num_slots += hweight32(adev->mes.compute_hqd_mask[i]); 475 } 476 477 ib_start_alignment = 32; 478 ib_size_alignment = 32; 479 break; 480 case AMDGPU_HW_IP_DMA: 481 type = AMD_IP_BLOCK_TYPE_SDMA; 482 for (i = 0; i < adev->sdma.num_instances; i++) 483 if (adev->sdma.instance[i].ring.sched.ready && 484 !adev->sdma.instance[i].ring.no_user_submission) 485 ++num_rings; 486 487 if (!adev->gfx.disable_uq) { 488 for (i = 0; i < AMDGPU_MES_MAX_SDMA_PIPES; i++) 489 num_slots += hweight32(adev->mes.sdma_hqd_mask[i]); 490 } 491 492 ib_start_alignment = 256; 493 ib_size_alignment = 4; 494 break; 495 case AMDGPU_HW_IP_UVD: 496 type = AMD_IP_BLOCK_TYPE_UVD; 497 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 498 if (adev->uvd.harvest_config & (1 << i)) 499 continue; 500 501 if (adev->uvd.inst[i].ring.sched.ready && 502 !adev->uvd.inst[i].ring.no_user_submission) 503 ++num_rings; 504 } 505 ib_start_alignment = 256; 506 ib_size_alignment = 64; 507 break; 508 case AMDGPU_HW_IP_VCE: 509 type = AMD_IP_BLOCK_TYPE_VCE; 510 for (i = 0; i < adev->vce.num_rings; i++) 511 if (adev->vce.ring[i].sched.ready && 512 !adev->vce.ring[i].no_user_submission) 513 ++num_rings; 514 ib_start_alignment = 256; 515 ib_size_alignment = 4; 516 break; 517 case AMDGPU_HW_IP_UVD_ENC: 518 type = AMD_IP_BLOCK_TYPE_UVD; 519 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 520 if (adev->uvd.harvest_config & (1 << i)) 521 continue; 522 523 for (j = 0; j < adev->uvd.num_enc_rings; j++) 524 if (adev->uvd.inst[i].ring_enc[j].sched.ready && 525 !adev->uvd.inst[i].ring_enc[j].no_user_submission) 526 ++num_rings; 527 } 528 ib_start_alignment = 256; 529 ib_size_alignment = 4; 530 break; 531 case AMDGPU_HW_IP_VCN_DEC: 532 type = AMD_IP_BLOCK_TYPE_VCN; 533 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 534 if (adev->vcn.harvest_config & (1 << i)) 535 continue; 536 537 if (adev->vcn.inst[i].ring_dec.sched.ready && 538 !adev->vcn.inst[i].ring_dec.no_user_submission) 539 ++num_rings; 540 } 541 ib_start_alignment = 256; 542 ib_size_alignment = 64; 543 break; 544 case AMDGPU_HW_IP_VCN_ENC: 545 type = AMD_IP_BLOCK_TYPE_VCN; 546 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 547 if (adev->vcn.harvest_config & (1 << i)) 548 continue; 549 550 for (j = 0; j < adev->vcn.inst[i].num_enc_rings; j++) 551 if (adev->vcn.inst[i].ring_enc[j].sched.ready && 552 !adev->vcn.inst[i].ring_enc[j].no_user_submission) 553 ++num_rings; 554 } 555 ib_start_alignment = 256; 556 ib_size_alignment = 4; 557 break; 558 case AMDGPU_HW_IP_VCN_JPEG: 559 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 560 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 561 562 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { 563 if (adev->jpeg.harvest_config & (1 << i)) 564 continue; 565 566 for (j = 0; j < adev->jpeg.num_jpeg_rings; j++) 567 if (adev->jpeg.inst[i].ring_dec[j].sched.ready && 568 !adev->jpeg.inst[i].ring_dec[j].no_user_submission) 569 ++num_rings; 570 } 571 ib_start_alignment = 256; 572 ib_size_alignment = 64; 573 break; 574 case AMDGPU_HW_IP_VPE: 575 type = AMD_IP_BLOCK_TYPE_VPE; 576 if (adev->vpe.ring.sched.ready && 577 !adev->vpe.ring.no_user_submission) 578 ++num_rings; 579 ib_start_alignment = 256; 580 ib_size_alignment = 4; 581 break; 582 default: 583 return -EINVAL; 584 } 585 586 for (i = 0; i < adev->num_ip_blocks; i++) 587 if (adev->ip_blocks[i].version->type == type && 588 adev->ip_blocks[i].status.valid) 589 break; 590 591 if (i == adev->num_ip_blocks) 592 return 0; 593 594 num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type], 595 num_rings); 596 597 result->hw_ip_version_major = adev->ip_blocks[i].version->major; 598 result->hw_ip_version_minor = adev->ip_blocks[i].version->minor; 599 600 if (adev->asic_type >= CHIP_VEGA10) { 601 switch (type) { 602 case AMD_IP_BLOCK_TYPE_GFX: 603 result->ip_discovery_version = 604 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, GC_HWIP, 0)); 605 break; 606 case AMD_IP_BLOCK_TYPE_SDMA: 607 result->ip_discovery_version = 608 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, SDMA0_HWIP, 0)); 609 break; 610 case AMD_IP_BLOCK_TYPE_UVD: 611 case AMD_IP_BLOCK_TYPE_VCN: 612 case AMD_IP_BLOCK_TYPE_JPEG: 613 result->ip_discovery_version = 614 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, UVD_HWIP, 0)); 615 break; 616 case AMD_IP_BLOCK_TYPE_VCE: 617 result->ip_discovery_version = 618 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, VCE_HWIP, 0)); 619 break; 620 case AMD_IP_BLOCK_TYPE_VPE: 621 result->ip_discovery_version = 622 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, VPE_HWIP, 0)); 623 break; 624 default: 625 result->ip_discovery_version = 0; 626 break; 627 } 628 } else { 629 result->ip_discovery_version = 0; 630 } 631 result->capabilities_flags = 0; 632 result->available_rings = (1 << num_rings) - 1; 633 result->userq_num_slots = num_slots; 634 result->ib_start_alignment = ib_start_alignment; 635 result->ib_size_alignment = ib_size_alignment; 636 return 0; 637 } 638 639 /* 640 * Userspace get information ioctl 641 */ 642 /** 643 * amdgpu_info_ioctl - answer a device specific request. 644 * 645 * @dev: drm device pointer 646 * @data: request object 647 * @filp: drm filp 648 * 649 * This function is used to pass device specific parameters to the userspace 650 * drivers. Examples include: pci device id, pipeline parms, tiling params, 651 * etc. (all asics). 652 * Returns 0 on success, -EINVAL on failure. 653 */ 654 int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 655 { 656 struct amdgpu_device *adev = drm_to_adev(dev); 657 struct drm_amdgpu_info *info = data; 658 struct amdgpu_mode_info *minfo = &adev->mode_info; 659 void __user *out = (void __user *)(uintptr_t)info->return_pointer; 660 struct amdgpu_fpriv *fpriv; 661 struct amdgpu_ip_block *ip_block; 662 enum amd_ip_block_type type; 663 struct amdgpu_xcp *xcp; 664 u32 count, inst_mask; 665 uint32_t size = info->return_size; 666 struct drm_crtc *crtc; 667 uint32_t ui32 = 0; 668 uint64_t ui64 = 0; 669 int i, found, ret; 670 int ui32_size = sizeof(ui32); 671 672 if (!info->return_size || !info->return_pointer) 673 return -EINVAL; 674 675 switch (info->query) { 676 case AMDGPU_INFO_ACCEL_WORKING: 677 ui32 = adev->accel_working; 678 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 679 case AMDGPU_INFO_CRTC_FROM_ID: 680 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { 681 crtc = (struct drm_crtc *)minfo->crtcs[i]; 682 if (crtc && crtc->base.id == info->mode_crtc.id) { 683 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 684 685 ui32 = amdgpu_crtc->crtc_id; 686 found = 1; 687 break; 688 } 689 } 690 if (!found) { 691 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); 692 return -EINVAL; 693 } 694 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 695 case AMDGPU_INFO_HW_IP_INFO: { 696 struct drm_amdgpu_info_hw_ip ip = {}; 697 698 ret = amdgpu_hw_ip_info(adev, info, &ip); 699 if (ret) 700 return ret; 701 702 ret = copy_to_user(out, &ip, min_t(size_t, size, sizeof(ip))); 703 return ret ? -EFAULT : 0; 704 } 705 case AMDGPU_INFO_HW_IP_COUNT: { 706 fpriv = (struct amdgpu_fpriv *)filp->driver_priv; 707 type = amdgpu_ip_get_block_type(adev, info->query_hw_ip.type); 708 ip_block = amdgpu_device_ip_get_ip_block(adev, type); 709 710 if (!ip_block || !ip_block->status.valid) 711 return -EINVAL; 712 713 if (adev->xcp_mgr && adev->xcp_mgr->num_xcps > 0 && 714 fpriv->xcp_id < adev->xcp_mgr->num_xcps) { 715 xcp = &adev->xcp_mgr->xcp[fpriv->xcp_id]; 716 switch (type) { 717 case AMD_IP_BLOCK_TYPE_GFX: 718 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &inst_mask); 719 if (ret) 720 return ret; 721 count = hweight32(inst_mask); 722 break; 723 case AMD_IP_BLOCK_TYPE_SDMA: 724 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_SDMA, &inst_mask); 725 if (ret) 726 return ret; 727 count = hweight32(inst_mask); 728 break; 729 case AMD_IP_BLOCK_TYPE_JPEG: 730 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask); 731 if (ret) 732 return ret; 733 count = hweight32(inst_mask) * adev->jpeg.num_jpeg_rings; 734 break; 735 case AMD_IP_BLOCK_TYPE_VCN: 736 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask); 737 if (ret) 738 return ret; 739 count = hweight32(inst_mask); 740 break; 741 default: 742 return -EINVAL; 743 } 744 745 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; 746 } 747 748 switch (type) { 749 case AMD_IP_BLOCK_TYPE_GFX: 750 case AMD_IP_BLOCK_TYPE_VCE: 751 count = 1; 752 break; 753 case AMD_IP_BLOCK_TYPE_SDMA: 754 count = adev->sdma.num_instances; 755 break; 756 case AMD_IP_BLOCK_TYPE_JPEG: 757 count = adev->jpeg.num_jpeg_inst * adev->jpeg.num_jpeg_rings; 758 break; 759 case AMD_IP_BLOCK_TYPE_VCN: 760 count = adev->vcn.num_vcn_inst; 761 break; 762 case AMD_IP_BLOCK_TYPE_UVD: 763 count = adev->uvd.num_uvd_inst; 764 break; 765 case AMD_IP_BLOCK_TYPE_VPE: 766 count = adev->vpe.num_instances; 767 break; 768 /* For all other IP block types not listed in the switch statement 769 * the ip status is valid here and the instance count is one. 770 */ 771 default: 772 count = 1; 773 break; 774 } 775 776 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; 777 } 778 case AMDGPU_INFO_TIMESTAMP: 779 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev); 780 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 781 case AMDGPU_INFO_FW_VERSION: { 782 struct drm_amdgpu_info_firmware fw_info; 783 784 /* We only support one instance of each IP block right now. */ 785 if (info->query_fw.ip_instance != 0) 786 return -EINVAL; 787 788 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev); 789 if (ret) 790 return ret; 791 792 return copy_to_user(out, &fw_info, 793 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0; 794 } 795 case AMDGPU_INFO_NUM_BYTES_MOVED: 796 ui64 = atomic64_read(&adev->num_bytes_moved); 797 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 798 case AMDGPU_INFO_NUM_EVICTIONS: 799 ui64 = atomic64_read(&adev->num_evictions); 800 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 801 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS: 802 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults); 803 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 804 case AMDGPU_INFO_VRAM_USAGE: 805 ui64 = ttm_resource_manager_used(&adev->mman.vram_mgr.manager) ? 806 ttm_resource_manager_usage(&adev->mman.vram_mgr.manager) : 0; 807 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 808 case AMDGPU_INFO_VIS_VRAM_USAGE: 809 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr); 810 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 811 case AMDGPU_INFO_GTT_USAGE: 812 ui64 = ttm_resource_manager_usage(&adev->mman.gtt_mgr.manager); 813 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 814 case AMDGPU_INFO_GDS_CONFIG: { 815 struct drm_amdgpu_info_gds gds_info; 816 817 memset(&gds_info, 0, sizeof(gds_info)); 818 gds_info.compute_partition_size = adev->gds.gds_size; 819 gds_info.gds_total_size = adev->gds.gds_size; 820 gds_info.gws_per_compute_partition = adev->gds.gws_size; 821 gds_info.oa_per_compute_partition = adev->gds.oa_size; 822 return copy_to_user(out, &gds_info, 823 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0; 824 } 825 case AMDGPU_INFO_VRAM_GTT: { 826 struct drm_amdgpu_info_vram_gtt vram_gtt; 827 828 vram_gtt.vram_size = adev->gmc.real_vram_size - 829 atomic64_read(&adev->vram_pin_size) - 830 AMDGPU_VM_RESERVED_VRAM; 831 vram_gtt.vram_cpu_accessible_size = 832 min(adev->gmc.visible_vram_size - 833 atomic64_read(&adev->visible_pin_size), 834 vram_gtt.vram_size); 835 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size; 836 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size); 837 return copy_to_user(out, &vram_gtt, 838 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; 839 } 840 case AMDGPU_INFO_MEMORY: { 841 struct drm_amdgpu_memory_info mem; 842 struct ttm_resource_manager *gtt_man = 843 &adev->mman.gtt_mgr.manager; 844 struct ttm_resource_manager *vram_man = 845 &adev->mman.vram_mgr.manager; 846 847 memset(&mem, 0, sizeof(mem)); 848 mem.vram.total_heap_size = adev->gmc.real_vram_size; 849 mem.vram.usable_heap_size = adev->gmc.real_vram_size - 850 atomic64_read(&adev->vram_pin_size) - 851 AMDGPU_VM_RESERVED_VRAM; 852 mem.vram.heap_usage = ttm_resource_manager_used(&adev->mman.vram_mgr.manager) ? 853 ttm_resource_manager_usage(vram_man) : 0; 854 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4; 855 856 mem.cpu_accessible_vram.total_heap_size = 857 adev->gmc.visible_vram_size; 858 mem.cpu_accessible_vram.usable_heap_size = 859 min(adev->gmc.visible_vram_size - 860 atomic64_read(&adev->visible_pin_size), 861 mem.vram.usable_heap_size); 862 mem.cpu_accessible_vram.heap_usage = 863 amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr); 864 mem.cpu_accessible_vram.max_allocation = 865 mem.cpu_accessible_vram.usable_heap_size * 3 / 4; 866 867 mem.gtt.total_heap_size = gtt_man->size; 868 mem.gtt.usable_heap_size = mem.gtt.total_heap_size - 869 atomic64_read(&adev->gart_pin_size); 870 mem.gtt.heap_usage = ttm_resource_manager_usage(gtt_man); 871 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4; 872 873 return copy_to_user(out, &mem, 874 min((size_t)size, sizeof(mem))) 875 ? -EFAULT : 0; 876 } 877 case AMDGPU_INFO_READ_MMR_REG: { 878 unsigned int se_num = (info->read_mmr_reg.instance >> 879 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & 880 AMDGPU_INFO_MMR_SE_INDEX_MASK; 881 unsigned int sh_num = (info->read_mmr_reg.instance >> 882 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & 883 AMDGPU_INFO_MMR_SH_INDEX_MASK; 884 unsigned int alloc_size; 885 uint32_t *regs; 886 int ret; 887 888 /* set full masks if the userspace set all bits 889 * in the bitfields 890 */ 891 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) 892 se_num = 0xffffffff; 893 else if (se_num >= AMDGPU_GFX_MAX_SE) 894 return -EINVAL; 895 896 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) 897 sh_num = 0xffffffff; 898 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE) 899 return -EINVAL; 900 901 if (info->read_mmr_reg.count > 128) 902 return -EINVAL; 903 904 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), 905 GFP_KERNEL); 906 if (!regs) 907 return -ENOMEM; 908 909 down_read(&adev->reset_domain->sem); 910 alloc_size = info->read_mmr_reg.count * sizeof(*regs); 911 amdgpu_gfx_off_ctrl(adev, false); 912 ret = 0; 913 for (i = 0; i < info->read_mmr_reg.count; i++) { 914 if (amdgpu_asic_read_register(adev, se_num, sh_num, 915 info->read_mmr_reg.dword_offset + i, 916 ®s[i])) { 917 DRM_DEBUG_KMS("unallowed offset %#x\n", 918 info->read_mmr_reg.dword_offset + i); 919 ret = -EFAULT; 920 break; 921 } 922 } 923 amdgpu_gfx_off_ctrl(adev, true); 924 up_read(&adev->reset_domain->sem); 925 926 if (!ret) { 927 ret = copy_to_user(out, regs, min(size, alloc_size)) 928 ? -EFAULT : 0; 929 } 930 kfree(regs); 931 return ret; 932 } 933 case AMDGPU_INFO_DEV_INFO: { 934 struct drm_amdgpu_info_device *dev_info; 935 uint64_t vm_size; 936 uint32_t pcie_gen_mask, pcie_width_mask; 937 938 dev_info = kzalloc_obj(*dev_info); 939 if (!dev_info) 940 return -ENOMEM; 941 942 dev_info->device_id = adev->pdev->device; 943 dev_info->chip_rev = adev->rev_id; 944 dev_info->external_rev = adev->external_rev_id; 945 dev_info->pci_rev = adev->pdev->revision; 946 dev_info->family = adev->family; 947 dev_info->num_shader_engines = adev->gfx.config.max_shader_engines; 948 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 949 /* return all clocks in KHz */ 950 dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; 951 if (adev->pm.dpm_enabled) { 952 dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10; 953 dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10; 954 dev_info->min_engine_clock = amdgpu_dpm_get_sclk(adev, true) * 10; 955 dev_info->min_memory_clock = amdgpu_dpm_get_mclk(adev, true) * 10; 956 } else { 957 dev_info->max_engine_clock = 958 dev_info->min_engine_clock = 959 adev->clock.default_sclk * 10; 960 dev_info->max_memory_clock = 961 dev_info->min_memory_clock = 962 adev->clock.default_mclk * 10; 963 } 964 dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; 965 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se * 966 adev->gfx.config.max_shader_engines; 967 dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; 968 dev_info->ids_flags = 0; 969 if (adev->flags & AMD_IS_APU) 970 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION; 971 if (adev->gfx.mcbp) 972 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION; 973 if (amdgpu_is_tmz(adev)) 974 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ; 975 if (adev->gfx.config.ta_cntl2_truncate_coord_mode) 976 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD; 977 978 /* Gang submit is not supported under SRIOV currently */ 979 if (!amdgpu_sriov_vf(adev)) 980 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_GANG_SUBMIT; 981 982 if (amdgpu_passthrough(adev)) 983 dev_info->ids_flags |= (AMDGPU_IDS_FLAGS_MODE_PT << 984 AMDGPU_IDS_FLAGS_MODE_SHIFT) & 985 AMDGPU_IDS_FLAGS_MODE_MASK; 986 else if (amdgpu_sriov_vf(adev)) 987 dev_info->ids_flags |= (AMDGPU_IDS_FLAGS_MODE_VF << 988 AMDGPU_IDS_FLAGS_MODE_SHIFT) & 989 AMDGPU_IDS_FLAGS_MODE_MASK; 990 991 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 992 vm_size -= AMDGPU_VA_RESERVED_TOP; 993 994 /* Older VCE FW versions are buggy and can handle only 40bits */ 995 if (adev->vce.fw_version && 996 adev->vce.fw_version < AMDGPU_VCE_FW_53_45) 997 vm_size = min(vm_size, 1ULL << 40); 998 999 dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_BOTTOM; 1000 dev_info->virtual_address_max = 1001 min(vm_size, AMDGPU_GMC_HOLE_START); 1002 1003 if (vm_size > AMDGPU_GMC_HOLE_START) { 1004 dev_info->high_va_offset = AMDGPU_GMC_HOLE_END; 1005 dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size; 1006 } 1007 dev_info->virtual_address_alignment = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 1008 dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE; 1009 dev_info->gart_page_size = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 1010 dev_info->cu_active_number = adev->gfx.cu_info.number; 1011 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; 1012 dev_info->ce_ram_size = adev->gfx.ce_ram_size; 1013 memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0], 1014 sizeof(adev->gfx.cu_info.ao_cu_bitmap)); 1015 memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], 1016 sizeof(dev_info->cu_bitmap)); 1017 dev_info->vram_type = adev->gmc.vram_type; 1018 dev_info->vram_bit_width = adev->gmc.vram_width; 1019 dev_info->vce_harvest_config = adev->vce.harvest_config; 1020 dev_info->gc_double_offchip_lds_buf = 1021 adev->gfx.config.double_offchip_lds_buf; 1022 dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size; 1023 dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs; 1024 dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh; 1025 dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches; 1026 dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth; 1027 dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth; 1028 dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads; 1029 1030 if (adev->family >= AMDGPU_FAMILY_NV) 1031 dev_info->pa_sc_tile_steering_override = 1032 adev->gfx.config.pa_sc_tile_steering_override; 1033 1034 dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask; 1035 1036 /* Combine the chip gen mask with the platform (CPU/mobo) mask. */ 1037 pcie_gen_mask = adev->pm.pcie_gen_mask & 1038 (adev->pm.pcie_gen_mask >> CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT); 1039 pcie_width_mask = adev->pm.pcie_mlw_mask & 1040 (adev->pm.pcie_mlw_mask >> CAIL_PCIE_LINK_WIDTH_SUPPORT_SHIFT); 1041 dev_info->pcie_gen = fls(pcie_gen_mask); 1042 dev_info->pcie_num_lanes = 1043 pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X32 ? 32 : 1044 pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X16 ? 16 : 1045 pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X12 ? 12 : 1046 pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X8 ? 8 : 1047 pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X4 ? 4 : 1048 pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X2 ? 2 : 1; 1049 1050 dev_info->tcp_cache_size = adev->gfx.config.gc_tcp_l1_size; 1051 dev_info->num_sqc_per_wgp = adev->gfx.config.gc_num_sqc_per_wgp; 1052 dev_info->sqc_data_cache_size = adev->gfx.config.gc_l1_data_cache_size_per_sqc; 1053 dev_info->sqc_inst_cache_size = adev->gfx.config.gc_l1_instruction_cache_size_per_sqc; 1054 dev_info->gl1c_cache_size = adev->gfx.config.gc_gl1c_size_per_instance * 1055 adev->gfx.config.gc_gl1c_per_sa; 1056 dev_info->gl2c_cache_size = adev->gfx.config.gc_gl2c_per_gpu; 1057 dev_info->mall_size = adev->gmc.mall_size; 1058 1059 1060 if (adev->gfx.funcs->get_gfx_shadow_info) { 1061 struct amdgpu_gfx_shadow_info shadow_info; 1062 1063 ret = amdgpu_gfx_get_gfx_shadow_info(adev, &shadow_info); 1064 if (!ret) { 1065 dev_info->shadow_size = shadow_info.shadow_size; 1066 dev_info->shadow_alignment = shadow_info.shadow_alignment; 1067 dev_info->csa_size = shadow_info.csa_size; 1068 dev_info->csa_alignment = shadow_info.csa_alignment; 1069 } 1070 } 1071 1072 dev_info->userq_ip_mask = amdgpu_userq_get_supported_ip_mask(adev); 1073 1074 ret = copy_to_user(out, dev_info, 1075 min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0; 1076 kfree(dev_info); 1077 return ret; 1078 } 1079 case AMDGPU_INFO_VCE_CLOCK_TABLE: { 1080 unsigned int i; 1081 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {}; 1082 struct amd_vce_state *vce_state; 1083 1084 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) { 1085 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i); 1086 if (vce_state) { 1087 vce_clk_table.entries[i].sclk = vce_state->sclk; 1088 vce_clk_table.entries[i].mclk = vce_state->mclk; 1089 vce_clk_table.entries[i].eclk = vce_state->evclk; 1090 vce_clk_table.num_valid_entries++; 1091 } 1092 } 1093 1094 return copy_to_user(out, &vce_clk_table, 1095 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0; 1096 } 1097 case AMDGPU_INFO_VBIOS: { 1098 uint32_t bios_size = adev->bios_size; 1099 1100 switch (info->vbios_info.type) { 1101 case AMDGPU_INFO_VBIOS_SIZE: 1102 return copy_to_user(out, &bios_size, 1103 min((size_t)size, sizeof(bios_size))) 1104 ? -EFAULT : 0; 1105 case AMDGPU_INFO_VBIOS_IMAGE: { 1106 uint8_t *bios; 1107 uint32_t bios_offset = info->vbios_info.offset; 1108 1109 if (bios_offset >= bios_size) 1110 return -EINVAL; 1111 1112 bios = adev->bios + bios_offset; 1113 return copy_to_user(out, bios, 1114 min((size_t)size, (size_t)(bios_size - bios_offset))) 1115 ? -EFAULT : 0; 1116 } 1117 case AMDGPU_INFO_VBIOS_INFO: { 1118 struct drm_amdgpu_info_vbios vbios_info = {}; 1119 struct atom_context *atom_context; 1120 1121 atom_context = adev->mode_info.atom_context; 1122 if (atom_context) { 1123 memcpy(vbios_info.name, atom_context->name, 1124 sizeof(atom_context->name)); 1125 memcpy(vbios_info.vbios_pn, atom_context->vbios_pn, 1126 sizeof(atom_context->vbios_pn)); 1127 vbios_info.version = atom_context->version; 1128 memcpy(vbios_info.vbios_ver_str, atom_context->vbios_ver_str, 1129 sizeof(atom_context->vbios_ver_str)); 1130 memcpy(vbios_info.date, atom_context->date, 1131 sizeof(atom_context->date)); 1132 } 1133 1134 return copy_to_user(out, &vbios_info, 1135 min((size_t)size, sizeof(vbios_info))) ? -EFAULT : 0; 1136 } 1137 default: 1138 DRM_DEBUG_KMS("Invalid request %d\n", 1139 info->vbios_info.type); 1140 return -EINVAL; 1141 } 1142 } 1143 case AMDGPU_INFO_NUM_HANDLES: { 1144 struct drm_amdgpu_info_num_handles handle; 1145 1146 switch (info->query_hw_ip.type) { 1147 case AMDGPU_HW_IP_UVD: 1148 /* Starting Polaris, we support unlimited UVD handles */ 1149 if (adev->asic_type < CHIP_POLARIS10) { 1150 handle.uvd_max_handles = adev->uvd.max_handles; 1151 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev); 1152 1153 return copy_to_user(out, &handle, 1154 min((size_t)size, sizeof(handle))) ? -EFAULT : 0; 1155 } else { 1156 return -ENODATA; 1157 } 1158 1159 break; 1160 default: 1161 return -EINVAL; 1162 } 1163 } 1164 case AMDGPU_INFO_SENSOR: { 1165 if (!adev->pm.dpm_enabled) 1166 return -ENOENT; 1167 1168 switch (info->sensor_info.type) { 1169 case AMDGPU_INFO_SENSOR_GFX_SCLK: 1170 /* get sclk in Mhz */ 1171 if (amdgpu_dpm_read_sensor(adev, 1172 AMDGPU_PP_SENSOR_GFX_SCLK, 1173 (void *)&ui32, &ui32_size)) { 1174 return -EINVAL; 1175 } 1176 ui32 /= 100; 1177 break; 1178 case AMDGPU_INFO_SENSOR_GFX_MCLK: 1179 /* get mclk in Mhz */ 1180 if (amdgpu_dpm_read_sensor(adev, 1181 AMDGPU_PP_SENSOR_GFX_MCLK, 1182 (void *)&ui32, &ui32_size)) { 1183 return -EINVAL; 1184 } 1185 ui32 /= 100; 1186 break; 1187 case AMDGPU_INFO_SENSOR_GPU_TEMP: 1188 /* get temperature in millidegrees C */ 1189 if (amdgpu_dpm_read_sensor(adev, 1190 AMDGPU_PP_SENSOR_GPU_TEMP, 1191 (void *)&ui32, &ui32_size)) { 1192 return -EINVAL; 1193 } 1194 break; 1195 case AMDGPU_INFO_SENSOR_GPU_LOAD: 1196 /* get GPU load */ 1197 if (amdgpu_dpm_read_sensor(adev, 1198 AMDGPU_PP_SENSOR_GPU_LOAD, 1199 (void *)&ui32, &ui32_size)) { 1200 return -EINVAL; 1201 } 1202 break; 1203 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER: 1204 /* get average GPU power */ 1205 if (amdgpu_dpm_read_sensor(adev, 1206 AMDGPU_PP_SENSOR_GPU_AVG_POWER, 1207 (void *)&ui32, &ui32_size)) { 1208 /* fall back to input power for backwards compat */ 1209 if (amdgpu_dpm_read_sensor(adev, 1210 AMDGPU_PP_SENSOR_GPU_INPUT_POWER, 1211 (void *)&ui32, &ui32_size)) { 1212 return -EINVAL; 1213 } 1214 } 1215 ui32 /= MILLIWATT_PER_WATT; 1216 break; 1217 case AMDGPU_INFO_SENSOR_GPU_INPUT_POWER: 1218 /* get input GPU power */ 1219 if (amdgpu_dpm_read_sensor(adev, 1220 AMDGPU_PP_SENSOR_GPU_INPUT_POWER, 1221 (void *)&ui32, &ui32_size)) { 1222 return -EINVAL; 1223 } 1224 ui32 /= MILLIWATT_PER_WATT; 1225 break; 1226 case AMDGPU_INFO_SENSOR_VDDNB: 1227 /* get VDDNB in millivolts */ 1228 if (amdgpu_dpm_read_sensor(adev, 1229 AMDGPU_PP_SENSOR_VDDNB, 1230 (void *)&ui32, &ui32_size)) { 1231 return -EINVAL; 1232 } 1233 break; 1234 case AMDGPU_INFO_SENSOR_VDDGFX: 1235 /* get VDDGFX in millivolts */ 1236 if (amdgpu_dpm_read_sensor(adev, 1237 AMDGPU_PP_SENSOR_VDDGFX, 1238 (void *)&ui32, &ui32_size)) { 1239 return -EINVAL; 1240 } 1241 break; 1242 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK: 1243 /* get stable pstate sclk in Mhz */ 1244 if (amdgpu_dpm_read_sensor(adev, 1245 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 1246 (void *)&ui32, &ui32_size)) { 1247 return -EINVAL; 1248 } 1249 ui32 /= 100; 1250 break; 1251 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK: 1252 /* get stable pstate mclk in Mhz */ 1253 if (amdgpu_dpm_read_sensor(adev, 1254 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 1255 (void *)&ui32, &ui32_size)) { 1256 return -EINVAL; 1257 } 1258 ui32 /= 100; 1259 break; 1260 case AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK: 1261 /* get peak pstate sclk in Mhz */ 1262 if (amdgpu_dpm_read_sensor(adev, 1263 AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK, 1264 (void *)&ui32, &ui32_size)) { 1265 return -EINVAL; 1266 } 1267 ui32 /= 100; 1268 break; 1269 case AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK: 1270 /* get peak pstate mclk in Mhz */ 1271 if (amdgpu_dpm_read_sensor(adev, 1272 AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK, 1273 (void *)&ui32, &ui32_size)) { 1274 return -EINVAL; 1275 } 1276 ui32 /= 100; 1277 break; 1278 default: 1279 DRM_DEBUG_KMS("Invalid request %d\n", 1280 info->sensor_info.type); 1281 return -EINVAL; 1282 } 1283 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 1284 } 1285 case AMDGPU_INFO_VRAM_LOST_COUNTER: 1286 ui32 = atomic_read(&adev->vram_lost_counter); 1287 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 1288 case AMDGPU_INFO_RAS_ENABLED_FEATURES: { 1289 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1290 uint64_t ras_mask; 1291 1292 if (!ras) 1293 return -EINVAL; 1294 ras_mask = (uint64_t)adev->ras_enabled << 32 | ras->features; 1295 1296 return copy_to_user(out, &ras_mask, 1297 min_t(u64, size, sizeof(ras_mask))) ? 1298 -EFAULT : 0; 1299 } 1300 case AMDGPU_INFO_VIDEO_CAPS: { 1301 const struct amdgpu_video_codecs *codecs; 1302 struct drm_amdgpu_info_video_caps *caps; 1303 int r; 1304 1305 if (!adev->asic_funcs->query_video_codecs) 1306 return -EINVAL; 1307 1308 switch (info->video_cap.type) { 1309 case AMDGPU_INFO_VIDEO_CAPS_DECODE: 1310 r = amdgpu_asic_query_video_codecs(adev, false, &codecs); 1311 if (r) 1312 return -EINVAL; 1313 break; 1314 case AMDGPU_INFO_VIDEO_CAPS_ENCODE: 1315 r = amdgpu_asic_query_video_codecs(adev, true, &codecs); 1316 if (r) 1317 return -EINVAL; 1318 break; 1319 default: 1320 DRM_DEBUG_KMS("Invalid request %d\n", 1321 info->video_cap.type); 1322 return -EINVAL; 1323 } 1324 1325 caps = kzalloc_obj(*caps); 1326 if (!caps) 1327 return -ENOMEM; 1328 1329 for (i = 0; i < codecs->codec_count; i++) { 1330 int idx = codecs->codec_array[i].codec_type; 1331 1332 switch (idx) { 1333 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2: 1334 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4: 1335 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1: 1336 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC: 1337 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC: 1338 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG: 1339 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9: 1340 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1: 1341 caps->codec_info[idx].valid = 1; 1342 caps->codec_info[idx].max_width = 1343 codecs->codec_array[i].max_width; 1344 caps->codec_info[idx].max_height = 1345 codecs->codec_array[i].max_height; 1346 caps->codec_info[idx].max_pixels_per_frame = 1347 codecs->codec_array[i].max_pixels_per_frame; 1348 caps->codec_info[idx].max_level = 1349 codecs->codec_array[i].max_level; 1350 break; 1351 default: 1352 break; 1353 } 1354 } 1355 r = copy_to_user(out, caps, 1356 min((size_t)size, sizeof(*caps))) ? -EFAULT : 0; 1357 kfree(caps); 1358 return r; 1359 } 1360 case AMDGPU_INFO_MAX_IBS: { 1361 uint32_t max_ibs[AMDGPU_HW_IP_NUM]; 1362 1363 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) 1364 max_ibs[i] = amdgpu_ring_max_ibs(i); 1365 1366 return copy_to_user(out, max_ibs, 1367 min((size_t)size, sizeof(max_ibs))) ? -EFAULT : 0; 1368 } 1369 case AMDGPU_INFO_GPUVM_FAULT: { 1370 struct amdgpu_fpriv *fpriv = filp->driver_priv; 1371 struct amdgpu_vm *vm = &fpriv->vm; 1372 struct drm_amdgpu_info_gpuvm_fault gpuvm_fault; 1373 unsigned long flags; 1374 1375 if (!vm) 1376 return -EINVAL; 1377 1378 memset(&gpuvm_fault, 0, sizeof(gpuvm_fault)); 1379 1380 amdgpu_pasid_lock(&flags); 1381 gpuvm_fault.addr = vm->fault_info.addr; 1382 gpuvm_fault.status = vm->fault_info.status; 1383 gpuvm_fault.vmhub = vm->fault_info.vmhub; 1384 amdgpu_pasid_unlock(flags); 1385 1386 return copy_to_user(out, &gpuvm_fault, 1387 min((size_t)size, sizeof(gpuvm_fault))) ? -EFAULT : 0; 1388 } 1389 case AMDGPU_INFO_UQ_FW_AREAS: { 1390 struct drm_amdgpu_info_uq_metadata meta_info = {}; 1391 1392 switch (info->query_hw_ip.type) { 1393 case AMDGPU_HW_IP_GFX: 1394 ret = amdgpu_userq_metadata_info_gfx(adev, info, &meta_info.gfx); 1395 if (ret) 1396 return ret; 1397 1398 ret = copy_to_user(out, &meta_info, 1399 min((size_t)size, sizeof(meta_info))) ? -EFAULT : 0; 1400 return 0; 1401 case AMDGPU_HW_IP_COMPUTE: 1402 ret = amdgpu_userq_metadata_info_compute(adev, info, &meta_info.compute); 1403 if (ret) 1404 return ret; 1405 1406 ret = copy_to_user(out, &meta_info, 1407 min((size_t)size, sizeof(meta_info))) ? -EFAULT : 0; 1408 return 0; 1409 case AMDGPU_HW_IP_DMA: 1410 ret = amdgpu_userq_metadata_info_sdma(adev, info, &meta_info.sdma); 1411 if (ret) 1412 return ret; 1413 1414 ret = copy_to_user(out, &meta_info, 1415 min((size_t)size, sizeof(meta_info))) ? -EFAULT : 0; 1416 return 0; 1417 default: 1418 return -EINVAL; 1419 } 1420 } 1421 default: 1422 DRM_DEBUG_KMS("Invalid request %d\n", info->query); 1423 return -EINVAL; 1424 } 1425 return 0; 1426 } 1427 1428 /** 1429 * amdgpu_proc_options_ioctl - set per-fd user options 1430 * 1431 * @dev: drm dev pointer 1432 * @data: pointer to struct drm_amdgpu_proc_options 1433 * @filp: drm file 1434 * 1435 * Sets options stored on the per-file amdgpu_fpriv. Currently the only 1436 * supported option is %AMDGPU_PROC_OPTIONS_OP_KFD_SIGBUS_DELAY which 1437 * controls how KFD delivers SIGBUS for poison/RAS events to the calling 1438 * process (immediate, suppressed, or delayed by N milliseconds). 1439 */ 1440 int amdgpu_proc_options_ioctl(struct drm_device *dev, void *data, 1441 struct drm_file *filp) 1442 { 1443 struct drm_amdgpu_proc_options *args = data; 1444 1445 switch (args->op) { 1446 case AMDGPU_PROC_OPTIONS_OP_KFD_SIGBUS_DELAY: 1447 return amdgpu_amdkfd_set_sigbus_delay(current, 1448 args->kfd_sigbus_delay.value); 1449 default: 1450 DRM_DEBUG_KMS("Invalid user option op %u\n", args->op); 1451 return -EINVAL; 1452 } 1453 } 1454 1455 /** 1456 * amdgpu_driver_open_kms - drm callback for open 1457 * 1458 * @dev: drm dev pointer 1459 * @file_priv: drm file 1460 * 1461 * On device open, init vm on cayman+ (all asics). 1462 * Returns 0 on success, error on failure. 1463 */ 1464 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 1465 { 1466 struct amdgpu_device *adev = drm_to_adev(dev); 1467 struct amdgpu_fpriv *fpriv; 1468 struct drm_exec exec; 1469 int r, pasid = 0; 1470 1471 /* Ensure IB tests are run on ring */ 1472 flush_delayed_work(&adev->delayed_init_work); 1473 1474 1475 if (amdgpu_ras_intr_triggered()) { 1476 DRM_ERROR("RAS Intr triggered, device disabled!!"); 1477 return -EHWPOISON; 1478 } 1479 1480 file_priv->driver_priv = NULL; 1481 1482 r = pm_runtime_get_sync(dev->dev); 1483 if (r < 0) 1484 goto pm_put; 1485 1486 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 1487 if (unlikely(!fpriv)) { 1488 r = -ENOMEM; 1489 goto out_suspend; 1490 } 1491 1492 r = amdgpu_xcp_open_device(adev, fpriv, file_priv); 1493 if (r) 1494 goto error_pasid; 1495 1496 amdgpu_debugfs_vm_init(file_priv); 1497 1498 r = amdgpu_vm_init(adev, &fpriv->vm, fpriv->xcp_id); 1499 if (r) 1500 goto error_pasid; 1501 1502 pasid = amdgpu_pasid_alloc(16, fpriv); 1503 if (pasid < 0) { 1504 dev_warn(adev->dev, "No more PASIDs available!"); 1505 pasid = 0; 1506 } 1507 fpriv->vm.pasid = pasid; 1508 1509 drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES, 0); 1510 drm_exec_until_all_locked(&exec) { 1511 r = amdgpu_vm_lock_pd(&fpriv->vm, &exec, 0); 1512 drm_exec_retry_on_contention(&exec); 1513 if (unlikely(r)) 1514 goto error_vm; 1515 } 1516 1517 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL); 1518 drm_exec_fini(&exec); 1519 if (!fpriv->prt_va) { 1520 r = -ENOMEM; 1521 goto error_vm; 1522 } 1523 1524 if (adev->gfx.mcbp) { 1525 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK; 1526 1527 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj, 1528 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE); 1529 if (r) 1530 goto error_vm; 1531 } 1532 1533 r = amdgpu_seq64_map(adev, &fpriv->vm, &fpriv->seq64_va); 1534 if (r) 1535 goto error_vm; 1536 1537 xa_init_flags(&fpriv->bo_list_handles, XA_FLAGS_ALLOC1); 1538 1539 r = amdgpu_userq_mgr_init(&fpriv->userq_mgr, file_priv, adev); 1540 if (r) 1541 drm_warn(adev_to_drm(adev), 1542 "Failed to init usermode queue manager (%d), use legacy workload submission only\n", 1543 r); 1544 1545 amdgpu_evf_mgr_init(&fpriv->evf_mgr); 1546 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr, adev); 1547 1548 file_priv->driver_priv = fpriv; 1549 goto out_suspend; 1550 1551 error_vm: 1552 if (pasid) { 1553 amdgpu_pasid_free(pasid); 1554 pasid = 0; 1555 } 1556 1557 amdgpu_vm_fini(adev, &fpriv->vm); 1558 1559 error_pasid: 1560 kfree(fpriv); 1561 1562 out_suspend: 1563 pm_put: 1564 pm_runtime_put_autosuspend(dev->dev); 1565 1566 return r; 1567 } 1568 1569 /** 1570 * amdgpu_driver_postclose_kms - drm callback for post close 1571 * 1572 * @dev: drm dev pointer 1573 * @file_priv: drm file 1574 * 1575 * On device post close, tear down vm on cayman+ (all asics). 1576 */ 1577 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1578 struct drm_file *file_priv) 1579 { 1580 struct amdgpu_device *adev = drm_to_adev(dev); 1581 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1582 struct amdgpu_bo_list *list; 1583 struct amdgpu_bo *pd; 1584 unsigned long handle; 1585 u32 pasid; 1586 1587 if (!fpriv) 1588 return; 1589 1590 pm_runtime_get_sync(dev->dev); 1591 1592 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL) 1593 amdgpu_uvd_free_handles(adev, file_priv); 1594 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL) 1595 amdgpu_vce_free_handles(adev, file_priv); 1596 1597 if (fpriv->csa_va) { 1598 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK; 1599 1600 WARN_ON(amdgpu_unmap_static_csa(adev, &fpriv->vm, adev->virt.csa_obj, 1601 fpriv->csa_va, csa_addr)); 1602 fpriv->csa_va = NULL; 1603 } 1604 1605 amdgpu_seq64_unmap(adev, fpriv); 1606 1607 pasid = fpriv->vm.pasid; 1608 pd = amdgpu_bo_ref(fpriv->vm.root.bo); 1609 if (!WARN_ON(amdgpu_bo_reserve(pd, true))) { 1610 amdgpu_vm_bo_del(adev, fpriv->prt_va); 1611 amdgpu_bo_unreserve(pd); 1612 } 1613 1614 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); 1615 1616 if (pasid) 1617 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid); 1618 1619 amdgpu_vm_fini(adev, &fpriv->vm); 1620 amdgpu_bo_unref(&pd); 1621 1622 xa_for_each(&fpriv->bo_list_handles, handle, list) 1623 amdgpu_bo_list_put(list); 1624 xa_destroy(&fpriv->bo_list_handles); 1625 1626 kfree(fpriv); 1627 file_priv->driver_priv = NULL; 1628 1629 pm_runtime_put_autosuspend(dev->dev); 1630 } 1631 1632 1633 void amdgpu_driver_release_kms(struct drm_device *dev) 1634 { 1635 struct amdgpu_device *adev = drm_to_adev(dev); 1636 1637 amdgpu_device_fini_sw(adev); 1638 pci_set_drvdata(adev->pdev, NULL); 1639 } 1640 1641 /* 1642 * VBlank related functions. 1643 */ 1644 /** 1645 * amdgpu_get_vblank_counter_kms - get frame count 1646 * 1647 * @crtc: crtc to get the frame count from 1648 * 1649 * Gets the frame count on the requested crtc (all asics). 1650 * Returns frame count on success, -EINVAL on failure. 1651 */ 1652 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc) 1653 { 1654 struct drm_device *dev = crtc->dev; 1655 unsigned int pipe = crtc->index; 1656 struct amdgpu_device *adev = drm_to_adev(dev); 1657 int vpos, hpos, stat; 1658 u32 count; 1659 1660 if (pipe >= adev->mode_info.num_crtc) { 1661 DRM_ERROR("Invalid crtc %u\n", pipe); 1662 return -EINVAL; 1663 } 1664 if (!down_read_trylock(&adev->reset_domain->sem)) 1665 return drm_crtc_vblank_count(crtc); 1666 1667 1668 /* The hw increments its frame counter at start of vsync, not at start 1669 * of vblank, as is required by DRM core vblank counter handling. 1670 * Cook the hw count here to make it appear to the caller as if it 1671 * incremented at start of vblank. We measure distance to start of 1672 * vblank in vpos. vpos therefore will be >= 0 between start of vblank 1673 * and start of vsync, so vpos >= 0 means to bump the hw frame counter 1674 * result by 1 to give the proper appearance to caller. 1675 */ 1676 if (adev->mode_info.crtcs[pipe]) { 1677 /* Repeat readout if needed to provide stable result if 1678 * we cross start of vsync during the queries. 1679 */ 1680 do { 1681 count = amdgpu_display_vblank_get_counter(adev, pipe); 1682 /* Ask amdgpu_display_get_crtc_scanoutpos to return 1683 * vpos as distance to start of vblank, instead of 1684 * regular vertical scanout pos. 1685 */ 1686 stat = amdgpu_display_get_crtc_scanoutpos( 1687 dev, pipe, GET_DISTANCE_TO_VBLANKSTART, 1688 &vpos, &hpos, NULL, NULL, 1689 &adev->mode_info.crtcs[pipe]->base.hwmode); 1690 } while (count != amdgpu_display_vblank_get_counter(adev, pipe)); 1691 1692 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 1693 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 1694 DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 1695 } else { 1696 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", 1697 pipe, vpos); 1698 1699 /* Bump counter if we are at >= leading edge of vblank, 1700 * but before vsync where vpos would turn negative and 1701 * the hw counter really increments. 1702 */ 1703 if (vpos >= 0) 1704 count++; 1705 } 1706 } else { 1707 /* Fallback to use value as is. */ 1708 count = amdgpu_display_vblank_get_counter(adev, pipe); 1709 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 1710 } 1711 1712 up_read(&adev->reset_domain->sem); 1713 return count; 1714 } 1715 1716 /** 1717 * amdgpu_enable_vblank_kms - enable vblank interrupt 1718 * 1719 * @crtc: crtc to enable vblank interrupt for 1720 * 1721 * Enable the interrupt on the requested crtc (all asics). 1722 * Returns 0 on success, -EINVAL on failure. 1723 */ 1724 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc) 1725 { 1726 struct drm_device *dev = crtc->dev; 1727 unsigned int pipe = crtc->index; 1728 struct amdgpu_device *adev = drm_to_adev(dev); 1729 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1730 1731 return amdgpu_irq_get(adev, &adev->crtc_irq, idx); 1732 } 1733 1734 /** 1735 * amdgpu_disable_vblank_kms - disable vblank interrupt 1736 * 1737 * @crtc: crtc to disable vblank interrupt for 1738 * 1739 * Disable the interrupt on the requested crtc (all asics). 1740 */ 1741 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc) 1742 { 1743 struct drm_device *dev = crtc->dev; 1744 unsigned int pipe = crtc->index; 1745 struct amdgpu_device *adev = drm_to_adev(dev); 1746 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1747 1748 amdgpu_irq_put(adev, &adev->crtc_irq, idx); 1749 } 1750 1751 /* 1752 * Debugfs info 1753 */ 1754 #if defined(CONFIG_DEBUG_FS) 1755 1756 static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused) 1757 { 1758 struct amdgpu_device *adev = m->private; 1759 struct drm_amdgpu_info_firmware fw_info; 1760 struct drm_amdgpu_query_fw query_fw; 1761 struct atom_context *ctx = adev->mode_info.atom_context; 1762 uint8_t smu_program, smu_major, smu_minor, smu_debug; 1763 int ret, i; 1764 1765 static const char *ta_fw_name[TA_FW_TYPE_MAX_INDEX] = { 1766 #define TA_FW_NAME(type)[TA_FW_TYPE_PSP_##type] = #type 1767 TA_FW_NAME(XGMI), 1768 TA_FW_NAME(RAS), 1769 TA_FW_NAME(HDCP), 1770 TA_FW_NAME(DTM), 1771 TA_FW_NAME(RAP), 1772 TA_FW_NAME(SECUREDISPLAY), 1773 #undef TA_FW_NAME 1774 }; 1775 1776 /* VCE */ 1777 query_fw.fw_type = AMDGPU_INFO_FW_VCE; 1778 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1779 if (ret) 1780 return ret; 1781 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n", 1782 fw_info.feature, fw_info.ver); 1783 1784 /* UVD */ 1785 query_fw.fw_type = AMDGPU_INFO_FW_UVD; 1786 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1787 if (ret) 1788 return ret; 1789 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n", 1790 fw_info.feature, fw_info.ver); 1791 1792 /* GMC */ 1793 query_fw.fw_type = AMDGPU_INFO_FW_GMC; 1794 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1795 if (ret) 1796 return ret; 1797 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n", 1798 fw_info.feature, fw_info.ver); 1799 1800 /* ME */ 1801 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME; 1802 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1803 if (ret) 1804 return ret; 1805 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n", 1806 fw_info.feature, fw_info.ver); 1807 1808 /* PFP */ 1809 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP; 1810 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1811 if (ret) 1812 return ret; 1813 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n", 1814 fw_info.feature, fw_info.ver); 1815 1816 /* CE */ 1817 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE; 1818 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1819 if (ret) 1820 return ret; 1821 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n", 1822 fw_info.feature, fw_info.ver); 1823 1824 /* RLC */ 1825 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC; 1826 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1827 if (ret) 1828 return ret; 1829 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n", 1830 fw_info.feature, fw_info.ver); 1831 1832 /* RLC SAVE RESTORE LIST CNTL */ 1833 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL; 1834 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1835 if (ret) 1836 return ret; 1837 seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n", 1838 fw_info.feature, fw_info.ver); 1839 1840 /* RLC SAVE RESTORE LIST GPM MEM */ 1841 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM; 1842 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1843 if (ret) 1844 return ret; 1845 seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n", 1846 fw_info.feature, fw_info.ver); 1847 1848 /* RLC SAVE RESTORE LIST SRM MEM */ 1849 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM; 1850 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1851 if (ret) 1852 return ret; 1853 seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n", 1854 fw_info.feature, fw_info.ver); 1855 1856 /* RLCP */ 1857 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCP; 1858 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1859 if (ret) 1860 return ret; 1861 seq_printf(m, "RLCP feature version: %u, firmware version: 0x%08x\n", 1862 fw_info.feature, fw_info.ver); 1863 1864 /* RLCV */ 1865 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCV; 1866 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1867 if (ret) 1868 return ret; 1869 seq_printf(m, "RLCV feature version: %u, firmware version: 0x%08x\n", 1870 fw_info.feature, fw_info.ver); 1871 1872 /* MEC */ 1873 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC; 1874 query_fw.index = 0; 1875 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1876 if (ret) 1877 return ret; 1878 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n", 1879 fw_info.feature, fw_info.ver); 1880 1881 /* MEC2 */ 1882 if (adev->gfx.mec2_fw) { 1883 query_fw.index = 1; 1884 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1885 if (ret) 1886 return ret; 1887 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n", 1888 fw_info.feature, fw_info.ver); 1889 } 1890 1891 /* IMU */ 1892 query_fw.fw_type = AMDGPU_INFO_FW_IMU; 1893 query_fw.index = 0; 1894 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1895 if (ret) 1896 return ret; 1897 seq_printf(m, "IMU feature version: %u, firmware version: 0x%08x\n", 1898 fw_info.feature, fw_info.ver); 1899 1900 /* PSP SOS */ 1901 query_fw.fw_type = AMDGPU_INFO_FW_SOS; 1902 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1903 if (ret) 1904 return ret; 1905 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n", 1906 fw_info.feature, fw_info.ver); 1907 1908 1909 /* PSP ASD */ 1910 query_fw.fw_type = AMDGPU_INFO_FW_ASD; 1911 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1912 if (ret) 1913 return ret; 1914 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n", 1915 fw_info.feature, fw_info.ver); 1916 1917 query_fw.fw_type = AMDGPU_INFO_FW_TA; 1918 for (i = TA_FW_TYPE_PSP_XGMI; i < TA_FW_TYPE_MAX_INDEX; i++) { 1919 query_fw.index = i; 1920 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1921 if (ret) 1922 continue; 1923 1924 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n", 1925 ta_fw_name[i], fw_info.feature, fw_info.ver); 1926 } 1927 1928 /* SMC */ 1929 query_fw.fw_type = AMDGPU_INFO_FW_SMC; 1930 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1931 if (ret) 1932 return ret; 1933 smu_program = (fw_info.ver >> 24) & 0xff; 1934 smu_major = (fw_info.ver >> 16) & 0xff; 1935 smu_minor = (fw_info.ver >> 8) & 0xff; 1936 smu_debug = (fw_info.ver >> 0) & 0xff; 1937 seq_printf(m, "SMC feature version: %u, program: %d, firmware version: 0x%08x (%d.%d.%d)\n", 1938 fw_info.feature, smu_program, fw_info.ver, smu_major, smu_minor, smu_debug); 1939 1940 /* SDMA */ 1941 query_fw.fw_type = AMDGPU_INFO_FW_SDMA; 1942 for (i = 0; i < adev->sdma.num_instances; i++) { 1943 query_fw.index = i; 1944 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1945 if (ret) 1946 return ret; 1947 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n", 1948 i, fw_info.feature, fw_info.ver); 1949 } 1950 1951 /* VCN */ 1952 query_fw.fw_type = AMDGPU_INFO_FW_VCN; 1953 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1954 if (ret) 1955 return ret; 1956 seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n", 1957 fw_info.feature, fw_info.ver); 1958 1959 /* DMCU */ 1960 query_fw.fw_type = AMDGPU_INFO_FW_DMCU; 1961 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1962 if (ret) 1963 return ret; 1964 seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n", 1965 fw_info.feature, fw_info.ver); 1966 1967 /* DMCUB */ 1968 query_fw.fw_type = AMDGPU_INFO_FW_DMCUB; 1969 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1970 if (ret) 1971 return ret; 1972 seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n", 1973 fw_info.feature, fw_info.ver); 1974 1975 /* TOC */ 1976 query_fw.fw_type = AMDGPU_INFO_FW_TOC; 1977 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1978 if (ret) 1979 return ret; 1980 seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n", 1981 fw_info.feature, fw_info.ver); 1982 1983 /* CAP */ 1984 if (adev->psp.cap_fw) { 1985 query_fw.fw_type = AMDGPU_INFO_FW_CAP; 1986 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1987 if (ret) 1988 return ret; 1989 seq_printf(m, "CAP feature version: %u, firmware version: 0x%08x\n", 1990 fw_info.feature, fw_info.ver); 1991 } 1992 1993 /* MES_KIQ */ 1994 query_fw.fw_type = AMDGPU_INFO_FW_MES_KIQ; 1995 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1996 if (ret) 1997 return ret; 1998 seq_printf(m, "MES_KIQ feature version: %u, firmware version: 0x%08x\n", 1999 fw_info.feature, fw_info.ver); 2000 2001 /* MES */ 2002 query_fw.fw_type = AMDGPU_INFO_FW_MES; 2003 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 2004 if (ret) 2005 return ret; 2006 seq_printf(m, "MES feature version: %u, firmware version: 0x%08x\n", 2007 fw_info.feature, fw_info.ver); 2008 2009 /* VPE */ 2010 query_fw.fw_type = AMDGPU_INFO_FW_VPE; 2011 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 2012 if (ret) 2013 return ret; 2014 seq_printf(m, "VPE feature version: %u, firmware version: 0x%08x\n", 2015 fw_info.feature, fw_info.ver); 2016 2017 seq_printf(m, "VBIOS version: %s\n", ctx->vbios_pn); 2018 2019 return 0; 2020 } 2021 2022 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_firmware_info); 2023 2024 #endif 2025 2026 void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev) 2027 { 2028 #if defined(CONFIG_DEBUG_FS) 2029 struct drm_minor *minor = adev_to_drm(adev)->primary; 2030 struct dentry *root = minor->debugfs_root; 2031 2032 debugfs_create_file("amdgpu_firmware_info", 0444, root, 2033 adev, &amdgpu_debugfs_firmware_info_fops); 2034 2035 #endif 2036 } 2037