1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_JPEG_H__ 25 #define __AMDGPU_JPEG_H__ 26 27 #include "amdgpu_ras.h" 28 29 #define AMDGPU_MAX_JPEG_INSTANCES 4 30 #define AMDGPU_MAX_JPEG_RINGS 8 31 32 #define AMDGPU_JPEG_HARVEST_JPEG0 (1 << 0) 33 #define AMDGPU_JPEG_HARVEST_JPEG1 (1 << 1) 34 35 #define WREG32_SOC15_JPEG_DPG_MODE(inst_idx, offset, value, indirect) \ 36 do { \ 37 if (!indirect) { \ 38 WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \ 39 mmUVD_DPG_LMA_DATA, value); \ 40 WREG32_SOC15( \ 41 JPEG, GET_INST(JPEG, inst_idx), \ 42 mmUVD_DPG_LMA_CTL, \ 43 (UVD_DPG_LMA_CTL__READ_WRITE_MASK | \ 44 offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT | \ 45 indirect << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \ 46 } else { \ 47 *adev->jpeg.inst[inst_idx].dpg_sram_curr_addr++ = \ 48 offset; \ 49 *adev->jpeg.inst[inst_idx].dpg_sram_curr_addr++ = \ 50 value; \ 51 } \ 52 } while (0) 53 54 #define RREG32_SOC15_JPEG_DPG_MODE(inst_idx, offset, mask_en) \ 55 ({ \ 56 WREG32_SOC15(JPEG, inst_idx, mmUVD_DPG_LMA_CTL, \ 57 (0x0 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT | \ 58 mask_en << UVD_DPG_LMA_CTL__MASK_EN__SHIFT | \ 59 offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)); \ 60 RREG32_SOC15(JPEG, inst_idx, mmUVD_DPG_LMA_DATA); \ 61 }) 62 63 struct amdgpu_jpeg_reg{ 64 unsigned jpeg_pitch[AMDGPU_MAX_JPEG_RINGS]; 65 }; 66 67 struct amdgpu_jpeg_inst { 68 struct amdgpu_ring ring_dec[AMDGPU_MAX_JPEG_RINGS]; 69 struct amdgpu_irq_src irq; 70 struct amdgpu_irq_src ras_poison_irq; 71 struct amdgpu_jpeg_reg external; 72 struct amdgpu_bo *dpg_sram_bo; 73 struct dpg_pause_state pause_state; 74 void *dpg_sram_cpu_addr; 75 uint64_t dpg_sram_gpu_addr; 76 uint32_t *dpg_sram_curr_addr; 77 uint8_t aid_id; 78 }; 79 80 struct amdgpu_jpeg_ras { 81 struct amdgpu_ras_block_object ras_block; 82 }; 83 84 struct amdgpu_jpeg { 85 uint8_t num_jpeg_inst; 86 struct amdgpu_jpeg_inst inst[AMDGPU_MAX_JPEG_INSTANCES]; 87 unsigned num_jpeg_rings; 88 struct amdgpu_jpeg_reg internal; 89 unsigned harvest_config; 90 struct delayed_work idle_work; 91 enum amd_powergating_state cur_state; 92 struct mutex jpeg_pg_lock; 93 atomic_t total_submission_cnt; 94 struct ras_common_if *ras_if; 95 struct amdgpu_jpeg_ras *ras; 96 97 uint16_t inst_mask; 98 uint8_t num_inst_per_aid; 99 bool indirect_sram; 100 }; 101 102 int amdgpu_jpeg_sw_init(struct amdgpu_device *adev); 103 int amdgpu_jpeg_sw_fini(struct amdgpu_device *adev); 104 int amdgpu_jpeg_suspend(struct amdgpu_device *adev); 105 int amdgpu_jpeg_resume(struct amdgpu_device *adev); 106 107 void amdgpu_jpeg_ring_begin_use(struct amdgpu_ring *ring); 108 void amdgpu_jpeg_ring_end_use(struct amdgpu_ring *ring); 109 110 int amdgpu_jpeg_dec_ring_test_ring(struct amdgpu_ring *ring); 111 int amdgpu_jpeg_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout); 112 113 int amdgpu_jpeg_process_poison_irq(struct amdgpu_device *adev, 114 struct amdgpu_irq_src *source, 115 struct amdgpu_iv_entry *entry); 116 int amdgpu_jpeg_ras_late_init(struct amdgpu_device *adev, 117 struct ras_common_if *ras_block); 118 int amdgpu_jpeg_ras_sw_init(struct amdgpu_device *adev); 119 int amdgpu_jpeg_psp_update_sram(struct amdgpu_device *adev, int inst_idx, 120 enum AMDGPU_UCODE_ID ucode_id); 121 122 #endif /*__AMDGPU_JPEG_H__*/ 123