xref: /linux/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c (revision d728fd03e5f2117853d91b3626d434a97fe896d1)
1 /*
2  * Copyright 2019 Advanced Micro Devices, Inc.
3  * All Rights Reserved.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the
7  * "Software"), to deal in the Software without restriction, including
8  * without limitation the rights to use, copy, modify, merge, publish,
9  * distribute, sub license, and/or sell copies of the Software, and to
10  * permit persons to whom the Software is furnished to do so, subject to
11  * the following conditions:
12  *
13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
20  *
21  * The above copyright notice and this permission notice (including the
22  * next paragraph) shall be included in all copies or substantial portions
23  * of the Software.
24  *
25  */
26 
27 #include "amdgpu.h"
28 #include "amdgpu_jpeg.h"
29 #include "amdgpu_pm.h"
30 #include "soc15d.h"
31 #include "soc15_common.h"
32 
33 #define JPEG_IDLE_TIMEOUT	msecs_to_jiffies(1000)
34 
35 static void amdgpu_jpeg_idle_work_handler(struct work_struct *work);
36 static void amdgpu_jpeg_reg_dump_fini(struct amdgpu_device *adev);
37 
38 int amdgpu_jpeg_sw_init(struct amdgpu_device *adev)
39 {
40 	int i, r;
41 
42 	INIT_DELAYED_WORK(&adev->jpeg.idle_work, amdgpu_jpeg_idle_work_handler);
43 	mutex_init(&adev->jpeg.jpeg_pg_lock);
44 	atomic_set(&adev->jpeg.total_submission_cnt, 0);
45 
46 	if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
47 	    (adev->pg_flags & AMD_PG_SUPPORT_JPEG_DPG))
48 		adev->jpeg.indirect_sram = true;
49 
50 	for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
51 		if (adev->jpeg.harvest_config & (1U << i))
52 			continue;
53 
54 		if (adev->jpeg.indirect_sram) {
55 			r = amdgpu_bo_create_kernel(adev, 64 * 2 * 4, PAGE_SIZE,
56 					AMDGPU_GEM_DOMAIN_VRAM |
57 					AMDGPU_GEM_DOMAIN_GTT,
58 					&adev->jpeg.inst[i].dpg_sram_bo,
59 					&adev->jpeg.inst[i].dpg_sram_gpu_addr,
60 					&adev->jpeg.inst[i].dpg_sram_cpu_addr);
61 			if (r) {
62 				dev_err(adev->dev,
63 				"JPEG %d (%d) failed to allocate DPG bo\n", i, r);
64 				return r;
65 			}
66 		}
67 	}
68 
69 	return 0;
70 }
71 
72 int amdgpu_jpeg_sw_fini(struct amdgpu_device *adev)
73 {
74 	int i, j;
75 
76 	for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
77 		if (adev->jpeg.harvest_config & (1U << i))
78 			continue;
79 
80 		amdgpu_bo_free_kernel(
81 			&adev->jpeg.inst[i].dpg_sram_bo,
82 			&adev->jpeg.inst[i].dpg_sram_gpu_addr,
83 			(void **)&adev->jpeg.inst[i].dpg_sram_cpu_addr);
84 
85 		for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j)
86 			amdgpu_ring_fini(&adev->jpeg.inst[i].ring_dec[j]);
87 	}
88 
89 	if (adev->jpeg.reg_list)
90 		amdgpu_jpeg_reg_dump_fini(adev);
91 
92 	mutex_destroy(&adev->jpeg.jpeg_pg_lock);
93 
94 	return 0;
95 }
96 
97 int amdgpu_jpeg_suspend(struct amdgpu_device *adev)
98 {
99 	cancel_delayed_work_sync(&adev->jpeg.idle_work);
100 
101 	return 0;
102 }
103 
104 int amdgpu_jpeg_resume(struct amdgpu_device *adev)
105 {
106 	return 0;
107 }
108 
109 static void amdgpu_jpeg_idle_work_handler(struct work_struct *work)
110 {
111 	struct amdgpu_device *adev =
112 		container_of(work, struct amdgpu_device, jpeg.idle_work.work);
113 	unsigned int fences = 0;
114 	unsigned int i, j;
115 
116 	for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
117 		if (adev->jpeg.harvest_config & (1U << i))
118 			continue;
119 
120 		for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j)
121 			fences += amdgpu_fence_count_emitted(&adev->jpeg.inst[i].ring_dec[j]);
122 	}
123 
124 	if (!fences && !atomic_read(&adev->jpeg.total_submission_cnt)) {
125 		mutex_lock(&adev->jpeg.jpeg_pg_lock);
126 		amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_JPEG,
127 						       AMD_PG_STATE_GATE);
128 		mutex_unlock(&adev->jpeg.jpeg_pg_lock);
129 	} else
130 		schedule_delayed_work(&adev->jpeg.idle_work, JPEG_IDLE_TIMEOUT);
131 }
132 
133 void amdgpu_jpeg_ring_begin_use(struct amdgpu_ring *ring)
134 {
135 	struct amdgpu_device *adev = ring->adev;
136 
137 	atomic_inc(&adev->jpeg.total_submission_cnt);
138 	cancel_delayed_work_sync(&adev->jpeg.idle_work);
139 
140 	mutex_lock(&adev->jpeg.jpeg_pg_lock);
141 	amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_JPEG,
142 						       AMD_PG_STATE_UNGATE);
143 	mutex_unlock(&adev->jpeg.jpeg_pg_lock);
144 }
145 
146 void amdgpu_jpeg_ring_end_use(struct amdgpu_ring *ring)
147 {
148 	atomic_dec(&ring->adev->jpeg.total_submission_cnt);
149 	schedule_delayed_work(&ring->adev->jpeg.idle_work, JPEG_IDLE_TIMEOUT);
150 }
151 
152 int amdgpu_jpeg_dec_ring_test_ring(struct amdgpu_ring *ring)
153 {
154 	struct amdgpu_device *adev = ring->adev;
155 	uint32_t tmp = 0;
156 	unsigned i;
157 	int r;
158 
159 	/* JPEG in SRIOV does not support direct register read/write */
160 	if (amdgpu_sriov_vf(adev))
161 		return 0;
162 
163 	r = amdgpu_ring_alloc(ring, 3);
164 	if (r)
165 		return r;
166 
167 	WREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch[ring->pipe], 0xCAFEDEAD);
168 	/* Add a read register to make sure the write register is executed. */
169 	RREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch[ring->pipe]);
170 
171 	amdgpu_ring_write(ring, PACKET0(adev->jpeg.internal.jpeg_pitch[ring->pipe], 0));
172 	amdgpu_ring_write(ring, 0xABADCAFE);
173 	amdgpu_ring_commit(ring);
174 
175 	for (i = 0; i < adev->usec_timeout; i++) {
176 		tmp = RREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch[ring->pipe]);
177 		if (tmp == 0xABADCAFE)
178 			break;
179 		udelay(1);
180 	}
181 
182 	if (i >= adev->usec_timeout)
183 		r = -ETIMEDOUT;
184 
185 	return r;
186 }
187 
188 static int amdgpu_jpeg_dec_set_reg(struct amdgpu_ring *ring, uint32_t handle,
189 		struct dma_fence **fence)
190 {
191 	struct amdgpu_device *adev = ring->adev;
192 	struct amdgpu_job *job;
193 	struct amdgpu_ib *ib;
194 	struct dma_fence *f = NULL;
195 	const unsigned ib_size_dw = 16;
196 	int i, r;
197 
198 	r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, ib_size_dw * 4,
199 				     AMDGPU_IB_POOL_DIRECT, &job);
200 	if (r)
201 		return r;
202 
203 	ib = &job->ibs[0];
204 
205 	ib->ptr[0] = PACKETJ(adev->jpeg.internal.jpeg_pitch[ring->pipe], 0, 0, PACKETJ_TYPE0);
206 	ib->ptr[1] = 0xDEADBEEF;
207 	for (i = 2; i < 16; i += 2) {
208 		ib->ptr[i] = PACKETJ(0, 0, 0, PACKETJ_TYPE6);
209 		ib->ptr[i+1] = 0;
210 	}
211 	ib->length_dw = 16;
212 
213 	r = amdgpu_job_submit_direct(job, ring, &f);
214 	if (r)
215 		goto err;
216 
217 	if (fence)
218 		*fence = dma_fence_get(f);
219 	dma_fence_put(f);
220 
221 	return 0;
222 
223 err:
224 	amdgpu_job_free(job);
225 	return r;
226 }
227 
228 int amdgpu_jpeg_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
229 {
230 	struct amdgpu_device *adev = ring->adev;
231 	uint32_t tmp = 0;
232 	unsigned i;
233 	struct dma_fence *fence = NULL;
234 	long r = 0;
235 
236 	r = amdgpu_jpeg_dec_set_reg(ring, 1, &fence);
237 	if (r)
238 		goto error;
239 
240 	r = dma_fence_wait_timeout(fence, false, timeout);
241 	if (r == 0) {
242 		r = -ETIMEDOUT;
243 		goto error;
244 	} else if (r < 0) {
245 		goto error;
246 	} else {
247 		r = 0;
248 	}
249 
250 	if (!amdgpu_sriov_vf(adev)) {
251 		for (i = 0; i < adev->usec_timeout; i++) {
252 			tmp = RREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch[ring->pipe]);
253 			if (tmp == 0xDEADBEEF)
254 				break;
255 			udelay(1);
256 			if (amdgpu_emu_mode == 1)
257 				udelay(10);
258 		}
259 
260 		if (i >= adev->usec_timeout)
261 			r = -ETIMEDOUT;
262 	}
263 
264 	dma_fence_put(fence);
265 error:
266 	return r;
267 }
268 
269 int amdgpu_jpeg_process_poison_irq(struct amdgpu_device *adev,
270 				struct amdgpu_irq_src *source,
271 				struct amdgpu_iv_entry *entry)
272 {
273 	struct ras_common_if *ras_if = adev->jpeg.ras_if;
274 	struct ras_dispatch_if ih_data = {
275 		.entry = entry,
276 	};
277 
278 	if (!ras_if)
279 		return 0;
280 
281 	ih_data.head = *ras_if;
282 	amdgpu_ras_interrupt_dispatch(adev, &ih_data);
283 
284 	return 0;
285 }
286 
287 int amdgpu_jpeg_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
288 {
289 	int r, i;
290 
291 	r = amdgpu_ras_block_late_init(adev, ras_block);
292 	if (r)
293 		return r;
294 
295 	if (amdgpu_ras_is_supported(adev, ras_block->block)) {
296 		for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
297 			if (adev->jpeg.harvest_config & (1 << i) ||
298 			    !adev->jpeg.inst[i].ras_poison_irq.funcs)
299 				continue;
300 
301 			r = amdgpu_irq_get(adev, &adev->jpeg.inst[i].ras_poison_irq, 0);
302 			if (r)
303 				goto late_fini;
304 		}
305 	}
306 	return 0;
307 
308 late_fini:
309 	amdgpu_ras_block_late_fini(adev, ras_block);
310 	return r;
311 }
312 
313 int amdgpu_jpeg_ras_sw_init(struct amdgpu_device *adev)
314 {
315 	int err;
316 	struct amdgpu_jpeg_ras *ras;
317 
318 	if (!adev->jpeg.ras)
319 		return 0;
320 
321 	ras = adev->jpeg.ras;
322 	err = amdgpu_ras_register_ras_block(adev, &ras->ras_block);
323 	if (err) {
324 		dev_err(adev->dev, "Failed to register jpeg ras block!\n");
325 		return err;
326 	}
327 
328 	strcpy(ras->ras_block.ras_comm.name, "jpeg");
329 	ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__JPEG;
330 	ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__POISON;
331 	adev->jpeg.ras_if = &ras->ras_block.ras_comm;
332 
333 	if (!ras->ras_block.ras_late_init)
334 		ras->ras_block.ras_late_init = amdgpu_jpeg_ras_late_init;
335 
336 	return 0;
337 }
338 
339 int amdgpu_jpeg_psp_update_sram(struct amdgpu_device *adev, int inst_idx,
340 			       enum AMDGPU_UCODE_ID ucode_id)
341 {
342 	struct amdgpu_firmware_info ucode = {
343 		.ucode_id = AMDGPU_UCODE_ID_JPEG_RAM,
344 		.mc_addr = adev->jpeg.inst[inst_idx].dpg_sram_gpu_addr,
345 		.ucode_size = ((uintptr_t)adev->jpeg.inst[inst_idx].dpg_sram_curr_addr -
346 			      (uintptr_t)adev->jpeg.inst[inst_idx].dpg_sram_cpu_addr),
347 	};
348 
349 	return psp_execute_ip_fw_load(&adev->psp, &ucode);
350 }
351 
352 /*
353  * debugfs for to enable/disable jpeg job submission to specific core.
354  */
355 #if defined(CONFIG_DEBUG_FS)
356 static int amdgpu_debugfs_jpeg_sched_mask_set(void *data, u64 val)
357 {
358 	struct amdgpu_device *adev = (struct amdgpu_device *)data;
359 	u32 i, j;
360 	u64 mask = 0;
361 	struct amdgpu_ring *ring;
362 
363 	if (!adev)
364 		return -ENODEV;
365 
366 	mask = (1ULL << (adev->jpeg.num_jpeg_inst * adev->jpeg.num_jpeg_rings)) - 1;
367 	if ((val & mask) == 0)
368 		return -EINVAL;
369 
370 	for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
371 		for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {
372 			ring = &adev->jpeg.inst[i].ring_dec[j];
373 			if (val & (1 << ((i * adev->jpeg.num_jpeg_rings) + j)))
374 				ring->sched.ready = true;
375 			else
376 				ring->sched.ready = false;
377 		}
378 	}
379 	/* publish sched.ready flag update effective immediately across smp */
380 	smp_rmb();
381 	return 0;
382 }
383 
384 static int amdgpu_debugfs_jpeg_sched_mask_get(void *data, u64 *val)
385 {
386 	struct amdgpu_device *adev = (struct amdgpu_device *)data;
387 	u32 i, j;
388 	u64 mask = 0;
389 	struct amdgpu_ring *ring;
390 
391 	if (!adev)
392 		return -ENODEV;
393 	for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
394 		for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {
395 			ring = &adev->jpeg.inst[i].ring_dec[j];
396 			if (ring->sched.ready)
397 				mask |= 1ULL << ((i * adev->jpeg.num_jpeg_rings) + j);
398 		}
399 	}
400 	*val = mask;
401 	return 0;
402 }
403 
404 DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_debugfs_jpeg_sched_mask_fops,
405 			 amdgpu_debugfs_jpeg_sched_mask_get,
406 			 amdgpu_debugfs_jpeg_sched_mask_set, "%llx\n");
407 
408 #endif
409 
410 void amdgpu_debugfs_jpeg_sched_mask_init(struct amdgpu_device *adev)
411 {
412 #if defined(CONFIG_DEBUG_FS)
413 	struct drm_minor *minor = adev_to_drm(adev)->primary;
414 	struct dentry *root = minor->debugfs_root;
415 	char name[32];
416 
417 	if (!(adev->jpeg.num_jpeg_inst > 1) && !(adev->jpeg.num_jpeg_rings > 1))
418 		return;
419 	sprintf(name, "amdgpu_jpeg_sched_mask");
420 	debugfs_create_file(name, 0600, root, adev,
421 			    &amdgpu_debugfs_jpeg_sched_mask_fops);
422 #endif
423 }
424 
425 static ssize_t amdgpu_get_jpeg_reset_mask(struct device *dev,
426 						struct device_attribute *attr,
427 						char *buf)
428 {
429 	struct drm_device *ddev = dev_get_drvdata(dev);
430 	struct amdgpu_device *adev = drm_to_adev(ddev);
431 
432 	if (!adev)
433 		return -ENODEV;
434 
435 	return amdgpu_show_reset_mask(buf, adev->jpeg.supported_reset);
436 }
437 
438 static DEVICE_ATTR(jpeg_reset_mask, 0444,
439 		   amdgpu_get_jpeg_reset_mask, NULL);
440 
441 int amdgpu_jpeg_sysfs_reset_mask_init(struct amdgpu_device *adev)
442 {
443 	int r = 0;
444 
445 	if (adev->jpeg.num_jpeg_inst) {
446 		r = device_create_file(adev->dev, &dev_attr_jpeg_reset_mask);
447 		if (r)
448 			return r;
449 	}
450 
451 	return r;
452 }
453 
454 void amdgpu_jpeg_sysfs_reset_mask_fini(struct amdgpu_device *adev)
455 {
456 	if (adev->dev->kobj.sd) {
457 		if (adev->jpeg.num_jpeg_inst)
458 			device_remove_file(adev->dev, &dev_attr_jpeg_reset_mask);
459 	}
460 }
461 
462 int amdgpu_jpeg_reg_dump_init(struct amdgpu_device *adev,
463 			       const struct amdgpu_hwip_reg_entry *reg, u32 count)
464 {
465 	adev->jpeg.ip_dump = kcalloc(adev->jpeg.num_jpeg_inst * count,
466 				     sizeof(uint32_t), GFP_KERNEL);
467 	if (!adev->jpeg.ip_dump) {
468 		dev_err(adev->dev,
469 			"Failed to allocate memory for JPEG IP Dump\n");
470 		return -ENOMEM;
471 	}
472 	adev->jpeg.reg_list = reg;
473 	adev->jpeg.reg_count = count;
474 
475 	return 0;
476 }
477 
478 static void amdgpu_jpeg_reg_dump_fini(struct amdgpu_device *adev)
479 {
480 	kfree(adev->jpeg.ip_dump);
481 	adev->jpeg.reg_list = NULL;
482 	adev->jpeg.reg_count = 0;
483 }
484 
485 void amdgpu_jpeg_dump_ip_state(struct amdgpu_ip_block *ip_block)
486 {
487 	struct amdgpu_device *adev = ip_block->adev;
488 	u32 inst_off, inst_id, is_powered;
489 	int i, j;
490 
491 	if (!adev->jpeg.ip_dump)
492 		return;
493 
494 	for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
495 		if (adev->jpeg.harvest_config & (1 << i))
496 			continue;
497 
498 		inst_id = GET_INST(JPEG, i);
499 		inst_off = i * adev->jpeg.reg_count;
500 		/* check power status from UVD_JPEG_POWER_STATUS */
501 		adev->jpeg.ip_dump[inst_off] =
502 			RREG32(SOC15_REG_ENTRY_OFFSET_INST(adev->jpeg.reg_list[0],
503 							   inst_id));
504 		is_powered = ((adev->jpeg.ip_dump[inst_off] & 0x1) != 1);
505 
506 		if (is_powered)
507 			for (j = 1; j < adev->jpeg.reg_count; j++)
508 				adev->jpeg.ip_dump[inst_off + j] =
509 					RREG32(SOC15_REG_ENTRY_OFFSET_INST(adev->jpeg.reg_list[j],
510 									   inst_id));
511 	}
512 }
513 
514 void amdgpu_jpeg_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
515 {
516 	struct amdgpu_device *adev = ip_block->adev;
517 	u32 inst_off, is_powered;
518 	int i, j;
519 
520 	if (!adev->jpeg.ip_dump)
521 		return;
522 
523 	drm_printf(p, "num_instances:%d\n", adev->jpeg.num_jpeg_inst);
524 	for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
525 		if (adev->jpeg.harvest_config & (1 << i)) {
526 			drm_printf(p, "\nHarvested Instance:JPEG%d Skipping dump\n", i);
527 			continue;
528 		}
529 
530 		inst_off = i * adev->jpeg.reg_count;
531 		is_powered = ((adev->jpeg.ip_dump[inst_off] & 0x1) != 1);
532 
533 		if (is_powered) {
534 			drm_printf(p, "Active Instance:JPEG%d\n", i);
535 			for (j = 0; j < adev->jpeg.reg_count; j++)
536 				drm_printf(p, "%-50s \t 0x%08x\n", adev->jpeg.reg_list[j].reg_name,
537 					   adev->jpeg.ip_dump[inst_off + j]);
538 		} else
539 			drm_printf(p, "\nInactive Instance:JPEG%d\n", i);
540 	}
541 }
542