xref: /linux/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c (revision 7f4f3b14e8079ecde096bd734af10e30d40c27b7) 
1 /*
2  * Copyright 2019 Advanced Micro Devices, Inc.
3  * All Rights Reserved.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the
7  * "Software"), to deal in the Software without restriction, including
8  * without limitation the rights to use, copy, modify, merge, publish,
9  * distribute, sub license, and/or sell copies of the Software, and to
10  * permit persons to whom the Software is furnished to do so, subject to
11  * the following conditions:
12  *
13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
20  *
21  * The above copyright notice and this permission notice (including the
22  * next paragraph) shall be included in all copies or substantial portions
23  * of the Software.
24  *
25  */
26 
27 #include "amdgpu.h"
28 #include "amdgpu_jpeg.h"
29 #include "amdgpu_pm.h"
30 #include "soc15d.h"
31 #include "soc15_common.h"
32 
33 #define JPEG_IDLE_TIMEOUT	msecs_to_jiffies(1000)
34 
35 static void amdgpu_jpeg_idle_work_handler(struct work_struct *work);
36 
37 int amdgpu_jpeg_sw_init(struct amdgpu_device *adev)
38 {
39 	int i, r;
40 
41 	INIT_DELAYED_WORK(&adev->jpeg.idle_work, amdgpu_jpeg_idle_work_handler);
42 	mutex_init(&adev->jpeg.jpeg_pg_lock);
43 	atomic_set(&adev->jpeg.total_submission_cnt, 0);
44 
45 	if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
46 	    (adev->pg_flags & AMD_PG_SUPPORT_JPEG_DPG))
47 		adev->jpeg.indirect_sram = true;
48 
49 	for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
50 		if (adev->jpeg.harvest_config & (1U << i))
51 			continue;
52 
53 		if (adev->jpeg.indirect_sram) {
54 			r = amdgpu_bo_create_kernel(adev, 64 * 2 * 4, PAGE_SIZE,
55 					AMDGPU_GEM_DOMAIN_VRAM |
56 					AMDGPU_GEM_DOMAIN_GTT,
57 					&adev->jpeg.inst[i].dpg_sram_bo,
58 					&adev->jpeg.inst[i].dpg_sram_gpu_addr,
59 					&adev->jpeg.inst[i].dpg_sram_cpu_addr);
60 			if (r) {
61 				dev_err(adev->dev,
62 				"JPEG %d (%d) failed to allocate DPG bo\n", i, r);
63 				return r;
64 			}
65 		}
66 	}
67 
68 	return 0;
69 }
70 
71 int amdgpu_jpeg_sw_fini(struct amdgpu_device *adev)
72 {
73 	int i, j;
74 
75 	for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
76 		if (adev->jpeg.harvest_config & (1U << i))
77 			continue;
78 
79 		amdgpu_bo_free_kernel(
80 			&adev->jpeg.inst[i].dpg_sram_bo,
81 			&adev->jpeg.inst[i].dpg_sram_gpu_addr,
82 			(void **)&adev->jpeg.inst[i].dpg_sram_cpu_addr);
83 
84 		for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j)
85 			amdgpu_ring_fini(&adev->jpeg.inst[i].ring_dec[j]);
86 	}
87 
88 	mutex_destroy(&adev->jpeg.jpeg_pg_lock);
89 
90 	return 0;
91 }
92 
93 int amdgpu_jpeg_suspend(struct amdgpu_device *adev)
94 {
95 	cancel_delayed_work_sync(&adev->jpeg.idle_work);
96 
97 	return 0;
98 }
99 
100 int amdgpu_jpeg_resume(struct amdgpu_device *adev)
101 {
102 	return 0;
103 }
104 
105 static void amdgpu_jpeg_idle_work_handler(struct work_struct *work)
106 {
107 	struct amdgpu_device *adev =
108 		container_of(work, struct amdgpu_device, jpeg.idle_work.work);
109 	unsigned int fences = 0;
110 	unsigned int i, j;
111 
112 	for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
113 		if (adev->jpeg.harvest_config & (1U << i))
114 			continue;
115 
116 		for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j)
117 			fences += amdgpu_fence_count_emitted(&adev->jpeg.inst[i].ring_dec[j]);
118 	}
119 
120 	if (!fences && !atomic_read(&adev->jpeg.total_submission_cnt))
121 		amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_JPEG,
122 						       AMD_PG_STATE_GATE);
123 	else
124 		schedule_delayed_work(&adev->jpeg.idle_work, JPEG_IDLE_TIMEOUT);
125 }
126 
127 void amdgpu_jpeg_ring_begin_use(struct amdgpu_ring *ring)
128 {
129 	struct amdgpu_device *adev = ring->adev;
130 
131 	atomic_inc(&adev->jpeg.total_submission_cnt);
132 	cancel_delayed_work_sync(&adev->jpeg.idle_work);
133 
134 	mutex_lock(&adev->jpeg.jpeg_pg_lock);
135 	amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_JPEG,
136 						       AMD_PG_STATE_UNGATE);
137 	mutex_unlock(&adev->jpeg.jpeg_pg_lock);
138 }
139 
140 void amdgpu_jpeg_ring_end_use(struct amdgpu_ring *ring)
141 {
142 	atomic_dec(&ring->adev->jpeg.total_submission_cnt);
143 	schedule_delayed_work(&ring->adev->jpeg.idle_work, JPEG_IDLE_TIMEOUT);
144 }
145 
146 int amdgpu_jpeg_dec_ring_test_ring(struct amdgpu_ring *ring)
147 {
148 	struct amdgpu_device *adev = ring->adev;
149 	uint32_t tmp = 0;
150 	unsigned i;
151 	int r;
152 
153 	/* JPEG in SRIOV does not support direct register read/write */
154 	if (amdgpu_sriov_vf(adev))
155 		return 0;
156 
157 	r = amdgpu_ring_alloc(ring, 3);
158 	if (r)
159 		return r;
160 
161 	WREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch[ring->pipe], 0xCAFEDEAD);
162 	/* Add a read register to make sure the write register is executed. */
163 	RREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch[ring->pipe]);
164 
165 	amdgpu_ring_write(ring, PACKET0(adev->jpeg.internal.jpeg_pitch[ring->pipe], 0));
166 	amdgpu_ring_write(ring, 0xABADCAFE);
167 	amdgpu_ring_commit(ring);
168 
169 	for (i = 0; i < adev->usec_timeout; i++) {
170 		tmp = RREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch[ring->pipe]);
171 		if (tmp == 0xABADCAFE)
172 			break;
173 		udelay(1);
174 	}
175 
176 	if (i >= adev->usec_timeout)
177 		r = -ETIMEDOUT;
178 
179 	return r;
180 }
181 
182 static int amdgpu_jpeg_dec_set_reg(struct amdgpu_ring *ring, uint32_t handle,
183 		struct dma_fence **fence)
184 {
185 	struct amdgpu_device *adev = ring->adev;
186 	struct amdgpu_job *job;
187 	struct amdgpu_ib *ib;
188 	struct dma_fence *f = NULL;
189 	const unsigned ib_size_dw = 16;
190 	int i, r;
191 
192 	r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, ib_size_dw * 4,
193 				     AMDGPU_IB_POOL_DIRECT, &job);
194 	if (r)
195 		return r;
196 
197 	ib = &job->ibs[0];
198 
199 	ib->ptr[0] = PACKETJ(adev->jpeg.internal.jpeg_pitch[ring->pipe], 0, 0, PACKETJ_TYPE0);
200 	ib->ptr[1] = 0xDEADBEEF;
201 	for (i = 2; i < 16; i += 2) {
202 		ib->ptr[i] = PACKETJ(0, 0, 0, PACKETJ_TYPE6);
203 		ib->ptr[i+1] = 0;
204 	}
205 	ib->length_dw = 16;
206 
207 	r = amdgpu_job_submit_direct(job, ring, &f);
208 	if (r)
209 		goto err;
210 
211 	if (fence)
212 		*fence = dma_fence_get(f);
213 	dma_fence_put(f);
214 
215 	return 0;
216 
217 err:
218 	amdgpu_job_free(job);
219 	return r;
220 }
221 
222 int amdgpu_jpeg_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
223 {
224 	struct amdgpu_device *adev = ring->adev;
225 	uint32_t tmp = 0;
226 	unsigned i;
227 	struct dma_fence *fence = NULL;
228 	long r = 0;
229 
230 	r = amdgpu_jpeg_dec_set_reg(ring, 1, &fence);
231 	if (r)
232 		goto error;
233 
234 	r = dma_fence_wait_timeout(fence, false, timeout);
235 	if (r == 0) {
236 		r = -ETIMEDOUT;
237 		goto error;
238 	} else if (r < 0) {
239 		goto error;
240 	} else {
241 		r = 0;
242 	}
243 
244 	if (!amdgpu_sriov_vf(adev)) {
245 		for (i = 0; i < adev->usec_timeout; i++) {
246 			tmp = RREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch[ring->pipe]);
247 			if (tmp == 0xDEADBEEF)
248 				break;
249 			udelay(1);
250 			if (amdgpu_emu_mode == 1)
251 				udelay(10);
252 		}
253 
254 		if (i >= adev->usec_timeout)
255 			r = -ETIMEDOUT;
256 	}
257 
258 	dma_fence_put(fence);
259 error:
260 	return r;
261 }
262 
263 int amdgpu_jpeg_process_poison_irq(struct amdgpu_device *adev,
264 				struct amdgpu_irq_src *source,
265 				struct amdgpu_iv_entry *entry)
266 {
267 	struct ras_common_if *ras_if = adev->jpeg.ras_if;
268 	struct ras_dispatch_if ih_data = {
269 		.entry = entry,
270 	};
271 
272 	if (!ras_if)
273 		return 0;
274 
275 	ih_data.head = *ras_if;
276 	amdgpu_ras_interrupt_dispatch(adev, &ih_data);
277 
278 	return 0;
279 }
280 
281 int amdgpu_jpeg_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
282 {
283 	int r, i;
284 
285 	r = amdgpu_ras_block_late_init(adev, ras_block);
286 	if (r)
287 		return r;
288 
289 	if (amdgpu_ras_is_supported(adev, ras_block->block)) {
290 		for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
291 			if (adev->jpeg.harvest_config & (1 << i) ||
292 			    !adev->jpeg.inst[i].ras_poison_irq.funcs)
293 				continue;
294 
295 			r = amdgpu_irq_get(adev, &adev->jpeg.inst[i].ras_poison_irq, 0);
296 			if (r)
297 				goto late_fini;
298 		}
299 	}
300 	return 0;
301 
302 late_fini:
303 	amdgpu_ras_block_late_fini(adev, ras_block);
304 	return r;
305 }
306 
307 int amdgpu_jpeg_ras_sw_init(struct amdgpu_device *adev)
308 {
309 	int err;
310 	struct amdgpu_jpeg_ras *ras;
311 
312 	if (!adev->jpeg.ras)
313 		return 0;
314 
315 	ras = adev->jpeg.ras;
316 	err = amdgpu_ras_register_ras_block(adev, &ras->ras_block);
317 	if (err) {
318 		dev_err(adev->dev, "Failed to register jpeg ras block!\n");
319 		return err;
320 	}
321 
322 	strcpy(ras->ras_block.ras_comm.name, "jpeg");
323 	ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__JPEG;
324 	ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__POISON;
325 	adev->jpeg.ras_if = &ras->ras_block.ras_comm;
326 
327 	if (!ras->ras_block.ras_late_init)
328 		ras->ras_block.ras_late_init = amdgpu_jpeg_ras_late_init;
329 
330 	return 0;
331 }
332 
333 int amdgpu_jpeg_psp_update_sram(struct amdgpu_device *adev, int inst_idx,
334 			       enum AMDGPU_UCODE_ID ucode_id)
335 {
336 	struct amdgpu_firmware_info ucode = {
337 		.ucode_id = AMDGPU_UCODE_ID_JPEG_RAM,
338 		.mc_addr = adev->jpeg.inst[inst_idx].dpg_sram_gpu_addr,
339 		.ucode_size = ((uintptr_t)adev->jpeg.inst[inst_idx].dpg_sram_curr_addr -
340 			      (uintptr_t)adev->jpeg.inst[inst_idx].dpg_sram_cpu_addr),
341 	};
342 
343 	return psp_execute_ip_fw_load(&adev->psp, &ucode);
344 }
345 
346 /*
347  * debugfs for to enable/disable jpeg job submission to specific core.
348  */
349 #if defined(CONFIG_DEBUG_FS)
350 static int amdgpu_debugfs_jpeg_sched_mask_set(void *data, u64 val)
351 {
352 	struct amdgpu_device *adev = (struct amdgpu_device *)data;
353 	u32 i, j;
354 	u64 mask = 0;
355 	struct amdgpu_ring *ring;
356 
357 	if (!adev)
358 		return -ENODEV;
359 
360 	mask = (1ULL << (adev->jpeg.num_jpeg_inst * adev->jpeg.num_jpeg_rings)) - 1;
361 	if ((val & mask) == 0)
362 		return -EINVAL;
363 
364 	for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
365 		for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {
366 			ring = &adev->jpeg.inst[i].ring_dec[j];
367 			if (val & (1 << ((i * adev->jpeg.num_jpeg_rings) + j)))
368 				ring->sched.ready = true;
369 			else
370 				ring->sched.ready = false;
371 		}
372 	}
373 	/* publish sched.ready flag update effective immediately across smp */
374 	smp_rmb();
375 	return 0;
376 }
377 
378 static int amdgpu_debugfs_jpeg_sched_mask_get(void *data, u64 *val)
379 {
380 	struct amdgpu_device *adev = (struct amdgpu_device *)data;
381 	u32 i, j;
382 	u64 mask = 0;
383 	struct amdgpu_ring *ring;
384 
385 	if (!adev)
386 		return -ENODEV;
387 	for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
388 		for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {
389 			ring = &adev->jpeg.inst[i].ring_dec[j];
390 			if (ring->sched.ready)
391 				mask |= 1ULL << ((i * adev->jpeg.num_jpeg_rings) + j);
392 		}
393 	}
394 	*val = mask;
395 	return 0;
396 }
397 
398 DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_debugfs_jpeg_sched_mask_fops,
399 			 amdgpu_debugfs_jpeg_sched_mask_get,
400 			 amdgpu_debugfs_jpeg_sched_mask_set, "%llx\n");
401 
402 #endif
403 
404 void amdgpu_debugfs_jpeg_sched_mask_init(struct amdgpu_device *adev)
405 {
406 #if defined(CONFIG_DEBUG_FS)
407 	struct drm_minor *minor = adev_to_drm(adev)->primary;
408 	struct dentry *root = minor->debugfs_root;
409 	char name[32];
410 
411 	if (!(adev->jpeg.num_jpeg_inst > 1) && !(adev->jpeg.num_jpeg_rings > 1))
412 		return;
413 	sprintf(name, "amdgpu_jpeg_sched_mask");
414 	debugfs_create_file(name, 0600, root, adev,
415 			    &amdgpu_debugfs_jpeg_sched_mask_fops);
416 #endif
417 }
418 
419 static ssize_t amdgpu_get_jpeg_reset_mask(struct device *dev,
420 						struct device_attribute *attr,
421 						char *buf)
422 {
423 	struct drm_device *ddev = dev_get_drvdata(dev);
424 	struct amdgpu_device *adev = drm_to_adev(ddev);
425 
426 	if (!adev)
427 		return -ENODEV;
428 
429 	return amdgpu_show_reset_mask(buf, adev->jpeg.supported_reset);
430 }
431 
432 static DEVICE_ATTR(jpeg_reset_mask, 0444,
433 		   amdgpu_get_jpeg_reset_mask, NULL);
434 
435 int amdgpu_jpeg_sysfs_reset_mask_init(struct amdgpu_device *adev)
436 {
437 	int r = 0;
438 
439 	if (adev->jpeg.num_jpeg_inst) {
440 		r = device_create_file(adev->dev, &dev_attr_jpeg_reset_mask);
441 		if (r)
442 			return r;
443 	}
444 
445 	return r;
446 }
447 
448 void amdgpu_jpeg_sysfs_reset_mask_fini(struct amdgpu_device *adev)
449 {
450 	if (adev->jpeg.num_jpeg_inst)
451 		device_remove_file(adev->dev, &dev_attr_jpeg_reset_mask);
452 }
453