1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * 23 */ 24 #include <linux/kthread.h> 25 #include <linux/wait.h> 26 #include <linux/sched.h> 27 #include <drm/drmP.h> 28 #include "amdgpu.h" 29 #include "amdgpu_trace.h" 30 31 static void amdgpu_job_timedout(struct amd_sched_job *s_job) 32 { 33 struct amdgpu_job *job = container_of(s_job, struct amdgpu_job, base); 34 35 DRM_ERROR("ring %s timeout, last signaled seq=%u, last emitted seq=%u\n", 36 job->base.sched->name, 37 atomic_read(&job->ring->fence_drv.last_seq), 38 job->ring->fence_drv.sync_seq); 39 amdgpu_gpu_reset(job->adev); 40 } 41 42 int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs, 43 struct amdgpu_job **job, struct amdgpu_vm *vm) 44 { 45 size_t size = sizeof(struct amdgpu_job); 46 47 if (num_ibs == 0) 48 return -EINVAL; 49 50 size += sizeof(struct amdgpu_ib) * num_ibs; 51 52 *job = kzalloc(size, GFP_KERNEL); 53 if (!*job) 54 return -ENOMEM; 55 56 (*job)->adev = adev; 57 (*job)->vm = vm; 58 (*job)->ibs = (void *)&(*job)[1]; 59 (*job)->num_ibs = num_ibs; 60 (*job)->need_pipeline_sync = false; 61 62 amdgpu_sync_create(&(*job)->sync); 63 64 return 0; 65 } 66 67 int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size, 68 struct amdgpu_job **job) 69 { 70 int r; 71 72 r = amdgpu_job_alloc(adev, 1, job, NULL); 73 if (r) 74 return r; 75 76 r = amdgpu_ib_get(adev, NULL, size, &(*job)->ibs[0]); 77 if (r) 78 kfree(*job); 79 80 return r; 81 } 82 83 void amdgpu_job_free_resources(struct amdgpu_job *job) 84 { 85 struct dma_fence *f; 86 unsigned i; 87 88 /* use sched fence if available */ 89 f = job->base.s_fence ? &job->base.s_fence->finished : job->fence; 90 91 for (i = 0; i < job->num_ibs; ++i) 92 amdgpu_ib_free(job->adev, &job->ibs[i], f); 93 } 94 95 static void amdgpu_job_free_cb(struct amd_sched_job *s_job) 96 { 97 struct amdgpu_job *job = container_of(s_job, struct amdgpu_job, base); 98 99 dma_fence_put(job->fence); 100 amdgpu_sync_free(&job->sync); 101 kfree(job); 102 } 103 104 void amdgpu_job_free(struct amdgpu_job *job) 105 { 106 amdgpu_job_free_resources(job); 107 108 dma_fence_put(job->fence); 109 amdgpu_sync_free(&job->sync); 110 kfree(job); 111 } 112 113 int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring, 114 struct amd_sched_entity *entity, void *owner, 115 struct dma_fence **f) 116 { 117 int r; 118 job->ring = ring; 119 120 if (!f) 121 return -EINVAL; 122 123 r = amd_sched_job_init(&job->base, &ring->sched, entity, owner); 124 if (r) 125 return r; 126 127 job->owner = owner; 128 job->fence_ctx = entity->fence_context; 129 *f = dma_fence_get(&job->base.s_fence->finished); 130 amdgpu_job_free_resources(job); 131 amd_sched_entity_push_job(&job->base); 132 133 return 0; 134 } 135 136 static struct dma_fence *amdgpu_job_dependency(struct amd_sched_job *sched_job) 137 { 138 struct amdgpu_job *job = to_amdgpu_job(sched_job); 139 struct amdgpu_vm *vm = job->vm; 140 141 struct dma_fence *fence = amdgpu_sync_get_fence(&job->sync); 142 143 while (fence == NULL && vm && !job->vm_id) { 144 struct amdgpu_ring *ring = job->ring; 145 int r; 146 147 r = amdgpu_vm_grab_id(vm, ring, &job->sync, 148 &job->base.s_fence->finished, 149 job); 150 if (r) 151 DRM_ERROR("Error getting VM ID (%d)\n", r); 152 153 fence = amdgpu_sync_get_fence(&job->sync); 154 } 155 156 if (amd_sched_dependency_optimized(fence, sched_job->s_entity)) 157 job->need_pipeline_sync = true; 158 159 return fence; 160 } 161 162 static struct dma_fence *amdgpu_job_run(struct amd_sched_job *sched_job) 163 { 164 struct dma_fence *fence = NULL; 165 struct amdgpu_job *job; 166 int r; 167 168 if (!sched_job) { 169 DRM_ERROR("job is null\n"); 170 return NULL; 171 } 172 job = to_amdgpu_job(sched_job); 173 174 BUG_ON(amdgpu_sync_peek_fence(&job->sync, NULL)); 175 176 trace_amdgpu_sched_run_job(job); 177 r = amdgpu_ib_schedule(job->ring, job->num_ibs, job->ibs, job, &fence); 178 if (r) 179 DRM_ERROR("Error scheduling IBs (%d)\n", r); 180 181 /* if gpu reset, hw fence will be replaced here */ 182 dma_fence_put(job->fence); 183 job->fence = dma_fence_get(fence); 184 amdgpu_job_free_resources(job); 185 return fence; 186 } 187 188 const struct amd_sched_backend_ops amdgpu_sched_ops = { 189 .dependency = amdgpu_job_dependency, 190 .run_job = amdgpu_job_run, 191 .timedout_job = amdgpu_job_timedout, 192 .free_job = amdgpu_job_free_cb 193 }; 194