1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * 23 */ 24 #include <linux/kthread.h> 25 #include <linux/wait.h> 26 #include <linux/sched.h> 27 28 #include <drm/drm_drv.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_trace.h" 32 #include "amdgpu_reset.h" 33 #include "amdgpu_dev_coredump.h" 34 #include "amdgpu_xgmi.h" 35 36 static void amdgpu_job_do_core_dump(struct amdgpu_device *adev, 37 struct amdgpu_job *job) 38 { 39 int i; 40 41 dev_info(adev->dev, "Dumping IP State\n"); 42 for (i = 0; i < adev->num_ip_blocks; i++) 43 if (adev->ip_blocks[i].version->funcs->dump_ip_state) 44 adev->ip_blocks[i].version->funcs 45 ->dump_ip_state((void *)&adev->ip_blocks[i]); 46 dev_info(adev->dev, "Dumping IP State Completed\n"); 47 48 amdgpu_coredump(adev, true, false, job); 49 } 50 51 static void amdgpu_job_core_dump(struct amdgpu_device *adev, 52 struct amdgpu_job *job) 53 { 54 struct list_head device_list, *device_list_handle = NULL; 55 struct amdgpu_device *tmp_adev = NULL; 56 struct amdgpu_hive_info *hive = NULL; 57 58 if (!amdgpu_sriov_vf(adev)) 59 hive = amdgpu_get_xgmi_hive(adev); 60 if (hive) 61 mutex_lock(&hive->hive_lock); 62 /* 63 * Reuse the logic in amdgpu_device_gpu_recover() to build list of 64 * devices for code dump 65 */ 66 INIT_LIST_HEAD(&device_list); 67 if (!amdgpu_sriov_vf(adev) && (adev->gmc.xgmi.num_physical_nodes > 1) && hive) { 68 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) 69 list_add_tail(&tmp_adev->reset_list, &device_list); 70 if (!list_is_first(&adev->reset_list, &device_list)) 71 list_rotate_to_front(&adev->reset_list, &device_list); 72 device_list_handle = &device_list; 73 } else { 74 list_add_tail(&adev->reset_list, &device_list); 75 device_list_handle = &device_list; 76 } 77 78 /* Do the coredump for each device */ 79 list_for_each_entry(tmp_adev, device_list_handle, reset_list) 80 amdgpu_job_do_core_dump(tmp_adev, job); 81 82 if (hive) { 83 mutex_unlock(&hive->hive_lock); 84 amdgpu_put_xgmi_hive(hive); 85 } 86 } 87 88 static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job) 89 { 90 struct amdgpu_ring *ring = to_amdgpu_ring(s_job->sched); 91 struct amdgpu_job *job = to_amdgpu_job(s_job); 92 struct amdgpu_task_info *ti; 93 struct amdgpu_device *adev = ring->adev; 94 int idx; 95 int r; 96 97 if (!drm_dev_enter(adev_to_drm(adev), &idx)) { 98 dev_info(adev->dev, "%s - device unplugged skipping recovery on scheduler:%s", 99 __func__, s_job->sched->name); 100 101 /* Effectively the job is aborted as the device is gone */ 102 return DRM_GPU_SCHED_STAT_ENODEV; 103 } 104 105 adev->job_hang = true; 106 107 /* 108 * Do the coredump immediately after a job timeout to get a very 109 * close dump/snapshot/representation of GPU's current error status 110 * Skip it for SRIOV, since VF FLR will be triggered by host driver 111 * before job timeout 112 */ 113 if (!amdgpu_sriov_vf(adev)) 114 amdgpu_job_core_dump(adev, job); 115 116 if (amdgpu_gpu_recovery && 117 amdgpu_ring_soft_recovery(ring, job->vmid, s_job->s_fence->parent)) { 118 dev_err(adev->dev, "ring %s timeout, but soft recovered\n", 119 s_job->sched->name); 120 goto exit; 121 } 122 123 dev_err(adev->dev, "ring %s timeout, signaled seq=%u, emitted seq=%u\n", 124 job->base.sched->name, atomic_read(&ring->fence_drv.last_seq), 125 ring->fence_drv.sync_seq); 126 127 ti = amdgpu_vm_get_task_info_pasid(ring->adev, job->pasid); 128 if (ti) { 129 dev_err(adev->dev, 130 "Process information: process %s pid %d thread %s pid %d\n", 131 ti->process_name, ti->tgid, ti->task_name, ti->pid); 132 amdgpu_vm_put_task_info(ti); 133 } 134 135 dma_fence_set_error(&s_job->s_fence->finished, -ETIME); 136 137 /* attempt a per ring reset */ 138 if (amdgpu_gpu_recovery && 139 ring->funcs->reset) { 140 dev_err(adev->dev, "Starting %s ring reset\n", s_job->sched->name); 141 /* stop the scheduler, but don't mess with the 142 * bad job yet because if ring reset fails 143 * we'll fall back to full GPU reset. 144 */ 145 drm_sched_wqueue_stop(&ring->sched); 146 r = amdgpu_ring_reset(ring, job->vmid); 147 if (!r) { 148 if (amdgpu_ring_sched_ready(ring)) 149 drm_sched_stop(&ring->sched, s_job); 150 atomic_inc(&ring->adev->gpu_reset_counter); 151 amdgpu_fence_driver_force_completion(ring); 152 if (amdgpu_ring_sched_ready(ring)) 153 drm_sched_start(&ring->sched); 154 dev_err(adev->dev, "Ring %s reset success\n", ring->sched.name); 155 goto exit; 156 } 157 dev_err(adev->dev, "Ring %s reset failure\n", ring->sched.name); 158 } 159 160 if (amdgpu_device_should_recover_gpu(ring->adev)) { 161 struct amdgpu_reset_context reset_context; 162 memset(&reset_context, 0, sizeof(reset_context)); 163 164 reset_context.method = AMD_RESET_METHOD_NONE; 165 reset_context.reset_req_dev = adev; 166 reset_context.src = AMDGPU_RESET_SRC_JOB; 167 clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 168 169 /* 170 * To avoid an unnecessary extra coredump, as we have already 171 * got the very close representation of GPU's error status 172 */ 173 set_bit(AMDGPU_SKIP_COREDUMP, &reset_context.flags); 174 175 r = amdgpu_device_gpu_recover(ring->adev, job, &reset_context); 176 if (r) 177 dev_err(adev->dev, "GPU Recovery Failed: %d\n", r); 178 } else { 179 drm_sched_suspend_timeout(&ring->sched); 180 if (amdgpu_sriov_vf(adev)) 181 adev->virt.tdr_debug = true; 182 } 183 184 exit: 185 adev->job_hang = false; 186 drm_dev_exit(idx); 187 return DRM_GPU_SCHED_STAT_NOMINAL; 188 } 189 190 int amdgpu_job_alloc(struct amdgpu_device *adev, struct amdgpu_vm *vm, 191 struct drm_sched_entity *entity, void *owner, 192 unsigned int num_ibs, struct amdgpu_job **job) 193 { 194 if (num_ibs == 0) 195 return -EINVAL; 196 197 *job = kzalloc(struct_size(*job, ibs, num_ibs), GFP_KERNEL); 198 if (!*job) 199 return -ENOMEM; 200 201 /* 202 * Initialize the scheduler to at least some ring so that we always 203 * have a pointer to adev. 204 */ 205 (*job)->base.sched = &adev->rings[0]->sched; 206 (*job)->vm = vm; 207 208 amdgpu_sync_create(&(*job)->explicit_sync); 209 (*job)->generation = amdgpu_vm_generation(adev, vm); 210 (*job)->vm_pd_addr = AMDGPU_BO_INVALID_OFFSET; 211 212 if (!entity) 213 return 0; 214 215 return drm_sched_job_init(&(*job)->base, entity, 1, owner); 216 } 217 218 int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, 219 struct drm_sched_entity *entity, void *owner, 220 size_t size, enum amdgpu_ib_pool_type pool_type, 221 struct amdgpu_job **job) 222 { 223 int r; 224 225 r = amdgpu_job_alloc(adev, NULL, entity, owner, 1, job); 226 if (r) 227 return r; 228 229 (*job)->num_ibs = 1; 230 r = amdgpu_ib_get(adev, NULL, size, pool_type, &(*job)->ibs[0]); 231 if (r) { 232 if (entity) 233 drm_sched_job_cleanup(&(*job)->base); 234 kfree(*job); 235 } 236 237 return r; 238 } 239 240 void amdgpu_job_set_resources(struct amdgpu_job *job, struct amdgpu_bo *gds, 241 struct amdgpu_bo *gws, struct amdgpu_bo *oa) 242 { 243 if (gds) { 244 job->gds_base = amdgpu_bo_gpu_offset(gds) >> PAGE_SHIFT; 245 job->gds_size = amdgpu_bo_size(gds) >> PAGE_SHIFT; 246 } 247 if (gws) { 248 job->gws_base = amdgpu_bo_gpu_offset(gws) >> PAGE_SHIFT; 249 job->gws_size = amdgpu_bo_size(gws) >> PAGE_SHIFT; 250 } 251 if (oa) { 252 job->oa_base = amdgpu_bo_gpu_offset(oa) >> PAGE_SHIFT; 253 job->oa_size = amdgpu_bo_size(oa) >> PAGE_SHIFT; 254 } 255 } 256 257 void amdgpu_job_free_resources(struct amdgpu_job *job) 258 { 259 struct amdgpu_ring *ring = to_amdgpu_ring(job->base.sched); 260 struct dma_fence *f; 261 unsigned i; 262 263 /* Check if any fences where initialized */ 264 if (job->base.s_fence && job->base.s_fence->finished.ops) 265 f = &job->base.s_fence->finished; 266 else if (job->hw_fence.ops) 267 f = &job->hw_fence; 268 else 269 f = NULL; 270 271 for (i = 0; i < job->num_ibs; ++i) 272 amdgpu_ib_free(ring->adev, &job->ibs[i], f); 273 } 274 275 static void amdgpu_job_free_cb(struct drm_sched_job *s_job) 276 { 277 struct amdgpu_job *job = to_amdgpu_job(s_job); 278 279 drm_sched_job_cleanup(s_job); 280 281 amdgpu_sync_free(&job->explicit_sync); 282 283 /* only put the hw fence if has embedded fence */ 284 if (!job->hw_fence.ops) 285 kfree(job); 286 else 287 dma_fence_put(&job->hw_fence); 288 } 289 290 void amdgpu_job_set_gang_leader(struct amdgpu_job *job, 291 struct amdgpu_job *leader) 292 { 293 struct dma_fence *fence = &leader->base.s_fence->scheduled; 294 295 WARN_ON(job->gang_submit); 296 297 /* 298 * Don't add a reference when we are the gang leader to avoid circle 299 * dependency. 300 */ 301 if (job != leader) 302 dma_fence_get(fence); 303 job->gang_submit = fence; 304 } 305 306 void amdgpu_job_free(struct amdgpu_job *job) 307 { 308 if (job->base.entity) 309 drm_sched_job_cleanup(&job->base); 310 311 amdgpu_job_free_resources(job); 312 amdgpu_sync_free(&job->explicit_sync); 313 if (job->gang_submit != &job->base.s_fence->scheduled) 314 dma_fence_put(job->gang_submit); 315 316 if (!job->hw_fence.ops) 317 kfree(job); 318 else 319 dma_fence_put(&job->hw_fence); 320 } 321 322 struct dma_fence *amdgpu_job_submit(struct amdgpu_job *job) 323 { 324 struct dma_fence *f; 325 326 drm_sched_job_arm(&job->base); 327 f = dma_fence_get(&job->base.s_fence->finished); 328 amdgpu_job_free_resources(job); 329 drm_sched_entity_push_job(&job->base); 330 331 return f; 332 } 333 334 int amdgpu_job_submit_direct(struct amdgpu_job *job, struct amdgpu_ring *ring, 335 struct dma_fence **fence) 336 { 337 int r; 338 339 job->base.sched = &ring->sched; 340 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, job, fence); 341 342 if (r) 343 return r; 344 345 amdgpu_job_free(job); 346 return 0; 347 } 348 349 static struct dma_fence * 350 amdgpu_job_prepare_job(struct drm_sched_job *sched_job, 351 struct drm_sched_entity *s_entity) 352 { 353 struct amdgpu_ring *ring = to_amdgpu_ring(s_entity->rq->sched); 354 struct amdgpu_job *job = to_amdgpu_job(sched_job); 355 struct dma_fence *fence = NULL; 356 int r; 357 358 r = drm_sched_entity_error(s_entity); 359 if (r) 360 goto error; 361 362 if (job->gang_submit) 363 fence = amdgpu_device_switch_gang(ring->adev, job->gang_submit); 364 365 if (!fence && job->vm && !job->vmid) { 366 r = amdgpu_vmid_grab(job->vm, ring, job, &fence); 367 if (r) { 368 dev_err(ring->adev->dev, "Error getting VM ID (%d)\n", r); 369 goto error; 370 } 371 } 372 373 return fence; 374 375 error: 376 dma_fence_set_error(&job->base.s_fence->finished, r); 377 return NULL; 378 } 379 380 static struct dma_fence *amdgpu_job_run(struct drm_sched_job *sched_job) 381 { 382 struct amdgpu_ring *ring = to_amdgpu_ring(sched_job->sched); 383 struct amdgpu_device *adev = ring->adev; 384 struct dma_fence *fence = NULL, *finished; 385 struct amdgpu_job *job; 386 int r = 0; 387 388 job = to_amdgpu_job(sched_job); 389 finished = &job->base.s_fence->finished; 390 391 trace_amdgpu_sched_run_job(job); 392 393 /* Skip job if VRAM is lost and never resubmit gangs */ 394 if (job->generation != amdgpu_vm_generation(adev, job->vm) || 395 (job->job_run_counter && job->gang_submit)) 396 dma_fence_set_error(finished, -ECANCELED); 397 398 if (finished->error < 0) { 399 dev_dbg(adev->dev, "Skip scheduling IBs in ring(%s)", 400 ring->name); 401 } else { 402 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, job, 403 &fence); 404 if (r) 405 dev_err(adev->dev, 406 "Error scheduling IBs (%d) in ring(%s)", r, 407 ring->name); 408 } 409 410 job->job_run_counter++; 411 amdgpu_job_free_resources(job); 412 413 fence = r ? ERR_PTR(r) : fence; 414 return fence; 415 } 416 417 #define to_drm_sched_job(sched_job) \ 418 container_of((sched_job), struct drm_sched_job, queue_node) 419 420 void amdgpu_job_stop_all_jobs_on_sched(struct drm_gpu_scheduler *sched) 421 { 422 struct drm_sched_job *s_job; 423 struct drm_sched_entity *s_entity = NULL; 424 int i; 425 426 /* Signal all jobs not yet scheduled */ 427 for (i = DRM_SCHED_PRIORITY_KERNEL; i < sched->num_rqs; i++) { 428 struct drm_sched_rq *rq = sched->sched_rq[i]; 429 spin_lock(&rq->lock); 430 list_for_each_entry(s_entity, &rq->entities, list) { 431 while ((s_job = to_drm_sched_job(spsc_queue_pop(&s_entity->job_queue)))) { 432 struct drm_sched_fence *s_fence = s_job->s_fence; 433 434 dma_fence_signal(&s_fence->scheduled); 435 dma_fence_set_error(&s_fence->finished, -EHWPOISON); 436 dma_fence_signal(&s_fence->finished); 437 } 438 } 439 spin_unlock(&rq->lock); 440 } 441 442 /* Signal all jobs already scheduled to HW */ 443 list_for_each_entry(s_job, &sched->pending_list, list) { 444 struct drm_sched_fence *s_fence = s_job->s_fence; 445 446 dma_fence_set_error(&s_fence->finished, -EHWPOISON); 447 dma_fence_signal(&s_fence->finished); 448 } 449 } 450 451 const struct drm_sched_backend_ops amdgpu_sched_ops = { 452 .prepare_job = amdgpu_job_prepare_job, 453 .run_job = amdgpu_job_run, 454 .timedout_job = amdgpu_job_timedout, 455 .free_job = amdgpu_job_free_cb 456 }; 457