1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * 23 */ 24 #include <linux/kthread.h> 25 #include <linux/wait.h> 26 #include <linux/sched.h> 27 28 #include <drm/drm_drv.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_trace.h" 32 #include "amdgpu_reset.h" 33 #include "amdgpu_dev_coredump.h" 34 #include "amdgpu_xgmi.h" 35 36 static void amdgpu_job_do_core_dump(struct amdgpu_device *adev, 37 struct amdgpu_job *job) 38 { 39 int i; 40 41 dev_info(adev->dev, "Dumping IP State\n"); 42 for (i = 0; i < adev->num_ip_blocks; i++) 43 if (adev->ip_blocks[i].version->funcs->dump_ip_state) 44 adev->ip_blocks[i].version->funcs 45 ->dump_ip_state((void *)&adev->ip_blocks[i]); 46 dev_info(adev->dev, "Dumping IP State Completed\n"); 47 48 amdgpu_coredump(adev, true, false, job); 49 } 50 51 static void amdgpu_job_core_dump(struct amdgpu_device *adev, 52 struct amdgpu_job *job) 53 { 54 struct list_head device_list, *device_list_handle = NULL; 55 struct amdgpu_device *tmp_adev = NULL; 56 struct amdgpu_hive_info *hive = NULL; 57 58 if (!amdgpu_sriov_vf(adev)) 59 hive = amdgpu_get_xgmi_hive(adev); 60 if (hive) 61 mutex_lock(&hive->hive_lock); 62 /* 63 * Reuse the logic in amdgpu_device_gpu_recover() to build list of 64 * devices for code dump 65 */ 66 INIT_LIST_HEAD(&device_list); 67 if (!amdgpu_sriov_vf(adev) && (adev->gmc.xgmi.num_physical_nodes > 1) && hive) { 68 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) 69 list_add_tail(&tmp_adev->reset_list, &device_list); 70 if (!list_is_first(&adev->reset_list, &device_list)) 71 list_rotate_to_front(&adev->reset_list, &device_list); 72 device_list_handle = &device_list; 73 } else { 74 list_add_tail(&adev->reset_list, &device_list); 75 device_list_handle = &device_list; 76 } 77 78 /* Do the coredump for each device */ 79 list_for_each_entry(tmp_adev, device_list_handle, reset_list) 80 amdgpu_job_do_core_dump(tmp_adev, job); 81 82 if (hive) { 83 mutex_unlock(&hive->hive_lock); 84 amdgpu_put_xgmi_hive(hive); 85 } 86 } 87 88 static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job) 89 { 90 struct amdgpu_ring *ring = to_amdgpu_ring(s_job->sched); 91 struct amdgpu_job *job = to_amdgpu_job(s_job); 92 struct drm_wedge_task_info *info = NULL; 93 struct amdgpu_task_info *ti = NULL; 94 struct amdgpu_device *adev = ring->adev; 95 int idx, r; 96 97 if (!drm_dev_enter(adev_to_drm(adev), &idx)) { 98 dev_info(adev->dev, "%s - device unplugged skipping recovery on scheduler:%s", 99 __func__, s_job->sched->name); 100 101 /* Effectively the job is aborted as the device is gone */ 102 return DRM_GPU_SCHED_STAT_ENODEV; 103 } 104 105 /* 106 * Do the coredump immediately after a job timeout to get a very 107 * close dump/snapshot/representation of GPU's current error status 108 * Skip it for SRIOV, since VF FLR will be triggered by host driver 109 * before job timeout 110 */ 111 if (!amdgpu_sriov_vf(adev)) 112 amdgpu_job_core_dump(adev, job); 113 114 if (amdgpu_gpu_recovery && 115 amdgpu_ring_soft_recovery(ring, job->vmid, s_job->s_fence->parent)) { 116 dev_err(adev->dev, "ring %s timeout, but soft recovered\n", 117 s_job->sched->name); 118 goto exit; 119 } 120 121 dev_err(adev->dev, "ring %s timeout, signaled seq=%u, emitted seq=%u\n", 122 job->base.sched->name, atomic_read(&ring->fence_drv.last_seq), 123 ring->fence_drv.sync_seq); 124 125 ti = amdgpu_vm_get_task_info_pasid(ring->adev, job->pasid); 126 if (ti) { 127 amdgpu_vm_print_task_info(adev, ti); 128 info = &ti->task; 129 } 130 131 /* attempt a per ring reset */ 132 if (unlikely(adev->debug_disable_gpu_ring_reset)) { 133 dev_err(adev->dev, "Ring reset disabled by debug mask\n"); 134 } else if (amdgpu_gpu_recovery && ring->funcs->reset) { 135 dev_err(adev->dev, "Starting %s ring reset\n", 136 s_job->sched->name); 137 r = amdgpu_ring_reset(ring, job->vmid, NULL); 138 if (!r) { 139 atomic_inc(&ring->adev->gpu_reset_counter); 140 dev_err(adev->dev, "Ring %s reset succeeded\n", 141 ring->sched.name); 142 drm_dev_wedged_event(adev_to_drm(adev), 143 DRM_WEDGE_RECOVERY_NONE, info); 144 goto exit; 145 } 146 dev_err(adev->dev, "Ring %s reset failed\n", ring->sched.name); 147 } 148 149 dma_fence_set_error(&s_job->s_fence->finished, -ETIME); 150 151 if (amdgpu_device_should_recover_gpu(ring->adev)) { 152 struct amdgpu_reset_context reset_context; 153 memset(&reset_context, 0, sizeof(reset_context)); 154 155 reset_context.method = AMD_RESET_METHOD_NONE; 156 reset_context.reset_req_dev = adev; 157 reset_context.src = AMDGPU_RESET_SRC_JOB; 158 clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 159 160 /* 161 * To avoid an unnecessary extra coredump, as we have already 162 * got the very close representation of GPU's error status 163 */ 164 set_bit(AMDGPU_SKIP_COREDUMP, &reset_context.flags); 165 166 r = amdgpu_device_gpu_recover(ring->adev, job, &reset_context); 167 if (r) 168 dev_err(adev->dev, "GPU Recovery Failed: %d\n", r); 169 } else { 170 drm_sched_suspend_timeout(&ring->sched); 171 if (amdgpu_sriov_vf(adev)) 172 adev->virt.tdr_debug = true; 173 } 174 175 exit: 176 amdgpu_vm_put_task_info(ti); 177 drm_dev_exit(idx); 178 return DRM_GPU_SCHED_STAT_NOMINAL; 179 } 180 181 int amdgpu_job_alloc(struct amdgpu_device *adev, struct amdgpu_vm *vm, 182 struct drm_sched_entity *entity, void *owner, 183 unsigned int num_ibs, struct amdgpu_job **job, 184 u64 drm_client_id) 185 { 186 if (num_ibs == 0) 187 return -EINVAL; 188 189 *job = kzalloc(struct_size(*job, ibs, num_ibs), GFP_KERNEL); 190 if (!*job) 191 return -ENOMEM; 192 193 (*job)->vm = vm; 194 195 amdgpu_sync_create(&(*job)->explicit_sync); 196 (*job)->generation = amdgpu_vm_generation(adev, vm); 197 (*job)->vm_pd_addr = AMDGPU_BO_INVALID_OFFSET; 198 199 if (!entity) 200 return 0; 201 202 return drm_sched_job_init(&(*job)->base, entity, 1, owner, 203 drm_client_id); 204 } 205 206 int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, 207 struct drm_sched_entity *entity, void *owner, 208 size_t size, enum amdgpu_ib_pool_type pool_type, 209 struct amdgpu_job **job) 210 { 211 int r; 212 213 r = amdgpu_job_alloc(adev, NULL, entity, owner, 1, job, 0); 214 if (r) 215 return r; 216 217 (*job)->num_ibs = 1; 218 r = amdgpu_ib_get(adev, NULL, size, pool_type, &(*job)->ibs[0]); 219 if (r) { 220 if (entity) 221 drm_sched_job_cleanup(&(*job)->base); 222 kfree(*job); 223 } 224 225 return r; 226 } 227 228 void amdgpu_job_set_resources(struct amdgpu_job *job, struct amdgpu_bo *gds, 229 struct amdgpu_bo *gws, struct amdgpu_bo *oa) 230 { 231 if (gds) { 232 job->gds_base = amdgpu_bo_gpu_offset(gds) >> PAGE_SHIFT; 233 job->gds_size = amdgpu_bo_size(gds) >> PAGE_SHIFT; 234 } 235 if (gws) { 236 job->gws_base = amdgpu_bo_gpu_offset(gws) >> PAGE_SHIFT; 237 job->gws_size = amdgpu_bo_size(gws) >> PAGE_SHIFT; 238 } 239 if (oa) { 240 job->oa_base = amdgpu_bo_gpu_offset(oa) >> PAGE_SHIFT; 241 job->oa_size = amdgpu_bo_size(oa) >> PAGE_SHIFT; 242 } 243 } 244 245 void amdgpu_job_free_resources(struct amdgpu_job *job) 246 { 247 struct dma_fence *f; 248 unsigned i; 249 250 /* Check if any fences where initialized */ 251 if (job->base.s_fence && job->base.s_fence->finished.ops) 252 f = &job->base.s_fence->finished; 253 else if (job->hw_fence.base.ops) 254 f = &job->hw_fence.base; 255 else 256 f = NULL; 257 258 for (i = 0; i < job->num_ibs; ++i) 259 amdgpu_ib_free(&job->ibs[i], f); 260 } 261 262 static void amdgpu_job_free_cb(struct drm_sched_job *s_job) 263 { 264 struct amdgpu_job *job = to_amdgpu_job(s_job); 265 266 drm_sched_job_cleanup(s_job); 267 268 amdgpu_sync_free(&job->explicit_sync); 269 270 /* only put the hw fence if has embedded fence */ 271 if (!job->hw_fence.base.ops) 272 kfree(job); 273 else 274 dma_fence_put(&job->hw_fence.base); 275 } 276 277 void amdgpu_job_set_gang_leader(struct amdgpu_job *job, 278 struct amdgpu_job *leader) 279 { 280 struct dma_fence *fence = &leader->base.s_fence->scheduled; 281 282 WARN_ON(job->gang_submit); 283 284 /* 285 * Don't add a reference when we are the gang leader to avoid circle 286 * dependency. 287 */ 288 if (job != leader) 289 dma_fence_get(fence); 290 job->gang_submit = fence; 291 } 292 293 void amdgpu_job_free(struct amdgpu_job *job) 294 { 295 if (job->base.entity) 296 drm_sched_job_cleanup(&job->base); 297 298 amdgpu_job_free_resources(job); 299 amdgpu_sync_free(&job->explicit_sync); 300 if (job->gang_submit != &job->base.s_fence->scheduled) 301 dma_fence_put(job->gang_submit); 302 303 if (!job->hw_fence.base.ops) 304 kfree(job); 305 else 306 dma_fence_put(&job->hw_fence.base); 307 } 308 309 struct dma_fence *amdgpu_job_submit(struct amdgpu_job *job) 310 { 311 struct dma_fence *f; 312 313 drm_sched_job_arm(&job->base); 314 f = dma_fence_get(&job->base.s_fence->finished); 315 amdgpu_job_free_resources(job); 316 drm_sched_entity_push_job(&job->base); 317 318 return f; 319 } 320 321 int amdgpu_job_submit_direct(struct amdgpu_job *job, struct amdgpu_ring *ring, 322 struct dma_fence **fence) 323 { 324 int r; 325 326 job->base.sched = &ring->sched; 327 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, job, fence); 328 329 if (r) 330 return r; 331 332 amdgpu_job_free(job); 333 return 0; 334 } 335 336 static struct dma_fence * 337 amdgpu_job_prepare_job(struct drm_sched_job *sched_job, 338 struct drm_sched_entity *s_entity) 339 { 340 struct amdgpu_ring *ring = to_amdgpu_ring(s_entity->rq->sched); 341 struct amdgpu_job *job = to_amdgpu_job(sched_job); 342 struct dma_fence *fence; 343 int r; 344 345 r = drm_sched_entity_error(s_entity); 346 if (r) 347 goto error; 348 349 if (job->gang_submit) { 350 fence = amdgpu_device_switch_gang(ring->adev, job->gang_submit); 351 if (fence) 352 return fence; 353 } 354 355 fence = amdgpu_device_enforce_isolation(ring->adev, ring, job); 356 if (fence) 357 return fence; 358 359 if (job->vm && !job->vmid) { 360 r = amdgpu_vmid_grab(job->vm, ring, job, &fence); 361 if (r) { 362 dev_err(ring->adev->dev, "Error getting VM ID (%d)\n", r); 363 goto error; 364 } 365 /* 366 * The VM structure might be released after the VMID is 367 * assigned, we had multiple problems with people trying to use 368 * the VM pointer so better set it to NULL. 369 */ 370 if (!fence) 371 job->vm = NULL; 372 return fence; 373 } 374 375 return NULL; 376 377 error: 378 dma_fence_set_error(&job->base.s_fence->finished, r); 379 return NULL; 380 } 381 382 static struct dma_fence *amdgpu_job_run(struct drm_sched_job *sched_job) 383 { 384 struct amdgpu_ring *ring = to_amdgpu_ring(sched_job->sched); 385 struct amdgpu_device *adev = ring->adev; 386 struct dma_fence *fence = NULL, *finished; 387 struct amdgpu_job *job; 388 int r = 0; 389 390 job = to_amdgpu_job(sched_job); 391 finished = &job->base.s_fence->finished; 392 393 trace_amdgpu_sched_run_job(job); 394 395 /* Skip job if VRAM is lost and never resubmit gangs */ 396 if (job->generation != amdgpu_vm_generation(adev, job->vm) || 397 (job->job_run_counter && job->gang_submit)) 398 dma_fence_set_error(finished, -ECANCELED); 399 400 if (finished->error < 0) { 401 dev_dbg(adev->dev, "Skip scheduling IBs in ring(%s)", 402 ring->name); 403 } else { 404 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, job, 405 &fence); 406 if (r) 407 dev_err(adev->dev, 408 "Error scheduling IBs (%d) in ring(%s)", r, 409 ring->name); 410 } 411 412 job->job_run_counter++; 413 amdgpu_job_free_resources(job); 414 415 fence = r ? ERR_PTR(r) : fence; 416 return fence; 417 } 418 419 /* 420 * This is a duplicate function from DRM scheduler sched_internal.h. 421 * Plan is to remove it when amdgpu_job_stop_all_jobs_on_sched is removed, due 422 * latter being incorrect and racy. 423 * 424 * See https://lore.kernel.org/amd-gfx/44edde63-7181-44fb-a4f7-94e50514f539@amd.com/ 425 */ 426 static struct drm_sched_job * 427 drm_sched_entity_queue_pop(struct drm_sched_entity *entity) 428 { 429 struct spsc_node *node; 430 431 node = spsc_queue_pop(&entity->job_queue); 432 if (!node) 433 return NULL; 434 435 return container_of(node, struct drm_sched_job, queue_node); 436 } 437 438 void amdgpu_job_stop_all_jobs_on_sched(struct drm_gpu_scheduler *sched) 439 { 440 struct drm_sched_job *s_job; 441 struct drm_sched_entity *s_entity = NULL; 442 int i; 443 444 /* Signal all jobs not yet scheduled */ 445 for (i = DRM_SCHED_PRIORITY_KERNEL; i < sched->num_rqs; i++) { 446 struct drm_sched_rq *rq = sched->sched_rq[i]; 447 spin_lock(&rq->lock); 448 list_for_each_entry(s_entity, &rq->entities, list) { 449 while ((s_job = drm_sched_entity_queue_pop(s_entity))) { 450 struct drm_sched_fence *s_fence = s_job->s_fence; 451 452 dma_fence_signal(&s_fence->scheduled); 453 dma_fence_set_error(&s_fence->finished, -EHWPOISON); 454 dma_fence_signal(&s_fence->finished); 455 } 456 } 457 spin_unlock(&rq->lock); 458 } 459 460 /* Signal all jobs already scheduled to HW */ 461 list_for_each_entry(s_job, &sched->pending_list, list) { 462 struct drm_sched_fence *s_fence = s_job->s_fence; 463 464 dma_fence_set_error(&s_fence->finished, -EHWPOISON); 465 dma_fence_signal(&s_fence->finished); 466 } 467 } 468 469 const struct drm_sched_backend_ops amdgpu_sched_ops = { 470 .prepare_job = amdgpu_job_prepare_job, 471 .run_job = amdgpu_job_run, 472 .timedout_job = amdgpu_job_timedout, 473 .free_job = amdgpu_job_free_cb 474 }; 475