1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * 23 */ 24 #include <linux/kthread.h> 25 #include <linux/wait.h> 26 #include <linux/sched.h> 27 28 #include <drm/drm_drv.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_trace.h" 32 #include "amdgpu_reset.h" 33 #include "amdgpu_dev_coredump.h" 34 #include "amdgpu_xgmi.h" 35 36 static void amdgpu_job_do_core_dump(struct amdgpu_device *adev, 37 struct amdgpu_job *job) 38 { 39 int i; 40 41 dev_info(adev->dev, "Dumping IP State\n"); 42 for (i = 0; i < adev->num_ip_blocks; i++) 43 if (adev->ip_blocks[i].version->funcs->dump_ip_state) 44 adev->ip_blocks[i].version->funcs 45 ->dump_ip_state((void *)&adev->ip_blocks[i]); 46 dev_info(adev->dev, "Dumping IP State Completed\n"); 47 48 amdgpu_coredump(adev, true, false, job); 49 } 50 51 static void amdgpu_job_core_dump(struct amdgpu_device *adev, 52 struct amdgpu_job *job) 53 { 54 struct list_head device_list, *device_list_handle = NULL; 55 struct amdgpu_device *tmp_adev = NULL; 56 struct amdgpu_hive_info *hive = NULL; 57 58 if (!amdgpu_sriov_vf(adev)) 59 hive = amdgpu_get_xgmi_hive(adev); 60 if (hive) 61 mutex_lock(&hive->hive_lock); 62 /* 63 * Reuse the logic in amdgpu_device_gpu_recover() to build list of 64 * devices for code dump 65 */ 66 INIT_LIST_HEAD(&device_list); 67 if (!amdgpu_sriov_vf(adev) && (adev->gmc.xgmi.num_physical_nodes > 1) && hive) { 68 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) 69 list_add_tail(&tmp_adev->reset_list, &device_list); 70 if (!list_is_first(&adev->reset_list, &device_list)) 71 list_rotate_to_front(&adev->reset_list, &device_list); 72 device_list_handle = &device_list; 73 } else { 74 list_add_tail(&adev->reset_list, &device_list); 75 device_list_handle = &device_list; 76 } 77 78 /* Do the coredump for each device */ 79 list_for_each_entry(tmp_adev, device_list_handle, reset_list) 80 amdgpu_job_do_core_dump(tmp_adev, job); 81 82 if (hive) { 83 mutex_unlock(&hive->hive_lock); 84 amdgpu_put_xgmi_hive(hive); 85 } 86 } 87 88 static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job) 89 { 90 struct amdgpu_ring *ring = to_amdgpu_ring(s_job->sched); 91 struct amdgpu_job *job = to_amdgpu_job(s_job); 92 struct amdgpu_task_info *ti; 93 struct amdgpu_device *adev = ring->adev; 94 int idx, r; 95 96 if (!drm_dev_enter(adev_to_drm(adev), &idx)) { 97 dev_info(adev->dev, "%s - device unplugged skipping recovery on scheduler:%s", 98 __func__, s_job->sched->name); 99 100 /* Effectively the job is aborted as the device is gone */ 101 return DRM_GPU_SCHED_STAT_ENODEV; 102 } 103 104 /* 105 * Do the coredump immediately after a job timeout to get a very 106 * close dump/snapshot/representation of GPU's current error status 107 * Skip it for SRIOV, since VF FLR will be triggered by host driver 108 * before job timeout 109 */ 110 if (!amdgpu_sriov_vf(adev)) 111 amdgpu_job_core_dump(adev, job); 112 113 if (amdgpu_gpu_recovery && 114 amdgpu_ring_soft_recovery(ring, job->vmid, s_job->s_fence->parent)) { 115 dev_err(adev->dev, "ring %s timeout, but soft recovered\n", 116 s_job->sched->name); 117 goto exit; 118 } 119 120 dev_err(adev->dev, "ring %s timeout, signaled seq=%u, emitted seq=%u\n", 121 job->base.sched->name, atomic_read(&ring->fence_drv.last_seq), 122 ring->fence_drv.sync_seq); 123 124 ti = amdgpu_vm_get_task_info_pasid(ring->adev, job->pasid); 125 if (ti) { 126 dev_err(adev->dev, 127 "Process information: process %s pid %d thread %s pid %d\n", 128 ti->process_name, ti->tgid, ti->task_name, ti->pid); 129 amdgpu_vm_put_task_info(ti); 130 } 131 132 /* attempt a per ring reset */ 133 if (unlikely(adev->debug_disable_gpu_ring_reset)) { 134 dev_err(adev->dev, "Ring reset disabled by debug mask\n"); 135 } else if (amdgpu_gpu_recovery && ring->funcs->reset) { 136 dev_err(adev->dev, "Starting %s ring reset\n", 137 s_job->sched->name); 138 r = amdgpu_ring_reset(ring, job->vmid, NULL); 139 if (!r) { 140 atomic_inc(&ring->adev->gpu_reset_counter); 141 dev_err(adev->dev, "Ring %s reset succeeded\n", 142 ring->sched.name); 143 drm_dev_wedged_event(adev_to_drm(adev), 144 DRM_WEDGE_RECOVERY_NONE); 145 goto exit; 146 } 147 dev_err(adev->dev, "Ring %s reset failed\n", ring->sched.name); 148 } 149 150 dma_fence_set_error(&s_job->s_fence->finished, -ETIME); 151 152 if (amdgpu_device_should_recover_gpu(ring->adev)) { 153 struct amdgpu_reset_context reset_context; 154 memset(&reset_context, 0, sizeof(reset_context)); 155 156 reset_context.method = AMD_RESET_METHOD_NONE; 157 reset_context.reset_req_dev = adev; 158 reset_context.src = AMDGPU_RESET_SRC_JOB; 159 clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 160 161 /* 162 * To avoid an unnecessary extra coredump, as we have already 163 * got the very close representation of GPU's error status 164 */ 165 set_bit(AMDGPU_SKIP_COREDUMP, &reset_context.flags); 166 167 r = amdgpu_device_gpu_recover(ring->adev, job, &reset_context); 168 if (r) 169 dev_err(adev->dev, "GPU Recovery Failed: %d\n", r); 170 } else { 171 drm_sched_suspend_timeout(&ring->sched); 172 if (amdgpu_sriov_vf(adev)) 173 adev->virt.tdr_debug = true; 174 } 175 176 exit: 177 drm_dev_exit(idx); 178 return DRM_GPU_SCHED_STAT_NOMINAL; 179 } 180 181 int amdgpu_job_alloc(struct amdgpu_device *adev, struct amdgpu_vm *vm, 182 struct drm_sched_entity *entity, void *owner, 183 unsigned int num_ibs, struct amdgpu_job **job) 184 { 185 if (num_ibs == 0) 186 return -EINVAL; 187 188 *job = kzalloc(struct_size(*job, ibs, num_ibs), GFP_KERNEL); 189 if (!*job) 190 return -ENOMEM; 191 192 (*job)->vm = vm; 193 194 amdgpu_sync_create(&(*job)->explicit_sync); 195 (*job)->generation = amdgpu_vm_generation(adev, vm); 196 (*job)->vm_pd_addr = AMDGPU_BO_INVALID_OFFSET; 197 198 if (!entity) 199 return 0; 200 201 return drm_sched_job_init(&(*job)->base, entity, 1, owner); 202 } 203 204 int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, 205 struct drm_sched_entity *entity, void *owner, 206 size_t size, enum amdgpu_ib_pool_type pool_type, 207 struct amdgpu_job **job) 208 { 209 int r; 210 211 r = amdgpu_job_alloc(adev, NULL, entity, owner, 1, job); 212 if (r) 213 return r; 214 215 (*job)->num_ibs = 1; 216 r = amdgpu_ib_get(adev, NULL, size, pool_type, &(*job)->ibs[0]); 217 if (r) { 218 if (entity) 219 drm_sched_job_cleanup(&(*job)->base); 220 kfree(*job); 221 } 222 223 return r; 224 } 225 226 void amdgpu_job_set_resources(struct amdgpu_job *job, struct amdgpu_bo *gds, 227 struct amdgpu_bo *gws, struct amdgpu_bo *oa) 228 { 229 if (gds) { 230 job->gds_base = amdgpu_bo_gpu_offset(gds) >> PAGE_SHIFT; 231 job->gds_size = amdgpu_bo_size(gds) >> PAGE_SHIFT; 232 } 233 if (gws) { 234 job->gws_base = amdgpu_bo_gpu_offset(gws) >> PAGE_SHIFT; 235 job->gws_size = amdgpu_bo_size(gws) >> PAGE_SHIFT; 236 } 237 if (oa) { 238 job->oa_base = amdgpu_bo_gpu_offset(oa) >> PAGE_SHIFT; 239 job->oa_size = amdgpu_bo_size(oa) >> PAGE_SHIFT; 240 } 241 } 242 243 void amdgpu_job_free_resources(struct amdgpu_job *job) 244 { 245 struct dma_fence *f; 246 unsigned i; 247 248 /* Check if any fences where initialized */ 249 if (job->base.s_fence && job->base.s_fence->finished.ops) 250 f = &job->base.s_fence->finished; 251 else if (job->hw_fence.base.ops) 252 f = &job->hw_fence.base; 253 else 254 f = NULL; 255 256 for (i = 0; i < job->num_ibs; ++i) 257 amdgpu_ib_free(&job->ibs[i], f); 258 } 259 260 static void amdgpu_job_free_cb(struct drm_sched_job *s_job) 261 { 262 struct amdgpu_job *job = to_amdgpu_job(s_job); 263 264 drm_sched_job_cleanup(s_job); 265 266 amdgpu_sync_free(&job->explicit_sync); 267 268 /* only put the hw fence if has embedded fence */ 269 if (!job->hw_fence.base.ops) 270 kfree(job); 271 else 272 dma_fence_put(&job->hw_fence.base); 273 } 274 275 void amdgpu_job_set_gang_leader(struct amdgpu_job *job, 276 struct amdgpu_job *leader) 277 { 278 struct dma_fence *fence = &leader->base.s_fence->scheduled; 279 280 WARN_ON(job->gang_submit); 281 282 /* 283 * Don't add a reference when we are the gang leader to avoid circle 284 * dependency. 285 */ 286 if (job != leader) 287 dma_fence_get(fence); 288 job->gang_submit = fence; 289 } 290 291 void amdgpu_job_free(struct amdgpu_job *job) 292 { 293 if (job->base.entity) 294 drm_sched_job_cleanup(&job->base); 295 296 amdgpu_job_free_resources(job); 297 amdgpu_sync_free(&job->explicit_sync); 298 if (job->gang_submit != &job->base.s_fence->scheduled) 299 dma_fence_put(job->gang_submit); 300 301 if (!job->hw_fence.base.ops) 302 kfree(job); 303 else 304 dma_fence_put(&job->hw_fence.base); 305 } 306 307 struct dma_fence *amdgpu_job_submit(struct amdgpu_job *job) 308 { 309 struct dma_fence *f; 310 311 drm_sched_job_arm(&job->base); 312 f = dma_fence_get(&job->base.s_fence->finished); 313 amdgpu_job_free_resources(job); 314 drm_sched_entity_push_job(&job->base); 315 316 return f; 317 } 318 319 int amdgpu_job_submit_direct(struct amdgpu_job *job, struct amdgpu_ring *ring, 320 struct dma_fence **fence) 321 { 322 int r; 323 324 job->base.sched = &ring->sched; 325 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, job, fence); 326 327 if (r) 328 return r; 329 330 amdgpu_job_free(job); 331 return 0; 332 } 333 334 static struct dma_fence * 335 amdgpu_job_prepare_job(struct drm_sched_job *sched_job, 336 struct drm_sched_entity *s_entity) 337 { 338 struct amdgpu_ring *ring = to_amdgpu_ring(s_entity->rq->sched); 339 struct amdgpu_job *job = to_amdgpu_job(sched_job); 340 struct dma_fence *fence; 341 int r; 342 343 r = drm_sched_entity_error(s_entity); 344 if (r) 345 goto error; 346 347 if (job->gang_submit) { 348 fence = amdgpu_device_switch_gang(ring->adev, job->gang_submit); 349 if (fence) 350 return fence; 351 } 352 353 fence = amdgpu_device_enforce_isolation(ring->adev, ring, job); 354 if (fence) 355 return fence; 356 357 if (job->vm && !job->vmid) { 358 r = amdgpu_vmid_grab(job->vm, ring, job, &fence); 359 if (r) { 360 dev_err(ring->adev->dev, "Error getting VM ID (%d)\n", r); 361 goto error; 362 } 363 /* 364 * The VM structure might be released after the VMID is 365 * assigned, we had multiple problems with people trying to use 366 * the VM pointer so better set it to NULL. 367 */ 368 if (!fence) 369 job->vm = NULL; 370 return fence; 371 } 372 373 return NULL; 374 375 error: 376 dma_fence_set_error(&job->base.s_fence->finished, r); 377 return NULL; 378 } 379 380 static struct dma_fence *amdgpu_job_run(struct drm_sched_job *sched_job) 381 { 382 struct amdgpu_ring *ring = to_amdgpu_ring(sched_job->sched); 383 struct amdgpu_device *adev = ring->adev; 384 struct dma_fence *fence = NULL, *finished; 385 struct amdgpu_job *job; 386 int r = 0; 387 388 job = to_amdgpu_job(sched_job); 389 finished = &job->base.s_fence->finished; 390 391 trace_amdgpu_sched_run_job(job); 392 393 /* Skip job if VRAM is lost and never resubmit gangs */ 394 if (job->generation != amdgpu_vm_generation(adev, job->vm) || 395 (job->job_run_counter && job->gang_submit)) 396 dma_fence_set_error(finished, -ECANCELED); 397 398 if (finished->error < 0) { 399 dev_dbg(adev->dev, "Skip scheduling IBs in ring(%s)", 400 ring->name); 401 } else { 402 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, job, 403 &fence); 404 if (r) 405 dev_err(adev->dev, 406 "Error scheduling IBs (%d) in ring(%s)", r, 407 ring->name); 408 } 409 410 job->job_run_counter++; 411 amdgpu_job_free_resources(job); 412 413 fence = r ? ERR_PTR(r) : fence; 414 return fence; 415 } 416 417 /* 418 * This is a duplicate function from DRM scheduler sched_internal.h. 419 * Plan is to remove it when amdgpu_job_stop_all_jobs_on_sched is removed, due 420 * latter being incorrect and racy. 421 * 422 * See https://lore.kernel.org/amd-gfx/44edde63-7181-44fb-a4f7-94e50514f539@amd.com/ 423 */ 424 static struct drm_sched_job * 425 drm_sched_entity_queue_pop(struct drm_sched_entity *entity) 426 { 427 struct spsc_node *node; 428 429 node = spsc_queue_pop(&entity->job_queue); 430 if (!node) 431 return NULL; 432 433 return container_of(node, struct drm_sched_job, queue_node); 434 } 435 436 void amdgpu_job_stop_all_jobs_on_sched(struct drm_gpu_scheduler *sched) 437 { 438 struct drm_sched_job *s_job; 439 struct drm_sched_entity *s_entity = NULL; 440 int i; 441 442 /* Signal all jobs not yet scheduled */ 443 for (i = DRM_SCHED_PRIORITY_KERNEL; i < sched->num_rqs; i++) { 444 struct drm_sched_rq *rq = sched->sched_rq[i]; 445 spin_lock(&rq->lock); 446 list_for_each_entry(s_entity, &rq->entities, list) { 447 while ((s_job = drm_sched_entity_queue_pop(s_entity))) { 448 struct drm_sched_fence *s_fence = s_job->s_fence; 449 450 dma_fence_signal(&s_fence->scheduled); 451 dma_fence_set_error(&s_fence->finished, -EHWPOISON); 452 dma_fence_signal(&s_fence->finished); 453 } 454 } 455 spin_unlock(&rq->lock); 456 } 457 458 /* Signal all jobs already scheduled to HW */ 459 list_for_each_entry(s_job, &sched->pending_list, list) { 460 struct drm_sched_fence *s_fence = s_job->s_fence; 461 462 dma_fence_set_error(&s_fence->finished, -EHWPOISON); 463 dma_fence_signal(&s_fence->finished); 464 } 465 } 466 467 const struct drm_sched_backend_ops amdgpu_sched_ops = { 468 .prepare_job = amdgpu_job_prepare_job, 469 .run_job = amdgpu_job_run, 470 .timedout_job = amdgpu_job_timedout, 471 .free_job = amdgpu_job_free_cb 472 }; 473