1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * 23 */ 24 #include <linux/kthread.h> 25 #include <linux/wait.h> 26 #include <linux/sched.h> 27 28 #include <drm/drm_drv.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_trace.h" 32 #include "amdgpu_reset.h" 33 #include "amdgpu_dev_coredump.h" 34 #include "amdgpu_xgmi.h" 35 36 static void amdgpu_job_do_core_dump(struct amdgpu_device *adev, 37 struct amdgpu_job *job) 38 { 39 int i; 40 41 dev_info(adev->dev, "Dumping IP State\n"); 42 for (i = 0; i < adev->num_ip_blocks; i++) 43 if (adev->ip_blocks[i].version->funcs->dump_ip_state) 44 adev->ip_blocks[i].version->funcs 45 ->dump_ip_state((void *)&adev->ip_blocks[i]); 46 dev_info(adev->dev, "Dumping IP State Completed\n"); 47 48 amdgpu_coredump(adev, true, false, job); 49 } 50 51 static void amdgpu_job_core_dump(struct amdgpu_device *adev, 52 struct amdgpu_job *job) 53 { 54 struct list_head device_list, *device_list_handle = NULL; 55 struct amdgpu_device *tmp_adev = NULL; 56 struct amdgpu_hive_info *hive = NULL; 57 58 if (!amdgpu_sriov_vf(adev)) 59 hive = amdgpu_get_xgmi_hive(adev); 60 if (hive) 61 mutex_lock(&hive->hive_lock); 62 /* 63 * Reuse the logic in amdgpu_device_gpu_recover() to build list of 64 * devices for code dump 65 */ 66 INIT_LIST_HEAD(&device_list); 67 if (!amdgpu_sriov_vf(adev) && (adev->gmc.xgmi.num_physical_nodes > 1) && hive) { 68 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) 69 list_add_tail(&tmp_adev->reset_list, &device_list); 70 if (!list_is_first(&adev->reset_list, &device_list)) 71 list_rotate_to_front(&adev->reset_list, &device_list); 72 device_list_handle = &device_list; 73 } else { 74 list_add_tail(&adev->reset_list, &device_list); 75 device_list_handle = &device_list; 76 } 77 78 /* Do the coredump for each device */ 79 list_for_each_entry(tmp_adev, device_list_handle, reset_list) 80 amdgpu_job_do_core_dump(tmp_adev, job); 81 82 if (hive) { 83 mutex_unlock(&hive->hive_lock); 84 amdgpu_put_xgmi_hive(hive); 85 } 86 } 87 88 static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job) 89 { 90 struct amdgpu_ring *ring = to_amdgpu_ring(s_job->sched); 91 struct amdgpu_job *job = to_amdgpu_job(s_job); 92 struct drm_wedge_task_info *info = NULL; 93 struct amdgpu_task_info *ti = NULL; 94 struct amdgpu_device *adev = ring->adev; 95 int idx, r; 96 97 if (!drm_dev_enter(adev_to_drm(adev), &idx)) { 98 dev_info(adev->dev, "%s - device unplugged skipping recovery on scheduler:%s", 99 __func__, s_job->sched->name); 100 101 /* Effectively the job is aborted as the device is gone */ 102 return DRM_GPU_SCHED_STAT_ENODEV; 103 } 104 105 /* 106 * Do the coredump immediately after a job timeout to get a very 107 * close dump/snapshot/representation of GPU's current error status 108 * Skip it for SRIOV, since VF FLR will be triggered by host driver 109 * before job timeout 110 */ 111 if (!amdgpu_sriov_vf(adev)) 112 amdgpu_job_core_dump(adev, job); 113 114 if (amdgpu_gpu_recovery && 115 amdgpu_ring_is_reset_type_supported(ring, AMDGPU_RESET_TYPE_SOFT_RESET) && 116 amdgpu_ring_soft_recovery(ring, job->vmid, s_job->s_fence->parent)) { 117 dev_err(adev->dev, "ring %s timeout, but soft recovered\n", 118 s_job->sched->name); 119 goto exit; 120 } 121 122 dev_err(adev->dev, "ring %s timeout, signaled seq=%u, emitted seq=%u\n", 123 job->base.sched->name, atomic_read(&ring->fence_drv.last_seq), 124 ring->fence_drv.sync_seq); 125 126 ti = amdgpu_vm_get_task_info_pasid(ring->adev, job->pasid); 127 if (ti) { 128 amdgpu_vm_print_task_info(adev, ti); 129 info = &ti->task; 130 } 131 132 /* attempt a per ring reset */ 133 if (amdgpu_gpu_recovery && 134 amdgpu_ring_is_reset_type_supported(ring, AMDGPU_RESET_TYPE_PER_QUEUE) && 135 ring->funcs->reset) { 136 dev_err(adev->dev, "Starting %s ring reset\n", 137 s_job->sched->name); 138 r = amdgpu_ring_reset(ring, job->vmid, job->hw_fence); 139 if (!r) { 140 atomic_inc(&ring->adev->gpu_reset_counter); 141 dev_err(adev->dev, "Ring %s reset succeeded\n", 142 ring->sched.name); 143 drm_dev_wedged_event(adev_to_drm(adev), 144 DRM_WEDGE_RECOVERY_NONE, info); 145 goto exit; 146 } 147 dev_err(adev->dev, "Ring %s reset failed\n", ring->sched.name); 148 } 149 150 if (dma_fence_get_status(&s_job->s_fence->finished) == 0) 151 dma_fence_set_error(&s_job->s_fence->finished, -ETIME); 152 153 if (amdgpu_device_should_recover_gpu(ring->adev)) { 154 struct amdgpu_reset_context reset_context; 155 memset(&reset_context, 0, sizeof(reset_context)); 156 157 reset_context.method = AMD_RESET_METHOD_NONE; 158 reset_context.reset_req_dev = adev; 159 reset_context.src = AMDGPU_RESET_SRC_JOB; 160 clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 161 162 /* 163 * To avoid an unnecessary extra coredump, as we have already 164 * got the very close representation of GPU's error status 165 */ 166 set_bit(AMDGPU_SKIP_COREDUMP, &reset_context.flags); 167 168 r = amdgpu_device_gpu_recover(ring->adev, job, &reset_context); 169 if (r) 170 dev_err(adev->dev, "GPU Recovery Failed: %d\n", r); 171 } else { 172 drm_sched_suspend_timeout(&ring->sched); 173 if (amdgpu_sriov_vf(adev)) 174 adev->virt.tdr_debug = true; 175 } 176 177 exit: 178 amdgpu_vm_put_task_info(ti); 179 drm_dev_exit(idx); 180 return DRM_GPU_SCHED_STAT_RESET; 181 } 182 183 int amdgpu_job_alloc(struct amdgpu_device *adev, struct amdgpu_vm *vm, 184 struct drm_sched_entity *entity, void *owner, 185 unsigned int num_ibs, struct amdgpu_job **job, 186 u64 drm_client_id) 187 { 188 struct amdgpu_fence *af; 189 int r; 190 191 if (num_ibs == 0) 192 return -EINVAL; 193 194 *job = kzalloc(struct_size(*job, ibs, num_ibs), GFP_KERNEL); 195 if (!*job) 196 return -ENOMEM; 197 198 af = kzalloc(sizeof(struct amdgpu_fence), GFP_KERNEL); 199 if (!af) { 200 r = -ENOMEM; 201 goto err_job; 202 } 203 (*job)->hw_fence = af; 204 205 af = kzalloc(sizeof(struct amdgpu_fence), GFP_KERNEL); 206 if (!af) { 207 r = -ENOMEM; 208 goto err_fence; 209 } 210 (*job)->hw_vm_fence = af; 211 212 (*job)->vm = vm; 213 214 amdgpu_sync_create(&(*job)->explicit_sync); 215 (*job)->generation = amdgpu_vm_generation(adev, vm); 216 (*job)->vm_pd_addr = AMDGPU_BO_INVALID_OFFSET; 217 218 if (!entity) 219 return 0; 220 221 return drm_sched_job_init(&(*job)->base, entity, 1, owner, 222 drm_client_id); 223 224 err_fence: 225 kfree((*job)->hw_fence); 226 err_job: 227 kfree(*job); 228 *job = NULL; 229 230 return r; 231 } 232 233 int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, 234 struct drm_sched_entity *entity, void *owner, 235 size_t size, enum amdgpu_ib_pool_type pool_type, 236 struct amdgpu_job **job, u64 k_job_id) 237 { 238 int r; 239 240 r = amdgpu_job_alloc(adev, NULL, entity, owner, 1, job, 241 k_job_id); 242 if (r) 243 return r; 244 245 (*job)->num_ibs = 1; 246 r = amdgpu_ib_get(adev, NULL, size, pool_type, &(*job)->ibs[0]); 247 if (r) { 248 if (entity) 249 drm_sched_job_cleanup(&(*job)->base); 250 kfree((*job)->hw_vm_fence); 251 kfree((*job)->hw_fence); 252 kfree(*job); 253 *job = NULL; 254 } 255 256 return r; 257 } 258 259 void amdgpu_job_set_resources(struct amdgpu_job *job, struct amdgpu_bo *gds, 260 struct amdgpu_bo *gws, struct amdgpu_bo *oa) 261 { 262 if (gds) { 263 job->gds_base = amdgpu_bo_gpu_offset(gds) >> PAGE_SHIFT; 264 job->gds_size = amdgpu_bo_size(gds) >> PAGE_SHIFT; 265 } 266 if (gws) { 267 job->gws_base = amdgpu_bo_gpu_offset(gws) >> PAGE_SHIFT; 268 job->gws_size = amdgpu_bo_size(gws) >> PAGE_SHIFT; 269 } 270 if (oa) { 271 job->oa_base = amdgpu_bo_gpu_offset(oa) >> PAGE_SHIFT; 272 job->oa_size = amdgpu_bo_size(oa) >> PAGE_SHIFT; 273 } 274 } 275 276 void amdgpu_job_free_resources(struct amdgpu_job *job) 277 { 278 struct dma_fence *f; 279 unsigned i; 280 281 /* Check if any fences were initialized */ 282 if (job->base.s_fence && job->base.s_fence->finished.ops) 283 f = &job->base.s_fence->finished; 284 else if (job->hw_fence && job->hw_fence->base.ops) 285 f = &job->hw_fence->base; 286 else 287 f = NULL; 288 289 for (i = 0; i < job->num_ibs; ++i) 290 amdgpu_ib_free(&job->ibs[i], f); 291 } 292 293 static void amdgpu_job_free_cb(struct drm_sched_job *s_job) 294 { 295 struct amdgpu_job *job = to_amdgpu_job(s_job); 296 297 drm_sched_job_cleanup(s_job); 298 299 amdgpu_sync_free(&job->explicit_sync); 300 301 if (job->hw_fence->base.ops) 302 dma_fence_put(&job->hw_fence->base); 303 else 304 kfree(job->hw_fence); 305 if (job->hw_vm_fence->base.ops) 306 dma_fence_put(&job->hw_vm_fence->base); 307 else 308 kfree(job->hw_vm_fence); 309 310 kfree(job); 311 } 312 313 void amdgpu_job_set_gang_leader(struct amdgpu_job *job, 314 struct amdgpu_job *leader) 315 { 316 struct dma_fence *fence = &leader->base.s_fence->scheduled; 317 318 WARN_ON(job->gang_submit); 319 320 /* 321 * Don't add a reference when we are the gang leader to avoid circle 322 * dependency. 323 */ 324 if (job != leader) 325 dma_fence_get(fence); 326 job->gang_submit = fence; 327 } 328 329 void amdgpu_job_free(struct amdgpu_job *job) 330 { 331 if (job->base.entity) 332 drm_sched_job_cleanup(&job->base); 333 334 amdgpu_job_free_resources(job); 335 amdgpu_sync_free(&job->explicit_sync); 336 if (job->gang_submit != &job->base.s_fence->scheduled) 337 dma_fence_put(job->gang_submit); 338 339 if (job->hw_fence->base.ops) 340 dma_fence_put(&job->hw_fence->base); 341 else 342 kfree(job->hw_fence); 343 if (job->hw_vm_fence->base.ops) 344 dma_fence_put(&job->hw_vm_fence->base); 345 else 346 kfree(job->hw_vm_fence); 347 348 kfree(job); 349 } 350 351 struct dma_fence *amdgpu_job_submit(struct amdgpu_job *job) 352 { 353 struct dma_fence *f; 354 355 drm_sched_job_arm(&job->base); 356 f = dma_fence_get(&job->base.s_fence->finished); 357 amdgpu_job_free_resources(job); 358 drm_sched_entity_push_job(&job->base); 359 360 return f; 361 } 362 363 int amdgpu_job_submit_direct(struct amdgpu_job *job, struct amdgpu_ring *ring, 364 struct dma_fence **fence) 365 { 366 int r; 367 368 job->base.sched = &ring->sched; 369 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, job, fence); 370 371 if (r) 372 return r; 373 374 amdgpu_job_free(job); 375 return 0; 376 } 377 378 static struct dma_fence * 379 amdgpu_job_prepare_job(struct drm_sched_job *sched_job, 380 struct drm_sched_entity *s_entity) 381 { 382 struct amdgpu_ring *ring = to_amdgpu_ring(s_entity->rq->sched); 383 struct amdgpu_job *job = to_amdgpu_job(sched_job); 384 struct dma_fence *fence; 385 int r; 386 387 r = drm_sched_entity_error(s_entity); 388 if (r) 389 goto error; 390 391 if (job->gang_submit) { 392 fence = amdgpu_device_switch_gang(ring->adev, job->gang_submit); 393 if (fence) 394 return fence; 395 } 396 397 fence = amdgpu_device_enforce_isolation(ring->adev, ring, job); 398 if (fence) 399 return fence; 400 401 if (job->vm && !job->vmid) { 402 r = amdgpu_vmid_grab(job->vm, ring, job, &fence); 403 if (r) { 404 dev_err(ring->adev->dev, "Error getting VM ID (%d)\n", r); 405 goto error; 406 } 407 return fence; 408 } 409 410 return NULL; 411 412 error: 413 dma_fence_set_error(&job->base.s_fence->finished, r); 414 return NULL; 415 } 416 417 static struct dma_fence *amdgpu_job_run(struct drm_sched_job *sched_job) 418 { 419 struct amdgpu_ring *ring = to_amdgpu_ring(sched_job->sched); 420 struct amdgpu_device *adev = ring->adev; 421 struct dma_fence *fence = NULL, *finished; 422 struct amdgpu_job *job; 423 int r = 0; 424 425 job = to_amdgpu_job(sched_job); 426 finished = &job->base.s_fence->finished; 427 428 trace_amdgpu_sched_run_job(job); 429 430 /* Skip job if VRAM is lost and never resubmit gangs */ 431 if (job->generation != amdgpu_vm_generation(adev, job->vm) || 432 (job->job_run_counter && job->gang_submit)) 433 dma_fence_set_error(finished, -ECANCELED); 434 435 if (finished->error < 0) { 436 dev_dbg(adev->dev, "Skip scheduling IBs in ring(%s)", 437 ring->name); 438 } else { 439 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, job, 440 &fence); 441 if (r) 442 dev_err(adev->dev, 443 "Error scheduling IBs (%d) in ring(%s)", r, 444 ring->name); 445 } 446 447 job->job_run_counter++; 448 amdgpu_job_free_resources(job); 449 450 fence = r ? ERR_PTR(r) : fence; 451 return fence; 452 } 453 454 /* 455 * This is a duplicate function from DRM scheduler sched_internal.h. 456 * Plan is to remove it when amdgpu_job_stop_all_jobs_on_sched is removed, due 457 * latter being incorrect and racy. 458 * 459 * See https://lore.kernel.org/amd-gfx/44edde63-7181-44fb-a4f7-94e50514f539@amd.com/ 460 */ 461 static struct drm_sched_job * 462 drm_sched_entity_queue_pop(struct drm_sched_entity *entity) 463 { 464 struct spsc_node *node; 465 466 node = spsc_queue_pop(&entity->job_queue); 467 if (!node) 468 return NULL; 469 470 return container_of(node, struct drm_sched_job, queue_node); 471 } 472 473 void amdgpu_job_stop_all_jobs_on_sched(struct drm_gpu_scheduler *sched) 474 { 475 struct drm_sched_job *s_job; 476 struct drm_sched_entity *s_entity = NULL; 477 int i; 478 479 /* Signal all jobs not yet scheduled */ 480 for (i = DRM_SCHED_PRIORITY_KERNEL; i < sched->num_rqs; i++) { 481 struct drm_sched_rq *rq = sched->sched_rq[i]; 482 spin_lock(&rq->lock); 483 list_for_each_entry(s_entity, &rq->entities, list) { 484 while ((s_job = drm_sched_entity_queue_pop(s_entity))) { 485 struct drm_sched_fence *s_fence = s_job->s_fence; 486 487 dma_fence_signal(&s_fence->scheduled); 488 dma_fence_set_error(&s_fence->finished, -EHWPOISON); 489 dma_fence_signal(&s_fence->finished); 490 } 491 } 492 spin_unlock(&rq->lock); 493 } 494 495 /* Signal all jobs already scheduled to HW */ 496 list_for_each_entry(s_job, &sched->pending_list, list) { 497 struct drm_sched_fence *s_fence = s_job->s_fence; 498 499 dma_fence_set_error(&s_fence->finished, -EHWPOISON); 500 dma_fence_signal(&s_fence->finished); 501 } 502 } 503 504 const struct drm_sched_backend_ops amdgpu_sched_ops = { 505 .prepare_job = amdgpu_job_prepare_job, 506 .run_job = amdgpu_job_run, 507 .timedout_job = amdgpu_job_timedout, 508 .free_job = amdgpu_job_free_cb 509 }; 510