1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * 23 */ 24 #include <linux/kthread.h> 25 #include <linux/wait.h> 26 #include <linux/sched.h> 27 28 #include <drm/drm_drv.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_trace.h" 32 #include "amdgpu_reset.h" 33 #include "amdgpu_dev_coredump.h" 34 #include "amdgpu_xgmi.h" 35 36 static void amdgpu_job_do_core_dump(struct amdgpu_device *adev, 37 struct amdgpu_job *job) 38 { 39 int i; 40 41 dev_info(adev->dev, "Dumping IP State\n"); 42 for (i = 0; i < adev->num_ip_blocks; i++) 43 if (adev->ip_blocks[i].version->funcs->dump_ip_state) 44 adev->ip_blocks[i].version->funcs 45 ->dump_ip_state((void *)&adev->ip_blocks[i]); 46 dev_info(adev->dev, "Dumping IP State Completed\n"); 47 48 amdgpu_coredump(adev, true, false, job); 49 } 50 51 static void amdgpu_job_core_dump(struct amdgpu_device *adev, 52 struct amdgpu_job *job) 53 { 54 struct list_head device_list, *device_list_handle = NULL; 55 struct amdgpu_device *tmp_adev = NULL; 56 struct amdgpu_hive_info *hive = NULL; 57 58 if (!amdgpu_sriov_vf(adev)) 59 hive = amdgpu_get_xgmi_hive(adev); 60 if (hive) 61 mutex_lock(&hive->hive_lock); 62 /* 63 * Reuse the logic in amdgpu_device_gpu_recover() to build list of 64 * devices for code dump 65 */ 66 INIT_LIST_HEAD(&device_list); 67 if (!amdgpu_sriov_vf(adev) && (adev->gmc.xgmi.num_physical_nodes > 1) && hive) { 68 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) 69 list_add_tail(&tmp_adev->reset_list, &device_list); 70 if (!list_is_first(&adev->reset_list, &device_list)) 71 list_rotate_to_front(&adev->reset_list, &device_list); 72 device_list_handle = &device_list; 73 } else { 74 list_add_tail(&adev->reset_list, &device_list); 75 device_list_handle = &device_list; 76 } 77 78 /* Do the coredump for each device */ 79 list_for_each_entry(tmp_adev, device_list_handle, reset_list) 80 amdgpu_job_do_core_dump(tmp_adev, job); 81 82 if (hive) { 83 mutex_unlock(&hive->hive_lock); 84 amdgpu_put_xgmi_hive(hive); 85 } 86 } 87 88 static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job) 89 { 90 struct amdgpu_ring *ring = to_amdgpu_ring(s_job->sched); 91 struct amdgpu_job *job = to_amdgpu_job(s_job); 92 struct amdgpu_task_info *ti; 93 struct amdgpu_device *adev = ring->adev; 94 int idx; 95 int r; 96 97 if (!drm_dev_enter(adev_to_drm(adev), &idx)) { 98 dev_info(adev->dev, "%s - device unplugged skipping recovery on scheduler:%s", 99 __func__, s_job->sched->name); 100 101 /* Effectively the job is aborted as the device is gone */ 102 return DRM_GPU_SCHED_STAT_ENODEV; 103 } 104 105 adev->job_hang = true; 106 107 /* 108 * Do the coredump immediately after a job timeout to get a very 109 * close dump/snapshot/representation of GPU's current error status 110 * Skip it for SRIOV, since VF FLR will be triggered by host driver 111 * before job timeout 112 */ 113 if (!amdgpu_sriov_vf(adev)) 114 amdgpu_job_core_dump(adev, job); 115 116 if (amdgpu_gpu_recovery && 117 amdgpu_ring_soft_recovery(ring, job->vmid, s_job->s_fence->parent)) { 118 dev_err(adev->dev, "ring %s timeout, but soft recovered\n", 119 s_job->sched->name); 120 goto exit; 121 } 122 123 dev_err(adev->dev, "ring %s timeout, signaled seq=%u, emitted seq=%u\n", 124 job->base.sched->name, atomic_read(&ring->fence_drv.last_seq), 125 ring->fence_drv.sync_seq); 126 127 ti = amdgpu_vm_get_task_info_pasid(ring->adev, job->pasid); 128 if (ti) { 129 dev_err(adev->dev, 130 "Process information: process %s pid %d thread %s pid %d\n", 131 ti->process_name, ti->tgid, ti->task_name, ti->pid); 132 amdgpu_vm_put_task_info(ti); 133 } 134 135 dma_fence_set_error(&s_job->s_fence->finished, -ETIME); 136 137 /* attempt a per ring reset */ 138 if (amdgpu_gpu_recovery && 139 ring->funcs->reset) { 140 dev_err(adev->dev, "Starting %s ring reset\n", s_job->sched->name); 141 /* stop the scheduler, but don't mess with the 142 * bad job yet because if ring reset fails 143 * we'll fall back to full GPU reset. 144 */ 145 drm_sched_wqueue_stop(&ring->sched); 146 r = amdgpu_ring_reset(ring, job->vmid); 147 if (!r) { 148 if (amdgpu_ring_sched_ready(ring)) 149 drm_sched_stop(&ring->sched, s_job); 150 atomic_inc(&ring->adev->gpu_reset_counter); 151 amdgpu_fence_driver_force_completion(ring); 152 if (amdgpu_ring_sched_ready(ring)) 153 drm_sched_start(&ring->sched, 0); 154 goto exit; 155 } 156 dev_err(adev->dev, "Ring %s reset failure\n", ring->sched.name); 157 } 158 159 if (amdgpu_device_should_recover_gpu(ring->adev)) { 160 struct amdgpu_reset_context reset_context; 161 memset(&reset_context, 0, sizeof(reset_context)); 162 163 reset_context.method = AMD_RESET_METHOD_NONE; 164 reset_context.reset_req_dev = adev; 165 reset_context.src = AMDGPU_RESET_SRC_JOB; 166 clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 167 168 /* 169 * To avoid an unnecessary extra coredump, as we have already 170 * got the very close representation of GPU's error status 171 */ 172 set_bit(AMDGPU_SKIP_COREDUMP, &reset_context.flags); 173 174 r = amdgpu_device_gpu_recover(ring->adev, job, &reset_context); 175 if (r) 176 dev_err(adev->dev, "GPU Recovery Failed: %d\n", r); 177 } else { 178 drm_sched_suspend_timeout(&ring->sched); 179 if (amdgpu_sriov_vf(adev)) 180 adev->virt.tdr_debug = true; 181 } 182 183 exit: 184 adev->job_hang = false; 185 drm_dev_exit(idx); 186 return DRM_GPU_SCHED_STAT_NOMINAL; 187 } 188 189 int amdgpu_job_alloc(struct amdgpu_device *adev, struct amdgpu_vm *vm, 190 struct drm_sched_entity *entity, void *owner, 191 unsigned int num_ibs, struct amdgpu_job **job) 192 { 193 if (num_ibs == 0) 194 return -EINVAL; 195 196 *job = kzalloc(struct_size(*job, ibs, num_ibs), GFP_KERNEL); 197 if (!*job) 198 return -ENOMEM; 199 200 /* 201 * Initialize the scheduler to at least some ring so that we always 202 * have a pointer to adev. 203 */ 204 (*job)->base.sched = &adev->rings[0]->sched; 205 (*job)->vm = vm; 206 207 amdgpu_sync_create(&(*job)->explicit_sync); 208 (*job)->generation = amdgpu_vm_generation(adev, vm); 209 (*job)->vm_pd_addr = AMDGPU_BO_INVALID_OFFSET; 210 211 if (!entity) 212 return 0; 213 214 return drm_sched_job_init(&(*job)->base, entity, 1, owner); 215 } 216 217 int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, 218 struct drm_sched_entity *entity, void *owner, 219 size_t size, enum amdgpu_ib_pool_type pool_type, 220 struct amdgpu_job **job) 221 { 222 int r; 223 224 r = amdgpu_job_alloc(adev, NULL, entity, owner, 1, job); 225 if (r) 226 return r; 227 228 (*job)->num_ibs = 1; 229 r = amdgpu_ib_get(adev, NULL, size, pool_type, &(*job)->ibs[0]); 230 if (r) { 231 if (entity) 232 drm_sched_job_cleanup(&(*job)->base); 233 kfree(*job); 234 } 235 236 return r; 237 } 238 239 void amdgpu_job_set_resources(struct amdgpu_job *job, struct amdgpu_bo *gds, 240 struct amdgpu_bo *gws, struct amdgpu_bo *oa) 241 { 242 if (gds) { 243 job->gds_base = amdgpu_bo_gpu_offset(gds) >> PAGE_SHIFT; 244 job->gds_size = amdgpu_bo_size(gds) >> PAGE_SHIFT; 245 } 246 if (gws) { 247 job->gws_base = amdgpu_bo_gpu_offset(gws) >> PAGE_SHIFT; 248 job->gws_size = amdgpu_bo_size(gws) >> PAGE_SHIFT; 249 } 250 if (oa) { 251 job->oa_base = amdgpu_bo_gpu_offset(oa) >> PAGE_SHIFT; 252 job->oa_size = amdgpu_bo_size(oa) >> PAGE_SHIFT; 253 } 254 } 255 256 void amdgpu_job_free_resources(struct amdgpu_job *job) 257 { 258 struct dma_fence *f; 259 unsigned i; 260 261 /* Check if any fences where initialized */ 262 if (job->base.s_fence && job->base.s_fence->finished.ops) 263 f = &job->base.s_fence->finished; 264 else if (job->hw_fence.ops) 265 f = &job->hw_fence; 266 else 267 f = NULL; 268 269 for (i = 0; i < job->num_ibs; ++i) 270 amdgpu_ib_free(NULL, &job->ibs[i], f); 271 } 272 273 static void amdgpu_job_free_cb(struct drm_sched_job *s_job) 274 { 275 struct amdgpu_job *job = to_amdgpu_job(s_job); 276 277 drm_sched_job_cleanup(s_job); 278 279 amdgpu_sync_free(&job->explicit_sync); 280 281 /* only put the hw fence if has embedded fence */ 282 if (!job->hw_fence.ops) 283 kfree(job); 284 else 285 dma_fence_put(&job->hw_fence); 286 } 287 288 void amdgpu_job_set_gang_leader(struct amdgpu_job *job, 289 struct amdgpu_job *leader) 290 { 291 struct dma_fence *fence = &leader->base.s_fence->scheduled; 292 293 WARN_ON(job->gang_submit); 294 295 /* 296 * Don't add a reference when we are the gang leader to avoid circle 297 * dependency. 298 */ 299 if (job != leader) 300 dma_fence_get(fence); 301 job->gang_submit = fence; 302 } 303 304 void amdgpu_job_free(struct amdgpu_job *job) 305 { 306 if (job->base.entity) 307 drm_sched_job_cleanup(&job->base); 308 309 amdgpu_job_free_resources(job); 310 amdgpu_sync_free(&job->explicit_sync); 311 if (job->gang_submit != &job->base.s_fence->scheduled) 312 dma_fence_put(job->gang_submit); 313 314 if (!job->hw_fence.ops) 315 kfree(job); 316 else 317 dma_fence_put(&job->hw_fence); 318 } 319 320 struct dma_fence *amdgpu_job_submit(struct amdgpu_job *job) 321 { 322 struct dma_fence *f; 323 324 drm_sched_job_arm(&job->base); 325 f = dma_fence_get(&job->base.s_fence->finished); 326 amdgpu_job_free_resources(job); 327 drm_sched_entity_push_job(&job->base); 328 329 return f; 330 } 331 332 int amdgpu_job_submit_direct(struct amdgpu_job *job, struct amdgpu_ring *ring, 333 struct dma_fence **fence) 334 { 335 int r; 336 337 job->base.sched = &ring->sched; 338 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, job, fence); 339 340 if (r) 341 return r; 342 343 amdgpu_job_free(job); 344 return 0; 345 } 346 347 static struct dma_fence * 348 amdgpu_job_prepare_job(struct drm_sched_job *sched_job, 349 struct drm_sched_entity *s_entity) 350 { 351 struct amdgpu_ring *ring = to_amdgpu_ring(s_entity->rq->sched); 352 struct amdgpu_job *job = to_amdgpu_job(sched_job); 353 struct dma_fence *fence = NULL; 354 int r; 355 356 r = drm_sched_entity_error(s_entity); 357 if (r) 358 goto error; 359 360 if (job->gang_submit) 361 fence = amdgpu_device_switch_gang(ring->adev, job->gang_submit); 362 363 if (!fence && job->vm && !job->vmid) { 364 r = amdgpu_vmid_grab(job->vm, ring, job, &fence); 365 if (r) { 366 dev_err(ring->adev->dev, "Error getting VM ID (%d)\n", r); 367 goto error; 368 } 369 } 370 371 return fence; 372 373 error: 374 dma_fence_set_error(&job->base.s_fence->finished, r); 375 return NULL; 376 } 377 378 static struct dma_fence *amdgpu_job_run(struct drm_sched_job *sched_job) 379 { 380 struct amdgpu_ring *ring = to_amdgpu_ring(sched_job->sched); 381 struct amdgpu_device *adev = ring->adev; 382 struct dma_fence *fence = NULL, *finished; 383 struct amdgpu_job *job; 384 int r = 0; 385 386 job = to_amdgpu_job(sched_job); 387 finished = &job->base.s_fence->finished; 388 389 trace_amdgpu_sched_run_job(job); 390 391 /* Skip job if VRAM is lost and never resubmit gangs */ 392 if (job->generation != amdgpu_vm_generation(adev, job->vm) || 393 (job->job_run_counter && job->gang_submit)) 394 dma_fence_set_error(finished, -ECANCELED); 395 396 if (finished->error < 0) { 397 dev_dbg(adev->dev, "Skip scheduling IBs in ring(%s)", 398 ring->name); 399 } else { 400 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, job, 401 &fence); 402 if (r) 403 dev_err(adev->dev, 404 "Error scheduling IBs (%d) in ring(%s)", r, 405 ring->name); 406 } 407 408 job->job_run_counter++; 409 amdgpu_job_free_resources(job); 410 411 fence = r ? ERR_PTR(r) : fence; 412 return fence; 413 } 414 415 #define to_drm_sched_job(sched_job) \ 416 container_of((sched_job), struct drm_sched_job, queue_node) 417 418 void amdgpu_job_stop_all_jobs_on_sched(struct drm_gpu_scheduler *sched) 419 { 420 struct drm_sched_job *s_job; 421 struct drm_sched_entity *s_entity = NULL; 422 int i; 423 424 /* Signal all jobs not yet scheduled */ 425 for (i = DRM_SCHED_PRIORITY_KERNEL; i < sched->num_rqs; i++) { 426 struct drm_sched_rq *rq = sched->sched_rq[i]; 427 spin_lock(&rq->lock); 428 list_for_each_entry(s_entity, &rq->entities, list) { 429 while ((s_job = to_drm_sched_job(spsc_queue_pop(&s_entity->job_queue)))) { 430 struct drm_sched_fence *s_fence = s_job->s_fence; 431 432 dma_fence_signal(&s_fence->scheduled); 433 dma_fence_set_error(&s_fence->finished, -EHWPOISON); 434 dma_fence_signal(&s_fence->finished); 435 } 436 } 437 spin_unlock(&rq->lock); 438 } 439 440 /* Signal all jobs already scheduled to HW */ 441 list_for_each_entry(s_job, &sched->pending_list, list) { 442 struct drm_sched_fence *s_fence = s_job->s_fence; 443 444 dma_fence_set_error(&s_fence->finished, -EHWPOISON); 445 dma_fence_signal(&s_fence->finished); 446 } 447 } 448 449 const struct drm_sched_backend_ops amdgpu_sched_ops = { 450 .prepare_job = amdgpu_job_prepare_job, 451 .run_job = amdgpu_job_run, 452 .timedout_job = amdgpu_job_timedout, 453 .free_job = amdgpu_job_free_cb 454 }; 455