1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * 23 */ 24 #include <linux/kthread.h> 25 #include <linux/wait.h> 26 #include <linux/sched.h> 27 28 #include <drm/drm_drv.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_trace.h" 32 #include "amdgpu_reset.h" 33 #include "amdgpu_dev_coredump.h" 34 #include "amdgpu_xgmi.h" 35 36 static void amdgpu_job_do_core_dump(struct amdgpu_device *adev, 37 struct amdgpu_job *job) 38 { 39 int i; 40 41 dev_info(adev->dev, "Dumping IP State\n"); 42 for (i = 0; i < adev->num_ip_blocks; i++) 43 if (adev->ip_blocks[i].version->funcs->dump_ip_state) 44 adev->ip_blocks[i].version->funcs 45 ->dump_ip_state((void *)&adev->ip_blocks[i]); 46 dev_info(adev->dev, "Dumping IP State Completed\n"); 47 48 amdgpu_coredump(adev, true, false, job); 49 } 50 51 static void amdgpu_job_core_dump(struct amdgpu_device *adev, 52 struct amdgpu_job *job) 53 { 54 struct list_head device_list, *device_list_handle = NULL; 55 struct amdgpu_device *tmp_adev = NULL; 56 struct amdgpu_hive_info *hive = NULL; 57 58 if (!amdgpu_sriov_vf(adev)) 59 hive = amdgpu_get_xgmi_hive(adev); 60 if (hive) 61 mutex_lock(&hive->hive_lock); 62 /* 63 * Reuse the logic in amdgpu_device_gpu_recover() to build list of 64 * devices for code dump 65 */ 66 INIT_LIST_HEAD(&device_list); 67 if (!amdgpu_sriov_vf(adev) && (adev->gmc.xgmi.num_physical_nodes > 1) && hive) { 68 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) 69 list_add_tail(&tmp_adev->reset_list, &device_list); 70 if (!list_is_first(&adev->reset_list, &device_list)) 71 list_rotate_to_front(&adev->reset_list, &device_list); 72 device_list_handle = &device_list; 73 } else { 74 list_add_tail(&adev->reset_list, &device_list); 75 device_list_handle = &device_list; 76 } 77 78 /* Do the coredump for each device */ 79 list_for_each_entry(tmp_adev, device_list_handle, reset_list) 80 amdgpu_job_do_core_dump(tmp_adev, job); 81 82 if (hive) { 83 mutex_unlock(&hive->hive_lock); 84 amdgpu_put_xgmi_hive(hive); 85 } 86 } 87 88 static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job) 89 { 90 struct amdgpu_ring *ring = to_amdgpu_ring(s_job->sched); 91 struct amdgpu_job *job = to_amdgpu_job(s_job); 92 struct drm_wedge_task_info *info = NULL; 93 struct amdgpu_task_info *ti = NULL; 94 struct amdgpu_device *adev = ring->adev; 95 int idx, r; 96 97 if (!drm_dev_enter(adev_to_drm(adev), &idx)) { 98 dev_info(adev->dev, "%s - device unplugged skipping recovery on scheduler:%s", 99 __func__, s_job->sched->name); 100 101 /* Effectively the job is aborted as the device is gone */ 102 return DRM_GPU_SCHED_STAT_ENODEV; 103 } 104 105 /* 106 * Do the coredump immediately after a job timeout to get a very 107 * close dump/snapshot/representation of GPU's current error status 108 * Skip it for SRIOV, since VF FLR will be triggered by host driver 109 * before job timeout 110 */ 111 if (!amdgpu_sriov_vf(adev)) 112 amdgpu_job_core_dump(adev, job); 113 114 if (amdgpu_gpu_recovery && 115 amdgpu_ring_is_reset_type_supported(ring, AMDGPU_RESET_TYPE_SOFT_RESET) && 116 amdgpu_ring_soft_recovery(ring, job->vmid, s_job->s_fence->parent)) { 117 dev_err(adev->dev, "ring %s timeout, but soft recovered\n", 118 s_job->sched->name); 119 goto exit; 120 } 121 122 dev_err(adev->dev, "ring %s timeout, signaled seq=%u, emitted seq=%u\n", 123 job->base.sched->name, atomic_read(&ring->fence_drv.last_seq), 124 ring->fence_drv.sync_seq); 125 126 ti = amdgpu_vm_get_task_info_pasid(ring->adev, job->pasid); 127 if (ti) { 128 amdgpu_vm_print_task_info(adev, ti); 129 info = &ti->task; 130 } 131 132 /* attempt a per ring reset */ 133 if (unlikely(adev->debug_disable_gpu_ring_reset)) { 134 dev_err(adev->dev, "Ring reset disabled by debug mask\n"); 135 } else if (amdgpu_gpu_recovery && 136 amdgpu_ring_is_reset_type_supported(ring, AMDGPU_RESET_TYPE_PER_QUEUE) && 137 ring->funcs->reset) { 138 dev_err(adev->dev, "Starting %s ring reset\n", 139 s_job->sched->name); 140 r = amdgpu_ring_reset(ring, job->vmid, &job->hw_fence); 141 if (!r) { 142 atomic_inc(&ring->adev->gpu_reset_counter); 143 dev_err(adev->dev, "Ring %s reset succeeded\n", 144 ring->sched.name); 145 drm_dev_wedged_event(adev_to_drm(adev), 146 DRM_WEDGE_RECOVERY_NONE, info); 147 goto exit; 148 } 149 dev_err(adev->dev, "Ring %s reset failed\n", ring->sched.name); 150 } 151 152 dma_fence_set_error(&s_job->s_fence->finished, -ETIME); 153 154 if (amdgpu_device_should_recover_gpu(ring->adev)) { 155 struct amdgpu_reset_context reset_context; 156 memset(&reset_context, 0, sizeof(reset_context)); 157 158 reset_context.method = AMD_RESET_METHOD_NONE; 159 reset_context.reset_req_dev = adev; 160 reset_context.src = AMDGPU_RESET_SRC_JOB; 161 clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 162 163 /* 164 * To avoid an unnecessary extra coredump, as we have already 165 * got the very close representation of GPU's error status 166 */ 167 set_bit(AMDGPU_SKIP_COREDUMP, &reset_context.flags); 168 169 r = amdgpu_device_gpu_recover(ring->adev, job, &reset_context); 170 if (r) 171 dev_err(adev->dev, "GPU Recovery Failed: %d\n", r); 172 } else { 173 drm_sched_suspend_timeout(&ring->sched); 174 if (amdgpu_sriov_vf(adev)) 175 adev->virt.tdr_debug = true; 176 } 177 178 exit: 179 amdgpu_vm_put_task_info(ti); 180 drm_dev_exit(idx); 181 return DRM_GPU_SCHED_STAT_RESET; 182 } 183 184 int amdgpu_job_alloc(struct amdgpu_device *adev, struct amdgpu_vm *vm, 185 struct drm_sched_entity *entity, void *owner, 186 unsigned int num_ibs, struct amdgpu_job **job, 187 u64 drm_client_id) 188 { 189 if (num_ibs == 0) 190 return -EINVAL; 191 192 *job = kzalloc(struct_size(*job, ibs, num_ibs), GFP_KERNEL); 193 if (!*job) 194 return -ENOMEM; 195 196 (*job)->vm = vm; 197 198 amdgpu_sync_create(&(*job)->explicit_sync); 199 (*job)->generation = amdgpu_vm_generation(adev, vm); 200 (*job)->vm_pd_addr = AMDGPU_BO_INVALID_OFFSET; 201 202 if (!entity) 203 return 0; 204 205 return drm_sched_job_init(&(*job)->base, entity, 1, owner, 206 drm_client_id); 207 } 208 209 int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, 210 struct drm_sched_entity *entity, void *owner, 211 size_t size, enum amdgpu_ib_pool_type pool_type, 212 struct amdgpu_job **job, u64 k_job_id) 213 { 214 int r; 215 216 r = amdgpu_job_alloc(adev, NULL, entity, owner, 1, job, 217 k_job_id); 218 if (r) 219 return r; 220 221 (*job)->num_ibs = 1; 222 r = amdgpu_ib_get(adev, NULL, size, pool_type, &(*job)->ibs[0]); 223 if (r) { 224 if (entity) 225 drm_sched_job_cleanup(&(*job)->base); 226 kfree(*job); 227 } 228 229 return r; 230 } 231 232 void amdgpu_job_set_resources(struct amdgpu_job *job, struct amdgpu_bo *gds, 233 struct amdgpu_bo *gws, struct amdgpu_bo *oa) 234 { 235 if (gds) { 236 job->gds_base = amdgpu_bo_gpu_offset(gds) >> PAGE_SHIFT; 237 job->gds_size = amdgpu_bo_size(gds) >> PAGE_SHIFT; 238 } 239 if (gws) { 240 job->gws_base = amdgpu_bo_gpu_offset(gws) >> PAGE_SHIFT; 241 job->gws_size = amdgpu_bo_size(gws) >> PAGE_SHIFT; 242 } 243 if (oa) { 244 job->oa_base = amdgpu_bo_gpu_offset(oa) >> PAGE_SHIFT; 245 job->oa_size = amdgpu_bo_size(oa) >> PAGE_SHIFT; 246 } 247 } 248 249 void amdgpu_job_free_resources(struct amdgpu_job *job) 250 { 251 struct dma_fence *f; 252 unsigned i; 253 254 /* Check if any fences where initialized */ 255 if (job->base.s_fence && job->base.s_fence->finished.ops) 256 f = &job->base.s_fence->finished; 257 else if (job->hw_fence.base.ops) 258 f = &job->hw_fence.base; 259 else 260 f = NULL; 261 262 for (i = 0; i < job->num_ibs; ++i) 263 amdgpu_ib_free(&job->ibs[i], f); 264 } 265 266 static void amdgpu_job_free_cb(struct drm_sched_job *s_job) 267 { 268 struct amdgpu_job *job = to_amdgpu_job(s_job); 269 270 drm_sched_job_cleanup(s_job); 271 272 amdgpu_sync_free(&job->explicit_sync); 273 274 /* only put the hw fence if has embedded fence */ 275 if (!job->hw_fence.base.ops) 276 kfree(job); 277 else 278 dma_fence_put(&job->hw_fence.base); 279 } 280 281 void amdgpu_job_set_gang_leader(struct amdgpu_job *job, 282 struct amdgpu_job *leader) 283 { 284 struct dma_fence *fence = &leader->base.s_fence->scheduled; 285 286 WARN_ON(job->gang_submit); 287 288 /* 289 * Don't add a reference when we are the gang leader to avoid circle 290 * dependency. 291 */ 292 if (job != leader) 293 dma_fence_get(fence); 294 job->gang_submit = fence; 295 } 296 297 void amdgpu_job_free(struct amdgpu_job *job) 298 { 299 if (job->base.entity) 300 drm_sched_job_cleanup(&job->base); 301 302 amdgpu_job_free_resources(job); 303 amdgpu_sync_free(&job->explicit_sync); 304 if (job->gang_submit != &job->base.s_fence->scheduled) 305 dma_fence_put(job->gang_submit); 306 307 if (!job->hw_fence.base.ops) 308 kfree(job); 309 else 310 dma_fence_put(&job->hw_fence.base); 311 } 312 313 struct dma_fence *amdgpu_job_submit(struct amdgpu_job *job) 314 { 315 struct dma_fence *f; 316 317 drm_sched_job_arm(&job->base); 318 f = dma_fence_get(&job->base.s_fence->finished); 319 amdgpu_job_free_resources(job); 320 drm_sched_entity_push_job(&job->base); 321 322 return f; 323 } 324 325 int amdgpu_job_submit_direct(struct amdgpu_job *job, struct amdgpu_ring *ring, 326 struct dma_fence **fence) 327 { 328 int r; 329 330 job->base.sched = &ring->sched; 331 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, job, fence); 332 333 if (r) 334 return r; 335 336 amdgpu_job_free(job); 337 return 0; 338 } 339 340 static struct dma_fence * 341 amdgpu_job_prepare_job(struct drm_sched_job *sched_job, 342 struct drm_sched_entity *s_entity) 343 { 344 struct amdgpu_ring *ring = to_amdgpu_ring(s_entity->rq->sched); 345 struct amdgpu_job *job = to_amdgpu_job(sched_job); 346 struct dma_fence *fence; 347 int r; 348 349 r = drm_sched_entity_error(s_entity); 350 if (r) 351 goto error; 352 353 if (job->gang_submit) { 354 fence = amdgpu_device_switch_gang(ring->adev, job->gang_submit); 355 if (fence) 356 return fence; 357 } 358 359 fence = amdgpu_device_enforce_isolation(ring->adev, ring, job); 360 if (fence) 361 return fence; 362 363 if (job->vm && !job->vmid) { 364 r = amdgpu_vmid_grab(job->vm, ring, job, &fence); 365 if (r) { 366 dev_err(ring->adev->dev, "Error getting VM ID (%d)\n", r); 367 goto error; 368 } 369 return fence; 370 } 371 372 return NULL; 373 374 error: 375 dma_fence_set_error(&job->base.s_fence->finished, r); 376 return NULL; 377 } 378 379 static struct dma_fence *amdgpu_job_run(struct drm_sched_job *sched_job) 380 { 381 struct amdgpu_ring *ring = to_amdgpu_ring(sched_job->sched); 382 struct amdgpu_device *adev = ring->adev; 383 struct dma_fence *fence = NULL, *finished; 384 struct amdgpu_job *job; 385 int r = 0; 386 387 job = to_amdgpu_job(sched_job); 388 finished = &job->base.s_fence->finished; 389 390 trace_amdgpu_sched_run_job(job); 391 392 /* Skip job if VRAM is lost and never resubmit gangs */ 393 if (job->generation != amdgpu_vm_generation(adev, job->vm) || 394 (job->job_run_counter && job->gang_submit)) 395 dma_fence_set_error(finished, -ECANCELED); 396 397 if (finished->error < 0) { 398 dev_dbg(adev->dev, "Skip scheduling IBs in ring(%s)", 399 ring->name); 400 } else { 401 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, job, 402 &fence); 403 if (r) 404 dev_err(adev->dev, 405 "Error scheduling IBs (%d) in ring(%s)", r, 406 ring->name); 407 } 408 409 job->job_run_counter++; 410 amdgpu_job_free_resources(job); 411 412 fence = r ? ERR_PTR(r) : fence; 413 return fence; 414 } 415 416 /* 417 * This is a duplicate function from DRM scheduler sched_internal.h. 418 * Plan is to remove it when amdgpu_job_stop_all_jobs_on_sched is removed, due 419 * latter being incorrect and racy. 420 * 421 * See https://lore.kernel.org/amd-gfx/44edde63-7181-44fb-a4f7-94e50514f539@amd.com/ 422 */ 423 static struct drm_sched_job * 424 drm_sched_entity_queue_pop(struct drm_sched_entity *entity) 425 { 426 struct spsc_node *node; 427 428 node = spsc_queue_pop(&entity->job_queue); 429 if (!node) 430 return NULL; 431 432 return container_of(node, struct drm_sched_job, queue_node); 433 } 434 435 void amdgpu_job_stop_all_jobs_on_sched(struct drm_gpu_scheduler *sched) 436 { 437 struct drm_sched_job *s_job; 438 struct drm_sched_entity *s_entity = NULL; 439 int i; 440 441 /* Signal all jobs not yet scheduled */ 442 for (i = DRM_SCHED_PRIORITY_KERNEL; i < sched->num_rqs; i++) { 443 struct drm_sched_rq *rq = sched->sched_rq[i]; 444 spin_lock(&rq->lock); 445 list_for_each_entry(s_entity, &rq->entities, list) { 446 while ((s_job = drm_sched_entity_queue_pop(s_entity))) { 447 struct drm_sched_fence *s_fence = s_job->s_fence; 448 449 dma_fence_signal(&s_fence->scheduled); 450 dma_fence_set_error(&s_fence->finished, -EHWPOISON); 451 dma_fence_signal(&s_fence->finished); 452 } 453 } 454 spin_unlock(&rq->lock); 455 } 456 457 /* Signal all jobs already scheduled to HW */ 458 list_for_each_entry(s_job, &sched->pending_list, list) { 459 struct drm_sched_fence *s_fence = s_job->s_fence; 460 461 dma_fence_set_error(&s_fence->finished, -EHWPOISON); 462 dma_fence_signal(&s_fence->finished); 463 } 464 } 465 466 const struct drm_sched_backend_ops amdgpu_sched_ops = { 467 .prepare_job = amdgpu_job_prepare_job, 468 .run_job = amdgpu_job_run, 469 .timedout_job = amdgpu_job_timedout, 470 .free_job = amdgpu_job_free_cb 471 }; 472