1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 /** 30 * DOC: Interrupt Handling 31 * 32 * Interrupts generated within GPU hardware raise interrupt requests that are 33 * passed to amdgpu IRQ handler which is responsible for detecting source and 34 * type of the interrupt and dispatching matching handlers. If handling an 35 * interrupt requires calling kernel functions that may sleep processing is 36 * dispatched to work handlers. 37 * 38 * If MSI functionality is not disabled by module parameter then MSI 39 * support will be enabled. 40 * 41 * For GPU interrupt sources that may be driven by another driver, IRQ domain 42 * support is used (with mapping between virtual and hardware IRQs). 43 */ 44 45 #include <linux/irq.h> 46 #include <linux/pci.h> 47 48 #include <drm/drm_crtc_helper.h> 49 #include <drm/drm_vblank.h> 50 #include <drm/amdgpu_drm.h> 51 #include <drm/drm_drv.h> 52 #include "amdgpu.h" 53 #include "amdgpu_ih.h" 54 #include "atom.h" 55 #include "amdgpu_connectors.h" 56 #include "amdgpu_trace.h" 57 #include "amdgpu_amdkfd.h" 58 #include "amdgpu_ras.h" 59 60 #include <linux/pm_runtime.h> 61 62 #ifdef CONFIG_DRM_AMD_DC 63 #include "amdgpu_dm_irq.h" 64 #endif 65 66 #define AMDGPU_WAIT_IDLE_TIMEOUT 200 67 68 const char *soc15_ih_clientid_name[] = { 69 "IH", 70 "SDMA2 or ACP", 71 "ATHUB", 72 "BIF", 73 "SDMA3 or DCE", 74 "SDMA4 or ISP", 75 "VMC1 or PCIE0", 76 "RLC", 77 "SDMA0", 78 "SDMA1", 79 "SE0SH", 80 "SE1SH", 81 "SE2SH", 82 "SE3SH", 83 "VCN1 or UVD1", 84 "THM", 85 "VCN or UVD", 86 "SDMA5 or VCE0", 87 "VMC", 88 "SDMA6 or XDMA", 89 "GRBM_CP", 90 "ATS", 91 "ROM_SMUIO", 92 "DF", 93 "SDMA7 or VCE1", 94 "PWR", 95 "reserved", 96 "UTCL2", 97 "EA", 98 "UTCL2LOG", 99 "MP0", 100 "MP1" 101 }; 102 103 /** 104 * amdgpu_hotplug_work_func - work handler for display hotplug event 105 * 106 * @work: work struct pointer 107 * 108 * This is the hotplug event work handler (all ASICs). 109 * The work gets scheduled from the IRQ handler if there 110 * was a hotplug interrupt. It walks through the connector table 111 * and calls hotplug handler for each connector. After this, it sends 112 * a DRM hotplug event to alert userspace. 113 * 114 * This design approach is required in order to defer hotplug event handling 115 * from the IRQ handler to a work handler because hotplug handler has to use 116 * mutexes which cannot be locked in an IRQ handler (since &mutex_lock may 117 * sleep). 118 */ 119 static void amdgpu_hotplug_work_func(struct work_struct *work) 120 { 121 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, 122 hotplug_work); 123 struct drm_device *dev = adev_to_drm(adev); 124 struct drm_mode_config *mode_config = &dev->mode_config; 125 struct drm_connector *connector; 126 struct drm_connector_list_iter iter; 127 128 mutex_lock(&mode_config->mutex); 129 drm_connector_list_iter_begin(dev, &iter); 130 drm_for_each_connector_iter(connector, &iter) 131 amdgpu_connector_hotplug(connector); 132 drm_connector_list_iter_end(&iter); 133 mutex_unlock(&mode_config->mutex); 134 /* Just fire off a uevent and let userspace tell us what to do */ 135 drm_helper_hpd_irq_event(dev); 136 } 137 138 /** 139 * amdgpu_irq_disable_all - disable *all* interrupts 140 * 141 * @adev: amdgpu device pointer 142 * 143 * Disable all types of interrupts from all sources. 144 */ 145 void amdgpu_irq_disable_all(struct amdgpu_device *adev) 146 { 147 unsigned long irqflags; 148 unsigned i, j, k; 149 int r; 150 151 spin_lock_irqsave(&adev->irq.lock, irqflags); 152 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) { 153 if (!adev->irq.client[i].sources) 154 continue; 155 156 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) { 157 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j]; 158 159 if (!src || !src->funcs->set || !src->num_types) 160 continue; 161 162 for (k = 0; k < src->num_types; ++k) { 163 atomic_set(&src->enabled_types[k], 0); 164 r = src->funcs->set(adev, src, k, 165 AMDGPU_IRQ_STATE_DISABLE); 166 if (r) 167 DRM_ERROR("error disabling interrupt (%d)\n", 168 r); 169 } 170 } 171 } 172 spin_unlock_irqrestore(&adev->irq.lock, irqflags); 173 } 174 175 /** 176 * amdgpu_irq_handler - IRQ handler 177 * 178 * @irq: IRQ number (unused) 179 * @arg: pointer to DRM device 180 * 181 * IRQ handler for amdgpu driver (all ASICs). 182 * 183 * Returns: 184 * result of handling the IRQ, as defined by &irqreturn_t 185 */ 186 static irqreturn_t amdgpu_irq_handler(int irq, void *arg) 187 { 188 struct drm_device *dev = (struct drm_device *) arg; 189 struct amdgpu_device *adev = drm_to_adev(dev); 190 irqreturn_t ret; 191 192 ret = amdgpu_ih_process(adev, &adev->irq.ih); 193 if (ret == IRQ_HANDLED) 194 pm_runtime_mark_last_busy(dev->dev); 195 196 /* For the hardware that cannot enable bif ring for both ras_controller_irq 197 * and ras_err_evnet_athub_irq ih cookies, the driver has to poll status 198 * register to check whether the interrupt is triggered or not, and properly 199 * ack the interrupt if it is there 200 */ 201 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__PCIE_BIF)) { 202 if (adev->nbio.ras_funcs && 203 adev->nbio.ras_funcs->handle_ras_controller_intr_no_bifring) 204 adev->nbio.ras_funcs->handle_ras_controller_intr_no_bifring(adev); 205 206 if (adev->nbio.ras_funcs && 207 adev->nbio.ras_funcs->handle_ras_err_event_athub_intr_no_bifring) 208 adev->nbio.ras_funcs->handle_ras_err_event_athub_intr_no_bifring(adev); 209 } 210 211 return ret; 212 } 213 214 /** 215 * amdgpu_irq_handle_ih1 - kick of processing for IH1 216 * 217 * @work: work structure in struct amdgpu_irq 218 * 219 * Kick of processing IH ring 1. 220 */ 221 static void amdgpu_irq_handle_ih1(struct work_struct *work) 222 { 223 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, 224 irq.ih1_work); 225 226 amdgpu_ih_process(adev, &adev->irq.ih1); 227 } 228 229 /** 230 * amdgpu_irq_handle_ih2 - kick of processing for IH2 231 * 232 * @work: work structure in struct amdgpu_irq 233 * 234 * Kick of processing IH ring 2. 235 */ 236 static void amdgpu_irq_handle_ih2(struct work_struct *work) 237 { 238 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, 239 irq.ih2_work); 240 241 amdgpu_ih_process(adev, &adev->irq.ih2); 242 } 243 244 /** 245 * amdgpu_irq_handle_ih_soft - kick of processing for ih_soft 246 * 247 * @work: work structure in struct amdgpu_irq 248 * 249 * Kick of processing IH soft ring. 250 */ 251 static void amdgpu_irq_handle_ih_soft(struct work_struct *work) 252 { 253 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, 254 irq.ih_soft_work); 255 256 amdgpu_ih_process(adev, &adev->irq.ih_soft); 257 } 258 259 /** 260 * amdgpu_msi_ok - check whether MSI functionality is enabled 261 * 262 * @adev: amdgpu device pointer (unused) 263 * 264 * Checks whether MSI functionality has been disabled via module parameter 265 * (all ASICs). 266 * 267 * Returns: 268 * *true* if MSIs are allowed to be enabled or *false* otherwise 269 */ 270 static bool amdgpu_msi_ok(struct amdgpu_device *adev) 271 { 272 if (amdgpu_msi == 1) 273 return true; 274 else if (amdgpu_msi == 0) 275 return false; 276 277 return true; 278 } 279 280 static void amdgpu_restore_msix(struct amdgpu_device *adev) 281 { 282 u16 ctrl; 283 284 pci_read_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl); 285 if (!(ctrl & PCI_MSIX_FLAGS_ENABLE)) 286 return; 287 288 /* VF FLR */ 289 ctrl &= ~PCI_MSIX_FLAGS_ENABLE; 290 pci_write_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, ctrl); 291 ctrl |= PCI_MSIX_FLAGS_ENABLE; 292 pci_write_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, ctrl); 293 } 294 295 /** 296 * amdgpu_irq_init - initialize interrupt handling 297 * 298 * @adev: amdgpu device pointer 299 * 300 * Sets up work functions for hotplug and reset interrupts, enables MSI 301 * functionality, initializes vblank, hotplug and reset interrupt handling. 302 * 303 * Returns: 304 * 0 on success or error code on failure 305 */ 306 int amdgpu_irq_init(struct amdgpu_device *adev) 307 { 308 int r = 0; 309 unsigned int irq; 310 311 spin_lock_init(&adev->irq.lock); 312 313 /* Enable MSI if not disabled by module parameter */ 314 adev->irq.msi_enabled = false; 315 316 if (amdgpu_msi_ok(adev)) { 317 int nvec = pci_msix_vec_count(adev->pdev); 318 unsigned int flags; 319 320 if (nvec <= 0) { 321 flags = PCI_IRQ_MSI; 322 } else { 323 flags = PCI_IRQ_MSI | PCI_IRQ_MSIX; 324 } 325 /* we only need one vector */ 326 nvec = pci_alloc_irq_vectors(adev->pdev, 1, 1, flags); 327 if (nvec > 0) { 328 adev->irq.msi_enabled = true; 329 dev_dbg(adev->dev, "using MSI/MSI-X.\n"); 330 } 331 } 332 333 if (!amdgpu_device_has_dc_support(adev)) { 334 if (!adev->enable_virtual_display) 335 /* Disable vblank IRQs aggressively for power-saving */ 336 adev_to_drm(adev)->vblank_disable_immediate = true; 337 338 r = drm_vblank_init(adev_to_drm(adev), adev->mode_info.num_crtc); 339 if (r) 340 return r; 341 342 /* Pre-DCE11 */ 343 INIT_WORK(&adev->hotplug_work, 344 amdgpu_hotplug_work_func); 345 } 346 347 INIT_WORK(&adev->irq.ih1_work, amdgpu_irq_handle_ih1); 348 INIT_WORK(&adev->irq.ih2_work, amdgpu_irq_handle_ih2); 349 INIT_WORK(&adev->irq.ih_soft_work, amdgpu_irq_handle_ih_soft); 350 351 /* Use vector 0 for MSI-X. */ 352 r = pci_irq_vector(adev->pdev, 0); 353 if (r < 0) 354 return r; 355 irq = r; 356 357 /* PCI devices require shared interrupts. */ 358 r = request_irq(irq, amdgpu_irq_handler, IRQF_SHARED, adev_to_drm(adev)->driver->name, 359 adev_to_drm(adev)); 360 if (r) { 361 if (!amdgpu_device_has_dc_support(adev)) 362 flush_work(&adev->hotplug_work); 363 return r; 364 } 365 adev->irq.installed = true; 366 adev->irq.irq = irq; 367 adev_to_drm(adev)->max_vblank_count = 0x00ffffff; 368 369 DRM_DEBUG("amdgpu: irq initialized.\n"); 370 return 0; 371 } 372 373 374 void amdgpu_irq_fini_hw(struct amdgpu_device *adev) 375 { 376 if (adev->irq.installed) { 377 free_irq(adev->irq.irq, adev_to_drm(adev)); 378 adev->irq.installed = false; 379 if (adev->irq.msi_enabled) 380 pci_free_irq_vectors(adev->pdev); 381 382 if (!amdgpu_device_has_dc_support(adev)) 383 flush_work(&adev->hotplug_work); 384 } 385 386 amdgpu_ih_ring_fini(adev, &adev->irq.ih_soft); 387 amdgpu_ih_ring_fini(adev, &adev->irq.ih); 388 amdgpu_ih_ring_fini(adev, &adev->irq.ih1); 389 amdgpu_ih_ring_fini(adev, &adev->irq.ih2); 390 } 391 392 /** 393 * amdgpu_irq_fini - shut down interrupt handling 394 * 395 * @adev: amdgpu device pointer 396 * 397 * Tears down work functions for hotplug and reset interrupts, disables MSI 398 * functionality, shuts down vblank, hotplug and reset interrupt handling, 399 * turns off interrupts from all sources (all ASICs). 400 */ 401 void amdgpu_irq_fini_sw(struct amdgpu_device *adev) 402 { 403 unsigned i, j; 404 405 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) { 406 if (!adev->irq.client[i].sources) 407 continue; 408 409 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) { 410 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j]; 411 412 if (!src) 413 continue; 414 415 kfree(src->enabled_types); 416 src->enabled_types = NULL; 417 } 418 kfree(adev->irq.client[i].sources); 419 adev->irq.client[i].sources = NULL; 420 } 421 } 422 423 /** 424 * amdgpu_irq_add_id - register IRQ source 425 * 426 * @adev: amdgpu device pointer 427 * @client_id: client id 428 * @src_id: source id 429 * @source: IRQ source pointer 430 * 431 * Registers IRQ source on a client. 432 * 433 * Returns: 434 * 0 on success or error code otherwise 435 */ 436 int amdgpu_irq_add_id(struct amdgpu_device *adev, 437 unsigned client_id, unsigned src_id, 438 struct amdgpu_irq_src *source) 439 { 440 if (client_id >= AMDGPU_IRQ_CLIENTID_MAX) 441 return -EINVAL; 442 443 if (src_id >= AMDGPU_MAX_IRQ_SRC_ID) 444 return -EINVAL; 445 446 if (!source->funcs) 447 return -EINVAL; 448 449 if (!adev->irq.client[client_id].sources) { 450 adev->irq.client[client_id].sources = 451 kcalloc(AMDGPU_MAX_IRQ_SRC_ID, 452 sizeof(struct amdgpu_irq_src *), 453 GFP_KERNEL); 454 if (!adev->irq.client[client_id].sources) 455 return -ENOMEM; 456 } 457 458 if (adev->irq.client[client_id].sources[src_id] != NULL) 459 return -EINVAL; 460 461 if (source->num_types && !source->enabled_types) { 462 atomic_t *types; 463 464 types = kcalloc(source->num_types, sizeof(atomic_t), 465 GFP_KERNEL); 466 if (!types) 467 return -ENOMEM; 468 469 source->enabled_types = types; 470 } 471 472 adev->irq.client[client_id].sources[src_id] = source; 473 return 0; 474 } 475 476 /** 477 * amdgpu_irq_dispatch - dispatch IRQ to IP blocks 478 * 479 * @adev: amdgpu device pointer 480 * @ih: interrupt ring instance 481 * 482 * Dispatches IRQ to IP blocks. 483 */ 484 void amdgpu_irq_dispatch(struct amdgpu_device *adev, 485 struct amdgpu_ih_ring *ih) 486 { 487 u32 ring_index = ih->rptr >> 2; 488 struct amdgpu_iv_entry entry; 489 unsigned client_id, src_id; 490 struct amdgpu_irq_src *src; 491 bool handled = false; 492 int r; 493 494 entry.ih = ih; 495 entry.iv_entry = (const uint32_t *)&ih->ring[ring_index]; 496 amdgpu_ih_decode_iv(adev, &entry); 497 498 trace_amdgpu_iv(ih - &adev->irq.ih, &entry); 499 500 client_id = entry.client_id; 501 src_id = entry.src_id; 502 503 if (client_id >= AMDGPU_IRQ_CLIENTID_MAX) { 504 DRM_DEBUG("Invalid client_id in IV: %d\n", client_id); 505 506 } else if (src_id >= AMDGPU_MAX_IRQ_SRC_ID) { 507 DRM_DEBUG("Invalid src_id in IV: %d\n", src_id); 508 509 } else if ((client_id == AMDGPU_IRQ_CLIENTID_LEGACY) && 510 adev->irq.virq[src_id]) { 511 generic_handle_domain_irq(adev->irq.domain, src_id); 512 513 } else if (!adev->irq.client[client_id].sources) { 514 DRM_DEBUG("Unregistered interrupt client_id: %d src_id: %d\n", 515 client_id, src_id); 516 517 } else if ((src = adev->irq.client[client_id].sources[src_id])) { 518 r = src->funcs->process(adev, src, &entry); 519 if (r < 0) 520 DRM_ERROR("error processing interrupt (%d)\n", r); 521 else if (r) 522 handled = true; 523 524 } else { 525 DRM_DEBUG("Unhandled interrupt src_id: %d\n", src_id); 526 } 527 528 /* Send it to amdkfd as well if it isn't already handled */ 529 if (!handled) 530 amdgpu_amdkfd_interrupt(adev, entry.iv_entry); 531 } 532 533 /** 534 * amdgpu_irq_delegate - delegate IV to soft IH ring 535 * 536 * @adev: amdgpu device pointer 537 * @entry: IV entry 538 * @num_dw: size of IV 539 * 540 * Delegate the IV to the soft IH ring and schedule processing of it. Used 541 * if the hardware delegation to IH1 or IH2 doesn't work for some reason. 542 */ 543 void amdgpu_irq_delegate(struct amdgpu_device *adev, 544 struct amdgpu_iv_entry *entry, 545 unsigned int num_dw) 546 { 547 amdgpu_ih_ring_write(&adev->irq.ih_soft, entry->iv_entry, num_dw); 548 schedule_work(&adev->irq.ih_soft_work); 549 } 550 551 /** 552 * amdgpu_irq_update - update hardware interrupt state 553 * 554 * @adev: amdgpu device pointer 555 * @src: interrupt source pointer 556 * @type: type of interrupt 557 * 558 * Updates interrupt state for the specific source (all ASICs). 559 */ 560 int amdgpu_irq_update(struct amdgpu_device *adev, 561 struct amdgpu_irq_src *src, unsigned type) 562 { 563 unsigned long irqflags; 564 enum amdgpu_interrupt_state state; 565 int r; 566 567 spin_lock_irqsave(&adev->irq.lock, irqflags); 568 569 /* We need to determine after taking the lock, otherwise 570 we might disable just enabled interrupts again */ 571 if (amdgpu_irq_enabled(adev, src, type)) 572 state = AMDGPU_IRQ_STATE_ENABLE; 573 else 574 state = AMDGPU_IRQ_STATE_DISABLE; 575 576 r = src->funcs->set(adev, src, type, state); 577 spin_unlock_irqrestore(&adev->irq.lock, irqflags); 578 return r; 579 } 580 581 /** 582 * amdgpu_irq_gpu_reset_resume_helper - update interrupt states on all sources 583 * 584 * @adev: amdgpu device pointer 585 * 586 * Updates state of all types of interrupts on all sources on resume after 587 * reset. 588 */ 589 void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev) 590 { 591 int i, j, k; 592 593 if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev)) 594 amdgpu_restore_msix(adev); 595 596 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) { 597 if (!adev->irq.client[i].sources) 598 continue; 599 600 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) { 601 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j]; 602 603 if (!src || !src->funcs || !src->funcs->set) 604 continue; 605 for (k = 0; k < src->num_types; k++) 606 amdgpu_irq_update(adev, src, k); 607 } 608 } 609 } 610 611 /** 612 * amdgpu_irq_get - enable interrupt 613 * 614 * @adev: amdgpu device pointer 615 * @src: interrupt source pointer 616 * @type: type of interrupt 617 * 618 * Enables specified type of interrupt on the specified source (all ASICs). 619 * 620 * Returns: 621 * 0 on success or error code otherwise 622 */ 623 int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src, 624 unsigned type) 625 { 626 if (!adev->irq.installed) 627 return -ENOENT; 628 629 if (type >= src->num_types) 630 return -EINVAL; 631 632 if (!src->enabled_types || !src->funcs->set) 633 return -EINVAL; 634 635 if (atomic_inc_return(&src->enabled_types[type]) == 1) 636 return amdgpu_irq_update(adev, src, type); 637 638 return 0; 639 } 640 641 /** 642 * amdgpu_irq_put - disable interrupt 643 * 644 * @adev: amdgpu device pointer 645 * @src: interrupt source pointer 646 * @type: type of interrupt 647 * 648 * Enables specified type of interrupt on the specified source (all ASICs). 649 * 650 * Returns: 651 * 0 on success or error code otherwise 652 */ 653 int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src, 654 unsigned type) 655 { 656 if (!adev->irq.installed) 657 return -ENOENT; 658 659 if (type >= src->num_types) 660 return -EINVAL; 661 662 if (!src->enabled_types || !src->funcs->set) 663 return -EINVAL; 664 665 if (atomic_dec_and_test(&src->enabled_types[type])) 666 return amdgpu_irq_update(adev, src, type); 667 668 return 0; 669 } 670 671 /** 672 * amdgpu_irq_enabled - check whether interrupt is enabled or not 673 * 674 * @adev: amdgpu device pointer 675 * @src: interrupt source pointer 676 * @type: type of interrupt 677 * 678 * Checks whether the given type of interrupt is enabled on the given source. 679 * 680 * Returns: 681 * *true* if interrupt is enabled, *false* if interrupt is disabled or on 682 * invalid parameters 683 */ 684 bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src, 685 unsigned type) 686 { 687 if (!adev->irq.installed) 688 return false; 689 690 if (type >= src->num_types) 691 return false; 692 693 if (!src->enabled_types || !src->funcs->set) 694 return false; 695 696 return !!atomic_read(&src->enabled_types[type]); 697 } 698 699 /* XXX: Generic IRQ handling */ 700 static void amdgpu_irq_mask(struct irq_data *irqd) 701 { 702 /* XXX */ 703 } 704 705 static void amdgpu_irq_unmask(struct irq_data *irqd) 706 { 707 /* XXX */ 708 } 709 710 /* amdgpu hardware interrupt chip descriptor */ 711 static struct irq_chip amdgpu_irq_chip = { 712 .name = "amdgpu-ih", 713 .irq_mask = amdgpu_irq_mask, 714 .irq_unmask = amdgpu_irq_unmask, 715 }; 716 717 /** 718 * amdgpu_irqdomain_map - create mapping between virtual and hardware IRQ numbers 719 * 720 * @d: amdgpu IRQ domain pointer (unused) 721 * @irq: virtual IRQ number 722 * @hwirq: hardware irq number 723 * 724 * Current implementation assigns simple interrupt handler to the given virtual 725 * IRQ. 726 * 727 * Returns: 728 * 0 on success or error code otherwise 729 */ 730 static int amdgpu_irqdomain_map(struct irq_domain *d, 731 unsigned int irq, irq_hw_number_t hwirq) 732 { 733 if (hwirq >= AMDGPU_MAX_IRQ_SRC_ID) 734 return -EPERM; 735 736 irq_set_chip_and_handler(irq, 737 &amdgpu_irq_chip, handle_simple_irq); 738 return 0; 739 } 740 741 /* Implementation of methods for amdgpu IRQ domain */ 742 static const struct irq_domain_ops amdgpu_hw_irqdomain_ops = { 743 .map = amdgpu_irqdomain_map, 744 }; 745 746 /** 747 * amdgpu_irq_add_domain - create a linear IRQ domain 748 * 749 * @adev: amdgpu device pointer 750 * 751 * Creates an IRQ domain for GPU interrupt sources 752 * that may be driven by another driver (e.g., ACP). 753 * 754 * Returns: 755 * 0 on success or error code otherwise 756 */ 757 int amdgpu_irq_add_domain(struct amdgpu_device *adev) 758 { 759 adev->irq.domain = irq_domain_add_linear(NULL, AMDGPU_MAX_IRQ_SRC_ID, 760 &amdgpu_hw_irqdomain_ops, adev); 761 if (!adev->irq.domain) { 762 DRM_ERROR("GPU irq add domain failed\n"); 763 return -ENODEV; 764 } 765 766 return 0; 767 } 768 769 /** 770 * amdgpu_irq_remove_domain - remove the IRQ domain 771 * 772 * @adev: amdgpu device pointer 773 * 774 * Removes the IRQ domain for GPU interrupt sources 775 * that may be driven by another driver (e.g., ACP). 776 */ 777 void amdgpu_irq_remove_domain(struct amdgpu_device *adev) 778 { 779 if (adev->irq.domain) { 780 irq_domain_remove(adev->irq.domain); 781 adev->irq.domain = NULL; 782 } 783 } 784 785 /** 786 * amdgpu_irq_create_mapping - create mapping between domain Linux IRQs 787 * 788 * @adev: amdgpu device pointer 789 * @src_id: IH source id 790 * 791 * Creates mapping between a domain IRQ (GPU IH src id) and a Linux IRQ 792 * Use this for components that generate a GPU interrupt, but are driven 793 * by a different driver (e.g., ACP). 794 * 795 * Returns: 796 * Linux IRQ 797 */ 798 unsigned amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned src_id) 799 { 800 adev->irq.virq[src_id] = irq_create_mapping(adev->irq.domain, src_id); 801 802 return adev->irq.virq[src_id]; 803 } 804