1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 /** 30 * DOC: Interrupt Handling 31 * 32 * Interrupts generated within GPU hardware raise interrupt requests that are 33 * passed to amdgpu IRQ handler which is responsible for detecting source and 34 * type of the interrupt and dispatching matching handlers. If handling an 35 * interrupt requires calling kernel functions that may sleep processing is 36 * dispatched to work handlers. 37 * 38 * If MSI functionality is not disabled by module parameter then MSI 39 * support will be enabled. 40 * 41 * For GPU interrupt sources that may be driven by another driver, IRQ domain 42 * support is used (with mapping between virtual and hardware IRQs). 43 */ 44 45 #include <linux/irq.h> 46 #include <linux/pci.h> 47 48 #include <drm/drm_vblank.h> 49 #include <drm/amdgpu_drm.h> 50 #include <drm/drm_drv.h> 51 #include "amdgpu.h" 52 #include "amdgpu_ih.h" 53 #include "atom.h" 54 #include "amdgpu_connectors.h" 55 #include "amdgpu_trace.h" 56 #include "amdgpu_amdkfd.h" 57 #include "amdgpu_ras.h" 58 59 #include <linux/pm_runtime.h> 60 61 #ifdef CONFIG_DRM_AMD_DC 62 #include "amdgpu_dm_irq.h" 63 #endif 64 65 #define AMDGPU_WAIT_IDLE_TIMEOUT 200 66 67 const char *soc15_ih_clientid_name[] = { 68 "IH", 69 "SDMA2 or ACP", 70 "ATHUB", 71 "BIF", 72 "SDMA3 or DCE", 73 "SDMA4 or ISP", 74 "VMC1 or PCIE0", 75 "RLC", 76 "SDMA0", 77 "SDMA1", 78 "SE0SH", 79 "SE1SH", 80 "SE2SH", 81 "SE3SH", 82 "VCN1 or UVD1", 83 "THM", 84 "VCN or UVD", 85 "SDMA5 or VCE0", 86 "VMC", 87 "SDMA6 or XDMA", 88 "GRBM_CP", 89 "ATS", 90 "ROM_SMUIO", 91 "DF", 92 "SDMA7 or VCE1", 93 "PWR", 94 "reserved", 95 "UTCL2", 96 "EA", 97 "UTCL2LOG", 98 "MP0", 99 "MP1" 100 }; 101 102 const int node_id_to_phys_map[NODEID_MAX] = { 103 [AID0_NODEID] = 0, 104 [XCD0_NODEID] = 0, 105 [XCD1_NODEID] = 1, 106 [AID1_NODEID] = 1, 107 [XCD2_NODEID] = 2, 108 [XCD3_NODEID] = 3, 109 [AID2_NODEID] = 2, 110 [XCD4_NODEID] = 4, 111 [XCD5_NODEID] = 5, 112 [AID3_NODEID] = 3, 113 [XCD6_NODEID] = 6, 114 [XCD7_NODEID] = 7, 115 }; 116 117 /** 118 * amdgpu_irq_disable_all - disable *all* interrupts 119 * 120 * @adev: amdgpu device pointer 121 * 122 * Disable all types of interrupts from all sources. 123 */ 124 void amdgpu_irq_disable_all(struct amdgpu_device *adev) 125 { 126 unsigned long irqflags; 127 unsigned int i, j, k; 128 int r; 129 130 spin_lock_irqsave(&adev->irq.lock, irqflags); 131 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) { 132 if (!adev->irq.client[i].sources) 133 continue; 134 135 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) { 136 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j]; 137 138 if (!src || !src->funcs->set || !src->num_types) 139 continue; 140 141 for (k = 0; k < src->num_types; ++k) { 142 r = src->funcs->set(adev, src, k, 143 AMDGPU_IRQ_STATE_DISABLE); 144 if (r) 145 DRM_ERROR("error disabling interrupt (%d)\n", 146 r); 147 } 148 } 149 } 150 spin_unlock_irqrestore(&adev->irq.lock, irqflags); 151 } 152 153 /** 154 * amdgpu_irq_handler - IRQ handler 155 * 156 * @irq: IRQ number (unused) 157 * @arg: pointer to DRM device 158 * 159 * IRQ handler for amdgpu driver (all ASICs). 160 * 161 * Returns: 162 * result of handling the IRQ, as defined by &irqreturn_t 163 */ 164 static irqreturn_t amdgpu_irq_handler(int irq, void *arg) 165 { 166 struct drm_device *dev = (struct drm_device *) arg; 167 struct amdgpu_device *adev = drm_to_adev(dev); 168 irqreturn_t ret; 169 170 ret = amdgpu_ih_process(adev, &adev->irq.ih); 171 if (ret == IRQ_HANDLED) 172 pm_runtime_mark_last_busy(dev->dev); 173 174 amdgpu_ras_interrupt_fatal_error_handler(adev); 175 176 return ret; 177 } 178 179 /** 180 * amdgpu_irq_handle_ih1 - kick of processing for IH1 181 * 182 * @work: work structure in struct amdgpu_irq 183 * 184 * Kick of processing IH ring 1. 185 */ 186 static void amdgpu_irq_handle_ih1(struct work_struct *work) 187 { 188 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, 189 irq.ih1_work); 190 191 amdgpu_ih_process(adev, &adev->irq.ih1); 192 } 193 194 /** 195 * amdgpu_irq_handle_ih2 - kick of processing for IH2 196 * 197 * @work: work structure in struct amdgpu_irq 198 * 199 * Kick of processing IH ring 2. 200 */ 201 static void amdgpu_irq_handle_ih2(struct work_struct *work) 202 { 203 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, 204 irq.ih2_work); 205 206 amdgpu_ih_process(adev, &adev->irq.ih2); 207 } 208 209 /** 210 * amdgpu_irq_handle_ih_soft - kick of processing for ih_soft 211 * 212 * @work: work structure in struct amdgpu_irq 213 * 214 * Kick of processing IH soft ring. 215 */ 216 static void amdgpu_irq_handle_ih_soft(struct work_struct *work) 217 { 218 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, 219 irq.ih_soft_work); 220 221 amdgpu_ih_process(adev, &adev->irq.ih_soft); 222 } 223 224 /** 225 * amdgpu_msi_ok - check whether MSI functionality is enabled 226 * 227 * @adev: amdgpu device pointer (unused) 228 * 229 * Checks whether MSI functionality has been disabled via module parameter 230 * (all ASICs). 231 * 232 * Returns: 233 * *true* if MSIs are allowed to be enabled or *false* otherwise 234 */ 235 static bool amdgpu_msi_ok(struct amdgpu_device *adev) 236 { 237 if (amdgpu_msi == 1) 238 return true; 239 else if (amdgpu_msi == 0) 240 return false; 241 242 return true; 243 } 244 245 static void amdgpu_restore_msix(struct amdgpu_device *adev) 246 { 247 u16 ctrl; 248 249 pci_read_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl); 250 if (!(ctrl & PCI_MSIX_FLAGS_ENABLE)) 251 return; 252 253 /* VF FLR */ 254 ctrl &= ~PCI_MSIX_FLAGS_ENABLE; 255 pci_write_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, ctrl); 256 ctrl |= PCI_MSIX_FLAGS_ENABLE; 257 pci_write_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, ctrl); 258 } 259 260 /** 261 * amdgpu_irq_init - initialize interrupt handling 262 * 263 * @adev: amdgpu device pointer 264 * 265 * Sets up work functions for hotplug and reset interrupts, enables MSI 266 * functionality, initializes vblank, hotplug and reset interrupt handling. 267 * 268 * Returns: 269 * 0 on success or error code on failure 270 */ 271 int amdgpu_irq_init(struct amdgpu_device *adev) 272 { 273 int r = 0; 274 unsigned int irq; 275 276 spin_lock_init(&adev->irq.lock); 277 278 /* Enable MSI if not disabled by module parameter */ 279 adev->irq.msi_enabled = false; 280 281 if (amdgpu_msi_ok(adev)) { 282 int nvec = pci_msix_vec_count(adev->pdev); 283 unsigned int flags; 284 285 if (nvec <= 0) 286 flags = PCI_IRQ_MSI; 287 else 288 flags = PCI_IRQ_MSI | PCI_IRQ_MSIX; 289 290 /* we only need one vector */ 291 nvec = pci_alloc_irq_vectors(adev->pdev, 1, 1, flags); 292 if (nvec > 0) { 293 adev->irq.msi_enabled = true; 294 dev_dbg(adev->dev, "using MSI/MSI-X.\n"); 295 } 296 } 297 298 INIT_WORK(&adev->irq.ih1_work, amdgpu_irq_handle_ih1); 299 INIT_WORK(&adev->irq.ih2_work, amdgpu_irq_handle_ih2); 300 INIT_WORK(&adev->irq.ih_soft_work, amdgpu_irq_handle_ih_soft); 301 302 /* Use vector 0 for MSI-X. */ 303 r = pci_irq_vector(adev->pdev, 0); 304 if (r < 0) 305 return r; 306 irq = r; 307 308 /* PCI devices require shared interrupts. */ 309 r = request_irq(irq, amdgpu_irq_handler, IRQF_SHARED, adev_to_drm(adev)->driver->name, 310 adev_to_drm(adev)); 311 if (r) 312 return r; 313 adev->irq.installed = true; 314 adev->irq.irq = irq; 315 adev_to_drm(adev)->max_vblank_count = 0x00ffffff; 316 317 DRM_DEBUG("amdgpu: irq initialized.\n"); 318 return 0; 319 } 320 321 322 void amdgpu_irq_fini_hw(struct amdgpu_device *adev) 323 { 324 if (adev->irq.installed) { 325 free_irq(adev->irq.irq, adev_to_drm(adev)); 326 adev->irq.installed = false; 327 if (adev->irq.msi_enabled) 328 pci_free_irq_vectors(adev->pdev); 329 } 330 331 amdgpu_ih_ring_fini(adev, &adev->irq.ih_soft); 332 amdgpu_ih_ring_fini(adev, &adev->irq.ih); 333 amdgpu_ih_ring_fini(adev, &adev->irq.ih1); 334 amdgpu_ih_ring_fini(adev, &adev->irq.ih2); 335 } 336 337 /** 338 * amdgpu_irq_fini_sw - shut down interrupt handling 339 * 340 * @adev: amdgpu device pointer 341 * 342 * Tears down work functions for hotplug and reset interrupts, disables MSI 343 * functionality, shuts down vblank, hotplug and reset interrupt handling, 344 * turns off interrupts from all sources (all ASICs). 345 */ 346 void amdgpu_irq_fini_sw(struct amdgpu_device *adev) 347 { 348 unsigned int i, j; 349 350 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) { 351 if (!adev->irq.client[i].sources) 352 continue; 353 354 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) { 355 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j]; 356 357 if (!src) 358 continue; 359 360 kfree(src->enabled_types); 361 src->enabled_types = NULL; 362 } 363 kfree(adev->irq.client[i].sources); 364 adev->irq.client[i].sources = NULL; 365 } 366 } 367 368 /** 369 * amdgpu_irq_add_id - register IRQ source 370 * 371 * @adev: amdgpu device pointer 372 * @client_id: client id 373 * @src_id: source id 374 * @source: IRQ source pointer 375 * 376 * Registers IRQ source on a client. 377 * 378 * Returns: 379 * 0 on success or error code otherwise 380 */ 381 int amdgpu_irq_add_id(struct amdgpu_device *adev, 382 unsigned int client_id, unsigned int src_id, 383 struct amdgpu_irq_src *source) 384 { 385 if (client_id >= AMDGPU_IRQ_CLIENTID_MAX) 386 return -EINVAL; 387 388 if (src_id >= AMDGPU_MAX_IRQ_SRC_ID) 389 return -EINVAL; 390 391 if (!source->funcs) 392 return -EINVAL; 393 394 if (!adev->irq.client[client_id].sources) { 395 adev->irq.client[client_id].sources = 396 kcalloc(AMDGPU_MAX_IRQ_SRC_ID, 397 sizeof(struct amdgpu_irq_src *), 398 GFP_KERNEL); 399 if (!adev->irq.client[client_id].sources) 400 return -ENOMEM; 401 } 402 403 if (adev->irq.client[client_id].sources[src_id] != NULL) 404 return -EINVAL; 405 406 if (source->num_types && !source->enabled_types) { 407 atomic_t *types; 408 409 types = kcalloc(source->num_types, sizeof(atomic_t), 410 GFP_KERNEL); 411 if (!types) 412 return -ENOMEM; 413 414 source->enabled_types = types; 415 } 416 417 adev->irq.client[client_id].sources[src_id] = source; 418 return 0; 419 } 420 421 /** 422 * amdgpu_irq_dispatch - dispatch IRQ to IP blocks 423 * 424 * @adev: amdgpu device pointer 425 * @ih: interrupt ring instance 426 * 427 * Dispatches IRQ to IP blocks. 428 */ 429 void amdgpu_irq_dispatch(struct amdgpu_device *adev, 430 struct amdgpu_ih_ring *ih) 431 { 432 u32 ring_index = ih->rptr >> 2; 433 struct amdgpu_iv_entry entry; 434 unsigned int client_id, src_id; 435 struct amdgpu_irq_src *src; 436 bool handled = false; 437 int r; 438 439 entry.ih = ih; 440 entry.iv_entry = (const uint32_t *)&ih->ring[ring_index]; 441 amdgpu_ih_decode_iv(adev, &entry); 442 443 trace_amdgpu_iv(ih - &adev->irq.ih, &entry); 444 445 client_id = entry.client_id; 446 src_id = entry.src_id; 447 448 if (client_id >= AMDGPU_IRQ_CLIENTID_MAX) { 449 DRM_DEBUG("Invalid client_id in IV: %d\n", client_id); 450 451 } else if (src_id >= AMDGPU_MAX_IRQ_SRC_ID) { 452 DRM_DEBUG("Invalid src_id in IV: %d\n", src_id); 453 454 } else if ((client_id == AMDGPU_IRQ_CLIENTID_LEGACY) && 455 adev->irq.virq[src_id]) { 456 generic_handle_domain_irq(adev->irq.domain, src_id); 457 458 } else if (!adev->irq.client[client_id].sources) { 459 DRM_DEBUG("Unregistered interrupt client_id: %d src_id: %d\n", 460 client_id, src_id); 461 462 } else if ((src = adev->irq.client[client_id].sources[src_id])) { 463 r = src->funcs->process(adev, src, &entry); 464 if (r < 0) 465 DRM_ERROR("error processing interrupt (%d)\n", r); 466 else if (r) 467 handled = true; 468 469 } else { 470 DRM_DEBUG("Unhandled interrupt src_id: %d\n", src_id); 471 } 472 473 /* Send it to amdkfd as well if it isn't already handled */ 474 if (!handled) 475 amdgpu_amdkfd_interrupt(adev, entry.iv_entry); 476 477 if (amdgpu_ih_ts_after(ih->processed_timestamp, entry.timestamp)) 478 ih->processed_timestamp = entry.timestamp; 479 } 480 481 /** 482 * amdgpu_irq_delegate - delegate IV to soft IH ring 483 * 484 * @adev: amdgpu device pointer 485 * @entry: IV entry 486 * @num_dw: size of IV 487 * 488 * Delegate the IV to the soft IH ring and schedule processing of it. Used 489 * if the hardware delegation to IH1 or IH2 doesn't work for some reason. 490 */ 491 void amdgpu_irq_delegate(struct amdgpu_device *adev, 492 struct amdgpu_iv_entry *entry, 493 unsigned int num_dw) 494 { 495 amdgpu_ih_ring_write(&adev->irq.ih_soft, entry->iv_entry, num_dw); 496 schedule_work(&adev->irq.ih_soft_work); 497 } 498 499 /** 500 * amdgpu_irq_update - update hardware interrupt state 501 * 502 * @adev: amdgpu device pointer 503 * @src: interrupt source pointer 504 * @type: type of interrupt 505 * 506 * Updates interrupt state for the specific source (all ASICs). 507 */ 508 int amdgpu_irq_update(struct amdgpu_device *adev, 509 struct amdgpu_irq_src *src, unsigned int type) 510 { 511 unsigned long irqflags; 512 enum amdgpu_interrupt_state state; 513 int r; 514 515 spin_lock_irqsave(&adev->irq.lock, irqflags); 516 517 /* We need to determine after taking the lock, otherwise 518 * we might disable just enabled interrupts again 519 */ 520 if (amdgpu_irq_enabled(adev, src, type)) 521 state = AMDGPU_IRQ_STATE_ENABLE; 522 else 523 state = AMDGPU_IRQ_STATE_DISABLE; 524 525 r = src->funcs->set(adev, src, type, state); 526 spin_unlock_irqrestore(&adev->irq.lock, irqflags); 527 return r; 528 } 529 530 /** 531 * amdgpu_irq_gpu_reset_resume_helper - update interrupt states on all sources 532 * 533 * @adev: amdgpu device pointer 534 * 535 * Updates state of all types of interrupts on all sources on resume after 536 * reset. 537 */ 538 void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev) 539 { 540 int i, j, k; 541 542 if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev)) 543 amdgpu_restore_msix(adev); 544 545 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) { 546 if (!adev->irq.client[i].sources) 547 continue; 548 549 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) { 550 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j]; 551 552 if (!src || !src->funcs || !src->funcs->set) 553 continue; 554 for (k = 0; k < src->num_types; k++) 555 amdgpu_irq_update(adev, src, k); 556 } 557 } 558 } 559 560 /** 561 * amdgpu_irq_get - enable interrupt 562 * 563 * @adev: amdgpu device pointer 564 * @src: interrupt source pointer 565 * @type: type of interrupt 566 * 567 * Enables specified type of interrupt on the specified source (all ASICs). 568 * 569 * Returns: 570 * 0 on success or error code otherwise 571 */ 572 int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src, 573 unsigned int type) 574 { 575 if (!adev->irq.installed) 576 return -ENOENT; 577 578 if (type >= src->num_types) 579 return -EINVAL; 580 581 if (!src->enabled_types || !src->funcs->set) 582 return -EINVAL; 583 584 if (atomic_inc_return(&src->enabled_types[type]) == 1) 585 return amdgpu_irq_update(adev, src, type); 586 587 return 0; 588 } 589 590 /** 591 * amdgpu_irq_put - disable interrupt 592 * 593 * @adev: amdgpu device pointer 594 * @src: interrupt source pointer 595 * @type: type of interrupt 596 * 597 * Enables specified type of interrupt on the specified source (all ASICs). 598 * 599 * Returns: 600 * 0 on success or error code otherwise 601 */ 602 int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src, 603 unsigned int type) 604 { 605 if (!adev->irq.installed) 606 return -ENOENT; 607 608 if (type >= src->num_types) 609 return -EINVAL; 610 611 if (!src->enabled_types || !src->funcs->set) 612 return -EINVAL; 613 614 if (WARN_ON(!amdgpu_irq_enabled(adev, src, type))) 615 return -EINVAL; 616 617 if (atomic_dec_and_test(&src->enabled_types[type])) 618 return amdgpu_irq_update(adev, src, type); 619 620 return 0; 621 } 622 623 /** 624 * amdgpu_irq_enabled - check whether interrupt is enabled or not 625 * 626 * @adev: amdgpu device pointer 627 * @src: interrupt source pointer 628 * @type: type of interrupt 629 * 630 * Checks whether the given type of interrupt is enabled on the given source. 631 * 632 * Returns: 633 * *true* if interrupt is enabled, *false* if interrupt is disabled or on 634 * invalid parameters 635 */ 636 bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src, 637 unsigned int type) 638 { 639 if (!adev->irq.installed) 640 return false; 641 642 if (type >= src->num_types) 643 return false; 644 645 if (!src->enabled_types || !src->funcs->set) 646 return false; 647 648 return !!atomic_read(&src->enabled_types[type]); 649 } 650 651 /* XXX: Generic IRQ handling */ 652 static void amdgpu_irq_mask(struct irq_data *irqd) 653 { 654 /* XXX */ 655 } 656 657 static void amdgpu_irq_unmask(struct irq_data *irqd) 658 { 659 /* XXX */ 660 } 661 662 /* amdgpu hardware interrupt chip descriptor */ 663 static struct irq_chip amdgpu_irq_chip = { 664 .name = "amdgpu-ih", 665 .irq_mask = amdgpu_irq_mask, 666 .irq_unmask = amdgpu_irq_unmask, 667 }; 668 669 /** 670 * amdgpu_irqdomain_map - create mapping between virtual and hardware IRQ numbers 671 * 672 * @d: amdgpu IRQ domain pointer (unused) 673 * @irq: virtual IRQ number 674 * @hwirq: hardware irq number 675 * 676 * Current implementation assigns simple interrupt handler to the given virtual 677 * IRQ. 678 * 679 * Returns: 680 * 0 on success or error code otherwise 681 */ 682 static int amdgpu_irqdomain_map(struct irq_domain *d, 683 unsigned int irq, irq_hw_number_t hwirq) 684 { 685 if (hwirq >= AMDGPU_MAX_IRQ_SRC_ID) 686 return -EPERM; 687 688 irq_set_chip_and_handler(irq, 689 &amdgpu_irq_chip, handle_simple_irq); 690 return 0; 691 } 692 693 /* Implementation of methods for amdgpu IRQ domain */ 694 static const struct irq_domain_ops amdgpu_hw_irqdomain_ops = { 695 .map = amdgpu_irqdomain_map, 696 }; 697 698 /** 699 * amdgpu_irq_add_domain - create a linear IRQ domain 700 * 701 * @adev: amdgpu device pointer 702 * 703 * Creates an IRQ domain for GPU interrupt sources 704 * that may be driven by another driver (e.g., ACP). 705 * 706 * Returns: 707 * 0 on success or error code otherwise 708 */ 709 int amdgpu_irq_add_domain(struct amdgpu_device *adev) 710 { 711 adev->irq.domain = irq_domain_add_linear(NULL, AMDGPU_MAX_IRQ_SRC_ID, 712 &amdgpu_hw_irqdomain_ops, adev); 713 if (!adev->irq.domain) { 714 DRM_ERROR("GPU irq add domain failed\n"); 715 return -ENODEV; 716 } 717 718 return 0; 719 } 720 721 /** 722 * amdgpu_irq_remove_domain - remove the IRQ domain 723 * 724 * @adev: amdgpu device pointer 725 * 726 * Removes the IRQ domain for GPU interrupt sources 727 * that may be driven by another driver (e.g., ACP). 728 */ 729 void amdgpu_irq_remove_domain(struct amdgpu_device *adev) 730 { 731 if (adev->irq.domain) { 732 irq_domain_remove(adev->irq.domain); 733 adev->irq.domain = NULL; 734 } 735 } 736 737 /** 738 * amdgpu_irq_create_mapping - create mapping between domain Linux IRQs 739 * 740 * @adev: amdgpu device pointer 741 * @src_id: IH source id 742 * 743 * Creates mapping between a domain IRQ (GPU IH src id) and a Linux IRQ 744 * Use this for components that generate a GPU interrupt, but are driven 745 * by a different driver (e.g., ACP). 746 * 747 * Returns: 748 * Linux IRQ 749 */ 750 unsigned int amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned int src_id) 751 { 752 adev->irq.virq[src_id] = irq_create_mapping(adev->irq.domain, src_id); 753 754 return adev->irq.virq[src_id]; 755 } 756