1 /* 2 * Copyright 2025 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_IP_H__ 25 #define __AMDGPU_IP_H__ 26 27 #include "amd_shared.h" 28 29 struct amdgpu_device; 30 31 /* Define the HW IP blocks will be used in driver , add more if necessary */ 32 enum amd_hw_ip_block_type { 33 GC_HWIP = 1, 34 HDP_HWIP, 35 SDMA0_HWIP, 36 SDMA1_HWIP, 37 SDMA2_HWIP, 38 SDMA3_HWIP, 39 SDMA4_HWIP, 40 SDMA5_HWIP, 41 SDMA6_HWIP, 42 SDMA7_HWIP, 43 LSDMA_HWIP, 44 MMHUB_HWIP, 45 ATHUB_HWIP, 46 NBIO_HWIP, 47 MP0_HWIP, 48 MP1_HWIP, 49 UVD_HWIP, 50 VCN_HWIP = UVD_HWIP, 51 JPEG_HWIP = VCN_HWIP, 52 VCN1_HWIP, 53 VCE_HWIP, 54 VPE_HWIP, 55 DF_HWIP, 56 DCE_HWIP, 57 OSSSYS_HWIP, 58 SMUIO_HWIP, 59 PWR_HWIP, 60 NBIF_HWIP, 61 THM_HWIP, 62 CLK_HWIP, 63 UMC_HWIP, 64 RSMU_HWIP, 65 XGMI_HWIP, 66 DCI_HWIP, 67 PCIE_HWIP, 68 ISP_HWIP, 69 ATU_HWIP, 70 AIGC_HWIP, 71 UMSCH_HWIP, 72 MAX_HWIP 73 }; 74 75 #define HWIP_MAX_INSTANCE 48 76 77 #define HW_ID_MAX 300 78 #define IP_VERSION_FULL(mj, mn, rv, var, srev) \ 79 (((mj) << 24) | ((mn) << 16) | ((rv) << 8) | ((var) << 4) | (srev)) 80 #define IP_VERSION(mj, mn, rv) IP_VERSION_FULL(mj, mn, rv, 0, 0) 81 #define IP_VERSION_MAJ(ver) ((ver) >> 24) 82 #define IP_VERSION_MIN(ver) (((ver) >> 16) & 0xFF) 83 #define IP_VERSION_REV(ver) (((ver) >> 8) & 0xFF) 84 #define IP_VERSION_VARIANT(ver) (((ver) >> 4) & 0xF) 85 #define IP_VERSION_SUBREV(ver) ((ver) & 0xF) 86 #define IP_VERSION_MAJ_MIN_REV(ver) ((ver) >> 8) 87 88 struct amdgpu_ring; 89 struct amdgpu_fence; 90 91 struct amdgpu_ip_map_info { 92 /* Map of logical to actual dev instances/mask */ 93 uint32_t dev_inst[MAX_HWIP][HWIP_MAX_INSTANCE]; 94 int8_t (*logical_to_dev_inst)(struct amdgpu_device *adev, 95 enum amd_hw_ip_block_type block, 96 int8_t inst); 97 uint32_t (*logical_to_dev_mask)(struct amdgpu_device *adev, 98 enum amd_hw_ip_block_type block, 99 uint32_t mask); 100 }; 101 102 #define AMDGPU_MAX_IP_NUM AMD_IP_BLOCK_TYPE_NUM 103 104 struct amdgpu_ip_block_status { 105 bool valid; 106 bool sw; 107 bool hw; 108 bool late_initialized; 109 bool hang; 110 }; 111 112 struct amdgpu_ip_block_version { 113 const enum amd_ip_block_type type; 114 const u32 major; 115 const u32 minor; 116 const u32 rev; 117 const struct amd_ip_funcs *funcs; 118 }; 119 120 struct amdgpu_ip_block { 121 struct amdgpu_ip_block_status status; 122 const struct amdgpu_ip_block_version *version; 123 struct amdgpu_device *adev; 124 }; 125 126 void amdgpu_ip_map_init(struct amdgpu_device *adev); 127 128 int amdgpu_ip_block_suspend(struct amdgpu_ip_block *ip_block); 129 int amdgpu_ip_block_resume(struct amdgpu_ip_block *ip_block); 130 131 struct amdgpu_ip_block * 132 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 133 enum amd_ip_block_type type); 134 135 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 136 enum amd_ip_block_type type, u32 major, 137 u32 minor); 138 139 int amdgpu_device_ip_block_add( 140 struct amdgpu_device *adev, 141 const struct amdgpu_ip_block_version *ip_block_version); 142 143 int amdgpu_device_ip_set_clockgating_state(struct amdgpu_device *adev, 144 enum amd_ip_block_type block_type, 145 enum amd_clockgating_state state); 146 int amdgpu_device_ip_set_powergating_state(struct amdgpu_device *adev, 147 enum amd_ip_block_type block_type, 148 enum amd_powergating_state state); 149 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 150 u64 *flags); 151 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 152 enum amd_ip_block_type block_type); 153 bool amdgpu_device_ip_is_valid(struct amdgpu_device *adev, 154 enum amd_ip_block_type block_type); 155 int amdgpu_device_ip_soft_reset(struct amdgpu_ring *guilty_ring, 156 struct amdgpu_fence *guilty_fence); 157 158 #endif /* __AMDGPU_IP_H__ */ 159