1 /* 2 * Copyright 2025 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "amdgpu_ip.h" 26 27 static int8_t amdgpu_logical_to_dev_inst(struct amdgpu_device *adev, 28 enum amd_hw_ip_block_type block, 29 int8_t inst) 30 { 31 int8_t dev_inst; 32 33 switch (block) { 34 case GC_HWIP: 35 case SDMA0_HWIP: 36 /* Both JPEG and VCN as JPEG is only alias of VCN */ 37 case VCN_HWIP: 38 dev_inst = adev->ip_map.dev_inst[block][inst]; 39 break; 40 default: 41 /* For rest of the IPs, no look up required. 42 * Assume 'logical instance == physical instance' for all configs. */ 43 dev_inst = inst; 44 break; 45 } 46 47 return dev_inst; 48 } 49 50 static uint32_t amdgpu_logical_to_dev_mask(struct amdgpu_device *adev, 51 enum amd_hw_ip_block_type block, 52 uint32_t mask) 53 { 54 uint32_t dev_mask = 0; 55 int8_t log_inst, dev_inst; 56 57 while (mask) { 58 log_inst = ffs(mask) - 1; 59 dev_inst = amdgpu_logical_to_dev_inst(adev, block, log_inst); 60 dev_mask |= (1 << dev_inst); 61 mask &= ~(1 << log_inst); 62 } 63 64 return dev_mask; 65 } 66 67 static void amdgpu_populate_ip_map(struct amdgpu_device *adev, 68 enum amd_hw_ip_block_type ip_block, 69 uint32_t inst_mask) 70 { 71 int l = 0, i; 72 73 while (inst_mask) { 74 i = ffs(inst_mask) - 1; 75 adev->ip_map.dev_inst[ip_block][l++] = i; 76 inst_mask &= ~(1 << i); 77 } 78 for (; l < HWIP_MAX_INSTANCE; l++) 79 adev->ip_map.dev_inst[ip_block][l] = -1; 80 } 81 82 void amdgpu_ip_map_init(struct amdgpu_device *adev) 83 { 84 u32 ip_map[][2] = { 85 { GC_HWIP, adev->gfx.xcc_mask }, 86 { SDMA0_HWIP, adev->sdma.sdma_mask }, 87 { VCN_HWIP, adev->vcn.inst_mask }, 88 }; 89 int i; 90 91 for (i = 0; i < ARRAY_SIZE(ip_map); ++i) 92 amdgpu_populate_ip_map(adev, ip_map[i][0], ip_map[i][1]); 93 94 adev->ip_map.logical_to_dev_inst = amdgpu_logical_to_dev_inst; 95 adev->ip_map.logical_to_dev_mask = amdgpu_logical_to_dev_mask; 96 } 97 98 int amdgpu_ip_block_suspend(struct amdgpu_ip_block *ip_block) 99 { 100 int r; 101 102 if (ip_block->version->funcs->suspend) { 103 r = ip_block->version->funcs->suspend(ip_block); 104 if (r) { 105 dev_err(ip_block->adev->dev, 106 "suspend of IP block <%s> failed %d\n", 107 ip_block->version->funcs->name, r); 108 return r; 109 } 110 } 111 112 ip_block->status.hw = false; 113 return 0; 114 } 115 116 int amdgpu_ip_block_resume(struct amdgpu_ip_block *ip_block) 117 { 118 int r; 119 120 if (ip_block->version->funcs->resume) { 121 r = ip_block->version->funcs->resume(ip_block); 122 if (r) { 123 dev_err(ip_block->adev->dev, 124 "resume of IP block <%s> failed %d\n", 125 ip_block->version->funcs->name, r); 126 return r; 127 } 128 } 129 130 ip_block->status.hw = true; 131 return 0; 132 } 133 134 /** 135 * amdgpu_device_ip_get_ip_block - get a hw IP pointer 136 * 137 * @adev: amdgpu_device pointer 138 * @type: Type of hardware IP (SMU, GFX, UVD, etc.) 139 * 140 * Returns a pointer to the hardware IP block structure 141 * if it exists for the asic, otherwise NULL. 142 */ 143 struct amdgpu_ip_block * 144 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 145 enum amd_ip_block_type type) 146 { 147 int i; 148 149 for (i = 0; i < adev->num_ip_blocks; i++) 150 if (adev->ip_blocks[i].version->type == type) 151 return &adev->ip_blocks[i]; 152 153 return NULL; 154 } 155 156 /** 157 * amdgpu_device_ip_block_version_cmp 158 * 159 * @adev: amdgpu_device pointer 160 * @type: enum amd_ip_block_type 161 * @major: major version 162 * @minor: minor version 163 * 164 * return 0 if equal or greater 165 * return 1 if smaller or the ip_block doesn't exist 166 */ 167 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 168 enum amd_ip_block_type type, u32 major, 169 u32 minor) 170 { 171 struct amdgpu_ip_block *ip_block = 172 amdgpu_device_ip_get_ip_block(adev, type); 173 174 if (ip_block && ((ip_block->version->major > major) || 175 ((ip_block->version->major == major) && 176 (ip_block->version->minor >= minor)))) 177 return 0; 178 179 return 1; 180 } 181 182 static const char *const ip_block_names[] = { 183 [AMD_IP_BLOCK_TYPE_COMMON] = "common", 184 [AMD_IP_BLOCK_TYPE_GMC] = "gmc", 185 [AMD_IP_BLOCK_TYPE_IH] = "ih", 186 [AMD_IP_BLOCK_TYPE_SMC] = "smu", 187 [AMD_IP_BLOCK_TYPE_PSP] = "psp", 188 [AMD_IP_BLOCK_TYPE_DCE] = "dce", 189 [AMD_IP_BLOCK_TYPE_GFX] = "gfx", 190 [AMD_IP_BLOCK_TYPE_SDMA] = "sdma", 191 [AMD_IP_BLOCK_TYPE_UVD] = "uvd", 192 [AMD_IP_BLOCK_TYPE_VCE] = "vce", 193 [AMD_IP_BLOCK_TYPE_ACP] = "acp", 194 [AMD_IP_BLOCK_TYPE_VCN] = "vcn", 195 [AMD_IP_BLOCK_TYPE_MES] = "mes", 196 [AMD_IP_BLOCK_TYPE_JPEG] = "jpeg", 197 [AMD_IP_BLOCK_TYPE_VPE] = "vpe", 198 [AMD_IP_BLOCK_TYPE_UMSCH_MM] = "umsch_mm", 199 [AMD_IP_BLOCK_TYPE_ISP] = "isp", 200 [AMD_IP_BLOCK_TYPE_RAS] = "ras", 201 }; 202 203 static const char *ip_block_name(struct amdgpu_device *adev, 204 enum amd_ip_block_type type) 205 { 206 int idx = (int)type; 207 208 return idx < ARRAY_SIZE(ip_block_names) ? ip_block_names[idx] : 209 "unknown"; 210 } 211 212 /** 213 * amdgpu_device_ip_block_add 214 * 215 * @adev: amdgpu_device pointer 216 * @ip_block_version: pointer to the IP to add 217 * 218 * Adds the IP block driver information to the collection of IPs 219 * on the asic. 220 */ 221 int amdgpu_device_ip_block_add( 222 struct amdgpu_device *adev, 223 const struct amdgpu_ip_block_version *ip_block_version) 224 { 225 if (!ip_block_version) 226 return -EINVAL; 227 228 switch (ip_block_version->type) { 229 case AMD_IP_BLOCK_TYPE_VCN: 230 if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK) 231 return 0; 232 break; 233 case AMD_IP_BLOCK_TYPE_JPEG: 234 if (adev->harvest_ip_mask & AMD_HARVEST_IP_JPEG_MASK) 235 return 0; 236 break; 237 default: 238 break; 239 } 240 241 dev_info(adev->dev, "detected ip block number %d <%s_v%d_%d_%d> (%s)\n", 242 adev->num_ip_blocks, 243 ip_block_name(adev, ip_block_version->type), 244 ip_block_version->major, ip_block_version->minor, 245 ip_block_version->rev, ip_block_version->funcs->name); 246 247 adev->ip_blocks[adev->num_ip_blocks].adev = adev; 248 249 adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version; 250 251 return 0; 252 } 253 254 /** 255 * amdgpu_device_ip_set_clockgating_state - set the CG state 256 * 257 * @adev: amdgpu_device pointer 258 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) 259 * @state: clockgating state (gate or ungate) 260 * 261 * Sets the requested clockgating state for all instances of 262 * the hardware IP specified. 263 * Returns the error code from the last instance. 264 */ 265 int amdgpu_device_ip_set_clockgating_state(struct amdgpu_device *adev, 266 enum amd_ip_block_type block_type, 267 enum amd_clockgating_state state) 268 { 269 int i, r = 0; 270 271 for (i = 0; i < adev->num_ip_blocks; i++) { 272 if (!adev->ip_blocks[i].status.valid) 273 continue; 274 if (adev->ip_blocks[i].version->type != block_type) 275 continue; 276 if (!adev->ip_blocks[i].version->funcs->set_clockgating_state) 277 continue; 278 r = adev->ip_blocks[i].version->funcs->set_clockgating_state( 279 &adev->ip_blocks[i], state); 280 if (r) 281 dev_err(adev->dev, 282 "set_clockgating_state of IP block <%s> failed %d\n", 283 adev->ip_blocks[i].version->funcs->name, r); 284 } 285 return r; 286 } 287 288 /** 289 * amdgpu_device_ip_set_powergating_state - set the PG state 290 * 291 * @adev: amdgpu_device pointer 292 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) 293 * @state: powergating state (gate or ungate) 294 * 295 * Sets the requested powergating state for all instances of 296 * the hardware IP specified. 297 * Returns the error code from the last instance. 298 */ 299 int amdgpu_device_ip_set_powergating_state(struct amdgpu_device *adev, 300 enum amd_ip_block_type block_type, 301 enum amd_powergating_state state) 302 { 303 int i, r = 0; 304 305 for (i = 0; i < adev->num_ip_blocks; i++) { 306 if (!adev->ip_blocks[i].status.valid) 307 continue; 308 if (adev->ip_blocks[i].version->type != block_type) 309 continue; 310 if (!adev->ip_blocks[i].version->funcs->set_powergating_state) 311 continue; 312 r = adev->ip_blocks[i].version->funcs->set_powergating_state( 313 &adev->ip_blocks[i], state); 314 if (r) 315 dev_err(adev->dev, 316 "set_powergating_state of IP block <%s> failed %d\n", 317 adev->ip_blocks[i].version->funcs->name, r); 318 } 319 return r; 320 } 321 322 /** 323 * amdgpu_device_ip_get_clockgating_state - get the CG state 324 * 325 * @adev: amdgpu_device pointer 326 * @flags: clockgating feature flags 327 * 328 * Walks the list of IPs on the device and updates the clockgating 329 * flags for each IP. 330 * Updates @flags with the feature flags for each hardware IP where 331 * clockgating is enabled. 332 */ 333 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 334 u64 *flags) 335 { 336 int i; 337 338 for (i = 0; i < adev->num_ip_blocks; i++) { 339 if (!adev->ip_blocks[i].status.valid) 340 continue; 341 if (adev->ip_blocks[i].version->funcs->get_clockgating_state) 342 adev->ip_blocks[i].version->funcs->get_clockgating_state( 343 &adev->ip_blocks[i], flags); 344 } 345 } 346 347 /** 348 * amdgpu_device_ip_wait_for_idle - wait for idle 349 * 350 * @adev: amdgpu_device pointer 351 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) 352 * 353 * Waits for the request hardware IP to be idle. 354 * Returns 0 for success or a negative error code on failure. 355 */ 356 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 357 enum amd_ip_block_type block_type) 358 { 359 struct amdgpu_ip_block *ip_block; 360 361 ip_block = amdgpu_device_ip_get_ip_block(adev, block_type); 362 if (!ip_block || !ip_block->status.valid) 363 return 0; 364 365 if (ip_block->version->funcs->wait_for_idle) 366 return ip_block->version->funcs->wait_for_idle(ip_block); 367 368 return 0; 369 } 370 371 /** 372 * amdgpu_device_ip_is_valid - is the hardware IP valid 373 * 374 * @adev: amdgpu_device pointer 375 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) 376 * 377 * Check if the hardware IP is valid or not. 378 * Returns true if it the IP is valid, false if not. 379 */ 380 bool amdgpu_device_ip_is_valid(struct amdgpu_device *adev, 381 enum amd_ip_block_type block_type) 382 { 383 struct amdgpu_ip_block *ip_block; 384 385 ip_block = amdgpu_device_ip_get_ip_block(adev, block_type); 386 if (ip_block) 387 return ip_block->status.valid; 388 389 return false; 390 } 391 392 /** 393 * amdgpu_ip_from_ring() - Find IP block type corresponding to ring type. 394 * 395 * @ring_type: The ring type whose IP block you are looking for. 396 */ 397 static enum amd_ip_block_type amdgpu_ip_from_ring(const enum amdgpu_ring_type ring_type) 398 { 399 switch (ring_type) { 400 case AMDGPU_RING_TYPE_GFX: 401 case AMDGPU_RING_TYPE_COMPUTE: 402 return AMD_IP_BLOCK_TYPE_GFX; 403 404 case AMDGPU_RING_TYPE_SDMA: 405 return AMD_IP_BLOCK_TYPE_SDMA; 406 407 case AMDGPU_RING_TYPE_UVD: 408 case AMDGPU_RING_TYPE_UVD_ENC: 409 return AMD_IP_BLOCK_TYPE_UVD; 410 411 case AMDGPU_RING_TYPE_VCE: 412 return AMD_IP_BLOCK_TYPE_VCE; 413 414 case AMDGPU_RING_TYPE_VCN_DEC: 415 case AMDGPU_RING_TYPE_VCN_ENC: 416 return AMD_IP_BLOCK_TYPE_VCN; 417 418 case AMDGPU_RING_TYPE_VCN_JPEG: 419 return AMD_IP_BLOCK_TYPE_JPEG; 420 421 case AMDGPU_RING_TYPE_VPE: 422 return AMD_IP_BLOCK_TYPE_VPE; 423 424 default: 425 return AMD_IP_BLOCK_TYPE_NUM; 426 } 427 } 428 429 /** 430 * amdgpu_ring_mask_from_ip() - Find mask of ring types corresponding to an IP block type. 431 * 432 * @ip_type: The IP block type whose rings you are looking for. 433 */ 434 static u32 amdgpu_ring_mask_from_ip(const enum amd_ip_block_type ip_type) 435 { 436 switch (ip_type) { 437 case AMD_IP_BLOCK_TYPE_GFX: 438 return BIT(AMDGPU_RING_TYPE_GFX) | BIT(AMDGPU_RING_TYPE_COMPUTE); 439 440 case AMD_IP_BLOCK_TYPE_SDMA: 441 return BIT(AMDGPU_RING_TYPE_SDMA); 442 443 case AMD_IP_BLOCK_TYPE_UVD: 444 return BIT(AMDGPU_RING_TYPE_UVD) | BIT(AMDGPU_RING_TYPE_UVD_ENC); 445 446 case AMD_IP_BLOCK_TYPE_VCE: 447 return BIT(AMD_IP_BLOCK_TYPE_VCE); 448 449 case AMD_IP_BLOCK_TYPE_VCN: 450 return BIT(AMDGPU_RING_TYPE_VCN_DEC) | BIT(AMDGPU_RING_TYPE_VCN_ENC); 451 452 case AMD_IP_BLOCK_TYPE_JPEG: 453 return BIT(AMDGPU_RING_TYPE_VCN_JPEG); 454 455 case AMD_IP_BLOCK_TYPE_VPE: 456 return BIT(AMDGPU_RING_TYPE_VPE); 457 458 default: 459 return 0; 460 } 461 } 462 463 /** 464 * amdgpu_device_ip_soft_reset() - Perform a graceful soft reset on an IP block. 465 * 466 * @guilty_ring: The ring which is guilty of causing a reset. 467 * @guilty_fence: The fence which didn't signal. 468 * 469 * IP block soft reset is used when attempting to recover 470 * from a GPU hang in a situation where a more fine grained 471 * reset type isn't available or didn't work. This effectively 472 * resets all rings that belong to the same device IP block 473 * and re-initializes the device IP block. 474 * 475 * The reset is handled gracefully, meaning that we try to 476 * minimize collateral damage (ie. avoid rejecting non-guilty jobs) 477 * as well as back up and restore the contents of all rings 478 * so that the system can move on from the hang. 479 */ 480 int amdgpu_device_ip_soft_reset(struct amdgpu_ring *guilty_ring, 481 struct amdgpu_fence *guilty_fence) 482 { 483 struct amdgpu_device *adev = guilty_ring->adev; 484 struct amdgpu_ip_block *ip_block; 485 enum amd_ip_block_type ip_type; 486 u32 ring_type_mask; 487 int r; 488 489 ip_type = amdgpu_ip_from_ring(guilty_ring->funcs->type); 490 ip_block = amdgpu_device_ip_get_ip_block(adev, ip_type); 491 492 if (unlikely(!ip_block)) { 493 dev_warn(adev->dev, "IP block not found for ring %s\n", 494 guilty_ring->name); 495 return -EOPNOTSUPP; 496 } 497 498 if (!ip_block->version->funcs->soft_reset) { 499 dev_warn(adev->dev, "IP block soft reset not supported on %s\n", 500 ip_block->version->funcs->name); 501 return -EOPNOTSUPP; 502 } 503 504 dev_err(adev->dev, "Starting %s IP block soft reset\n", 505 ip_block->version->funcs->name); 506 507 ring_type_mask = amdgpu_ring_mask_from_ip(ip_type); 508 509 amdgpu_device_lock_reset_domain(adev->reset_domain); 510 amdgpu_multi_ring_reset_helper_begin(ring_type_mask, guilty_ring, guilty_fence); 511 512 r = ip_block->version->funcs->soft_reset(ip_block); 513 514 r = amdgpu_multi_ring_reset_helper_end(ring_type_mask, guilty_ring, r); 515 amdgpu_device_unlock_reset_domain(adev->reset_domain); 516 517 if (r) { 518 dev_err(adev->dev, "Failed %s IP block soft reset: %d\n", 519 ip_block->version->funcs->name, r); 520 return r; 521 } 522 523 dev_err(adev->dev, "Successful %s IP block soft reset\n", 524 ip_block->version->funcs->name); 525 return 0; 526 } 527