1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_IMU_H__ 25 #define __AMDGPU_IMU_H__ 26 27 enum imu_work_mode { 28 DEBUG_MODE, 29 MISSION_MODE 30 }; 31 32 struct amdgpu_imu_funcs { 33 int (*init_microcode)(struct amdgpu_device *adev); 34 int (*load_microcode)(struct amdgpu_device *adev); 35 void (*setup_imu)(struct amdgpu_device *adev); 36 int (*start_imu)(struct amdgpu_device *adev); 37 void (*program_rlc_ram)(struct amdgpu_device *adev); 38 int (*wait_for_reset_status)(struct amdgpu_device *adev); 39 int (*switch_compute_partition)(struct amdgpu_device *adev, 40 int num_xccs_per_xcp, 41 int compute_partition_mode); 42 void (*init_mcm_addr_lut)(struct amdgpu_device *adev); 43 }; 44 45 struct imu_rlc_ram_golden { 46 u32 hwip; 47 u32 instance; 48 u32 segment; 49 u32 reg; 50 u32 data; 51 u32 addr_mask; 52 }; 53 54 #define IMU_RLC_RAM_GOLDEN_VALUE(ip, inst, reg, data, addr_mask) \ 55 { ip##_HWIP, inst, reg##_BASE_IDX, reg, data, addr_mask } 56 57 struct amdgpu_imu { 58 const struct amdgpu_imu_funcs *funcs; 59 enum imu_work_mode mode; 60 }; 61 62 #endif 63