xref: /linux/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h (revision 4f2c0a4acffbec01079c28f839422e64ddeff004)
1289bcffbSLikun Gao /*
2289bcffbSLikun Gao  * Copyright 2021 Advanced Micro Devices, Inc.
3289bcffbSLikun Gao  *
4289bcffbSLikun Gao  * Permission is hereby granted, free of charge, to any person obtaining a
5289bcffbSLikun Gao  * copy of this software and associated documentation files (the "Software"),
6289bcffbSLikun Gao  * to deal in the Software without restriction, including without limitation
7289bcffbSLikun Gao  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8289bcffbSLikun Gao  * and/or sell copies of the Software, and to permit persons to whom the
9289bcffbSLikun Gao  * Software is furnished to do so, subject to the following conditions:
10289bcffbSLikun Gao  *
11289bcffbSLikun Gao  * The above copyright notice and this permission notice shall be included in
12289bcffbSLikun Gao  * all copies or substantial portions of the Software.
13289bcffbSLikun Gao  *
14289bcffbSLikun Gao  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15289bcffbSLikun Gao  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16289bcffbSLikun Gao  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17289bcffbSLikun Gao  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18289bcffbSLikun Gao  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19289bcffbSLikun Gao  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20289bcffbSLikun Gao  * OTHER DEALINGS IN THE SOFTWARE.
21289bcffbSLikun Gao  *
22289bcffbSLikun Gao  */
23289bcffbSLikun Gao 
24289bcffbSLikun Gao #ifndef __AMDGPU_IMU_H__
25289bcffbSLikun Gao #define __AMDGPU_IMU_H__
26289bcffbSLikun Gao 
27542a0f2eSHuang Rui enum imu_work_mode {
28542a0f2eSHuang Rui 	DEBUG_MODE,
29542a0f2eSHuang Rui 	MISSION_MODE
30542a0f2eSHuang Rui };
31542a0f2eSHuang Rui 
32289bcffbSLikun Gao struct amdgpu_imu_funcs {
33289bcffbSLikun Gao     int (*init_microcode)(struct amdgpu_device *adev);
34289bcffbSLikun Gao     int (*load_microcode)(struct amdgpu_device *adev);
35289bcffbSLikun Gao     void (*setup_imu)(struct amdgpu_device *adev);
36289bcffbSLikun Gao     int (*start_imu)(struct amdgpu_device *adev);
37289bcffbSLikun Gao     void (*program_rlc_ram)(struct amdgpu_device *adev);
38*16600b7dSHuang Rui     int (*wait_for_reset_status)(struct amdgpu_device *adev);
39289bcffbSLikun Gao };
40289bcffbSLikun Gao 
41289bcffbSLikun Gao struct imu_rlc_ram_golden {
42289bcffbSLikun Gao     u32 hwip;
43289bcffbSLikun Gao     u32 instance;
44289bcffbSLikun Gao     u32 segment;
45289bcffbSLikun Gao     u32 reg;
46289bcffbSLikun Gao     u32 data;
47289bcffbSLikun Gao     u32 addr_mask;
48289bcffbSLikun Gao };
49289bcffbSLikun Gao 
50289bcffbSLikun Gao #define IMU_RLC_RAM_GOLDEN_VALUE(ip, inst, reg, data, addr_mask) \
51289bcffbSLikun Gao     { ip##_HWIP, inst, reg##_BASE_IDX, reg, data, addr_mask }
52289bcffbSLikun Gao 
53289bcffbSLikun Gao struct amdgpu_imu {
54289bcffbSLikun Gao     const struct amdgpu_imu_funcs *funcs;
55542a0f2eSHuang Rui     enum imu_work_mode mode;
56289bcffbSLikun Gao };
57289bcffbSLikun Gao 
58289bcffbSLikun Gao #endif
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