xref: /linux/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h (revision 6a143a7cf94730f57544ea14a987dc025364dbb8)
1 /*
2  * Copyright 2014 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #ifndef __AMDGPU_IH_H__
25 #define __AMDGPU_IH_H__
26 
27 /* Maximum number of IVs processed at once */
28 #define AMDGPU_IH_MAX_NUM_IVS	32
29 
30 struct amdgpu_device;
31 struct amdgpu_iv_entry;
32 
33 struct amdgpu_ih_regs {
34 	uint32_t ih_rb_base;
35 	uint32_t ih_rb_base_hi;
36 	uint32_t ih_rb_cntl;
37 	uint32_t ih_rb_wptr;
38 	uint32_t ih_rb_rptr;
39 	uint32_t ih_doorbell_rptr;
40 	uint32_t ih_rb_wptr_addr_lo;
41 	uint32_t ih_rb_wptr_addr_hi;
42 	uint32_t psp_reg_id;
43 };
44 
45 /*
46  * R6xx+ IH ring
47  */
48 struct amdgpu_ih_ring {
49 	unsigned		ring_size;
50 	uint32_t		ptr_mask;
51 	u32			doorbell_index;
52 	bool			use_doorbell;
53 	bool			use_bus_addr;
54 
55 	struct amdgpu_bo	*ring_obj;
56 	volatile uint32_t	*ring;
57 	uint64_t		gpu_addr;
58 
59 	uint64_t		wptr_addr;
60 	volatile uint32_t	*wptr_cpu;
61 
62 	uint64_t		rptr_addr;
63 	volatile uint32_t	*rptr_cpu;
64 
65 	bool                    enabled;
66 	unsigned		rptr;
67 	atomic_t		lock;
68 	struct amdgpu_ih_regs	ih_regs;
69 };
70 
71 /* provided by the ih block */
72 struct amdgpu_ih_funcs {
73 	/* ring read/write ptr handling, called from interrupt context */
74 	u32 (*get_wptr)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
75 	void (*decode_iv)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
76 			  struct amdgpu_iv_entry *entry);
77 	void (*set_rptr)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
78 };
79 
80 #define amdgpu_ih_get_wptr(adev, ih) (adev)->irq.ih_funcs->get_wptr((adev), (ih))
81 #define amdgpu_ih_decode_iv(adev, iv) \
82 	(adev)->irq.ih_funcs->decode_iv((adev), (ih), (iv))
83 #define amdgpu_ih_set_rptr(adev, ih) (adev)->irq.ih_funcs->set_rptr((adev), (ih))
84 
85 int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
86 			unsigned ring_size, bool use_bus_addr);
87 void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
88 void amdgpu_ih_ring_write(struct amdgpu_ih_ring *ih, const uint32_t *iv,
89 			  unsigned int num_dw);
90 int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
91 void amdgpu_ih_decode_iv_helper(struct amdgpu_device *adev,
92 				struct amdgpu_ih_ring *ih,
93 				struct amdgpu_iv_entry *entry);
94 #endif
95