1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_IH_H__ 25 #define __AMDGPU_IH_H__ 26 27 /* Maximum number of IVs processed at once */ 28 #define AMDGPU_IH_MAX_NUM_IVS 32 29 30 #define IH_RING_SIZE (256 * 1024) 31 #define IH_SW_RING_SIZE (16 * 1024) /* enough for 512 CAM entries */ 32 #define IH_PSP_RING_SIZE (SZ_4K) 33 #define IH_UALINK_RING_SIZE (256 * 1024) 34 35 struct amdgpu_device; 36 struct amdgpu_iv_entry; 37 38 struct amdgpu_ih_regs { 39 uint32_t ih_rb_base; 40 uint32_t ih_rb_base_hi; 41 uint32_t ih_rb_cntl; 42 uint32_t ih_rb_wptr; 43 uint32_t ih_rb_rptr; 44 uint32_t ih_doorbell_rptr; 45 uint32_t ih_rb_wptr_addr_lo; 46 uint32_t ih_rb_wptr_addr_hi; 47 uint32_t psp_reg_id; 48 }; 49 50 /* 51 * R6xx+ IH ring 52 */ 53 struct amdgpu_ih_ring { 54 unsigned ring_size; 55 uint32_t ptr_mask; 56 u32 doorbell_index; 57 bool use_doorbell; 58 bool use_bus_addr; 59 60 struct amdgpu_bo *ring_obj; 61 uint32_t *ring; 62 uint64_t gpu_addr; 63 64 uint64_t wptr_addr; 65 uint32_t *wptr_cpu; 66 67 uint64_t rptr_addr; 68 uint32_t *rptr_cpu; 69 70 bool enabled; 71 unsigned rptr; 72 struct amdgpu_ih_regs ih_regs; 73 74 /* For waiting on IH processing at checkpoint. */ 75 wait_queue_head_t wait_process; 76 uint64_t processed_timestamp; 77 bool overflow; 78 }; 79 80 /* return true if time stamp t2 is after t1 with 48bit wrap around */ 81 #define amdgpu_ih_ts_after(t1, t2) \ 82 (((int64_t)((t2) << 16) - (int64_t)((t1) << 16)) > 0LL) 83 84 #define amdgpu_ih_ts_after_or_equal(t1, t2) \ 85 (((int64_t)((t2) << 16) - (int64_t)((t1) << 16)) >= 0LL) 86 87 /* provided by the ih block */ 88 struct amdgpu_ih_funcs { 89 /* ring read/write ptr handling, called from interrupt context */ 90 u32 (*get_wptr)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih); 91 void (*decode_iv)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, 92 struct amdgpu_iv_entry *entry); 93 uint64_t (*decode_iv_ts)(struct amdgpu_ih_ring *ih, u32 rptr, 94 signed int offset); 95 void (*set_rptr)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih); 96 /* Decode IH cookie node_id into a human-readable die name string. 97 * Returns buf, or NULL if this IH version does not support node_id decoding. 98 */ 99 const char *(*node_id_to_die_name)(struct amdgpu_device *adev, 100 unsigned int node_id, 101 char *buf, size_t size); 102 }; 103 104 #define amdgpu_ih_get_wptr(adev, ih) (adev)->irq.ih_funcs->get_wptr((adev), (ih)) 105 #define amdgpu_ih_decode_iv(adev, iv) \ 106 (adev)->irq.ih_funcs->decode_iv((adev), (ih), (iv)) 107 #define amdgpu_ih_decode_iv_ts(adev, ih, rptr, offset) \ 108 (WARN_ON_ONCE(!(adev)->irq.ih_funcs->decode_iv_ts) ? 0 : \ 109 (adev)->irq.ih_funcs->decode_iv_ts((ih), (rptr), (offset))) 110 #define amdgpu_ih_set_rptr(adev, ih) (adev)->irq.ih_funcs->set_rptr((adev), (ih)) 111 112 int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, 113 unsigned ring_size, bool use_bus_addr); 114 void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih); 115 void amdgpu_ih_ring_write(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, 116 const uint32_t *iv, unsigned int num_dw); 117 int amdgpu_ih_wait_on_checkpoint_process_ts(struct amdgpu_device *adev, 118 struct amdgpu_ih_ring *ih); 119 int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih); 120 void amdgpu_ih_decode_iv_helper(struct amdgpu_device *adev, 121 struct amdgpu_ih_ring *ih, 122 struct amdgpu_iv_entry *entry); 123 uint64_t amdgpu_ih_decode_iv_ts_helper(struct amdgpu_ih_ring *ih, u32 rptr, 124 signed int offset); 125 const char *amdgpu_ih_ring_name(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih); 126 #endif 127