1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_IH_H__ 25 #define __AMDGPU_IH_H__ 26 27 /* Maximum number of IVs processed at once */ 28 #define AMDGPU_IH_MAX_NUM_IVS 32 29 30 struct amdgpu_device; 31 struct amdgpu_iv_entry; 32 33 struct amdgpu_ih_regs { 34 uint32_t ih_rb_base; 35 uint32_t ih_rb_base_hi; 36 uint32_t ih_rb_cntl; 37 uint32_t ih_rb_wptr; 38 uint32_t ih_rb_rptr; 39 uint32_t ih_doorbell_rptr; 40 uint32_t ih_rb_wptr_addr_lo; 41 uint32_t ih_rb_wptr_addr_hi; 42 uint32_t psp_reg_id; 43 }; 44 45 /* 46 * R6xx+ IH ring 47 */ 48 struct amdgpu_ih_ring { 49 unsigned ring_size; 50 uint32_t ptr_mask; 51 u32 doorbell_index; 52 bool use_doorbell; 53 bool use_bus_addr; 54 55 struct amdgpu_bo *ring_obj; 56 volatile uint32_t *ring; 57 uint64_t gpu_addr; 58 59 uint64_t wptr_addr; 60 volatile uint32_t *wptr_cpu; 61 62 uint64_t rptr_addr; 63 volatile uint32_t *rptr_cpu; 64 65 bool enabled; 66 unsigned rptr; 67 struct amdgpu_ih_regs ih_regs; 68 69 /* For waiting on IH processing at checkpoint. */ 70 wait_queue_head_t wait_process; 71 }; 72 73 /* provided by the ih block */ 74 struct amdgpu_ih_funcs { 75 /* ring read/write ptr handling, called from interrupt context */ 76 u32 (*get_wptr)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih); 77 void (*decode_iv)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, 78 struct amdgpu_iv_entry *entry); 79 void (*set_rptr)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih); 80 }; 81 82 #define amdgpu_ih_get_wptr(adev, ih) (adev)->irq.ih_funcs->get_wptr((adev), (ih)) 83 #define amdgpu_ih_decode_iv(adev, iv) \ 84 (adev)->irq.ih_funcs->decode_iv((adev), (ih), (iv)) 85 #define amdgpu_ih_set_rptr(adev, ih) (adev)->irq.ih_funcs->set_rptr((adev), (ih)) 86 87 int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, 88 unsigned ring_size, bool use_bus_addr); 89 void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih); 90 void amdgpu_ih_ring_write(struct amdgpu_ih_ring *ih, const uint32_t *iv, 91 unsigned int num_dw); 92 int amdgpu_ih_wait_on_checkpoint_process(struct amdgpu_device *adev, 93 struct amdgpu_ih_ring *ih); 94 int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih); 95 void amdgpu_ih_decode_iv_helper(struct amdgpu_device *adev, 96 struct amdgpu_ih_ring *ih, 97 struct amdgpu_iv_entry *entry); 98 #endif 99