1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef __AMDGPU_IDS_H__ 24 #define __AMDGPU_IDS_H__ 25 26 #include <linux/types.h> 27 #include <linux/mutex.h> 28 #include <linux/list.h> 29 #include <linux/dma-fence.h> 30 31 #include "amdgpu_sync.h" 32 33 /* maximum number of VMIDs */ 34 #define AMDGPU_NUM_VMID 16 35 36 struct amdgpu_device; 37 struct amdgpu_vm; 38 struct amdgpu_ring; 39 struct amdgpu_sync; 40 struct amdgpu_job; 41 42 struct amdgpu_vmid { 43 struct list_head list; 44 struct amdgpu_sync active; 45 struct dma_fence *last_flush; 46 uint64_t owner; 47 48 uint64_t pd_gpu_addr; 49 /* last flushed PD/PT update */ 50 struct dma_fence *flushed_updates; 51 52 uint32_t current_gpu_reset_count; 53 54 uint32_t gds_base; 55 uint32_t gds_size; 56 uint32_t gws_base; 57 uint32_t gws_size; 58 uint32_t oa_base; 59 uint32_t oa_size; 60 61 unsigned pasid; 62 struct dma_fence *pasid_mapping; 63 }; 64 65 struct amdgpu_vmid_mgr { 66 struct mutex lock; 67 unsigned num_ids; 68 struct list_head ids_lru; 69 struct amdgpu_vmid ids[AMDGPU_NUM_VMID]; 70 atomic_t reserved_vmid_num; 71 }; 72 73 int amdgpu_pasid_alloc(unsigned int bits); 74 void amdgpu_pasid_free(u32 pasid); 75 void amdgpu_pasid_free_delayed(struct dma_resv *resv, 76 u32 pasid); 77 78 bool amdgpu_vmid_had_gpu_reset(struct amdgpu_device *adev, 79 struct amdgpu_vmid *id); 80 int amdgpu_vmid_alloc_reserved(struct amdgpu_device *adev, 81 struct amdgpu_vm *vm, 82 unsigned vmhub); 83 void amdgpu_vmid_free_reserved(struct amdgpu_device *adev, 84 struct amdgpu_vm *vm, 85 unsigned vmhub); 86 int amdgpu_vmid_grab(struct amdgpu_vm *vm, struct amdgpu_ring *ring, 87 struct amdgpu_sync *sync, struct dma_fence *fence, 88 struct amdgpu_job *job); 89 void amdgpu_vmid_reset(struct amdgpu_device *adev, unsigned vmhub, 90 unsigned vmid); 91 void amdgpu_vmid_reset_all(struct amdgpu_device *adev); 92 93 void amdgpu_vmid_mgr_init(struct amdgpu_device *adev); 94 void amdgpu_vmid_mgr_fini(struct amdgpu_device *adev); 95 96 #endif 97