1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 * Christian König 28 */ 29 #include <linux/seq_file.h> 30 #include <linux/slab.h> 31 #include <drm/drmP.h> 32 #include <drm/amdgpu_drm.h> 33 #include "amdgpu.h" 34 #include "atom.h" 35 36 #define AMDGPU_IB_TEST_TIMEOUT msecs_to_jiffies(1000) 37 38 /* 39 * IB 40 * IBs (Indirect Buffers) and areas of GPU accessible memory where 41 * commands are stored. You can put a pointer to the IB in the 42 * command ring and the hw will fetch the commands from the IB 43 * and execute them. Generally userspace acceleration drivers 44 * produce command buffers which are send to the kernel and 45 * put in IBs for execution by the requested ring. 46 */ 47 static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev); 48 49 /** 50 * amdgpu_ib_get - request an IB (Indirect Buffer) 51 * 52 * @ring: ring index the IB is associated with 53 * @size: requested IB size 54 * @ib: IB object returned 55 * 56 * Request an IB (all asics). IBs are allocated using the 57 * suballocator. 58 * Returns 0 on success, error on failure. 59 */ 60 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 61 unsigned size, struct amdgpu_ib *ib) 62 { 63 int r; 64 65 if (size) { 66 r = amdgpu_sa_bo_new(&adev->ring_tmp_bo, 67 &ib->sa_bo, size, 256); 68 if (r) { 69 dev_err(adev->dev, "failed to get a new IB (%d)\n", r); 70 return r; 71 } 72 73 ib->ptr = amdgpu_sa_bo_cpu_addr(ib->sa_bo); 74 75 if (!vm) 76 ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo); 77 } 78 79 return 0; 80 } 81 82 /** 83 * amdgpu_ib_free - free an IB (Indirect Buffer) 84 * 85 * @adev: amdgpu_device pointer 86 * @ib: IB object to free 87 * @f: the fence SA bo need wait on for the ib alloation 88 * 89 * Free an IB (all asics). 90 */ 91 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 92 struct dma_fence *f) 93 { 94 amdgpu_sa_bo_free(adev, &ib->sa_bo, f); 95 } 96 97 /** 98 * amdgpu_ib_schedule - schedule an IB (Indirect Buffer) on the ring 99 * 100 * @adev: amdgpu_device pointer 101 * @num_ibs: number of IBs to schedule 102 * @ibs: IB objects to schedule 103 * @f: fence created during this submission 104 * 105 * Schedule an IB on the associated ring (all asics). 106 * Returns 0 on success, error on failure. 107 * 108 * On SI, there are two parallel engines fed from the primary ring, 109 * the CE (Constant Engine) and the DE (Drawing Engine). Since 110 * resource descriptors have moved to memory, the CE allows you to 111 * prime the caches while the DE is updating register state so that 112 * the resource descriptors will be already in cache when the draw is 113 * processed. To accomplish this, the userspace driver submits two 114 * IBs, one for the CE and one for the DE. If there is a CE IB (called 115 * a CONST_IB), it will be put on the ring prior to the DE IB. Prior 116 * to SI there was just a DE IB. 117 */ 118 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 119 struct amdgpu_ib *ibs, struct amdgpu_job *job, 120 struct dma_fence **f) 121 { 122 struct amdgpu_device *adev = ring->adev; 123 struct amdgpu_ib *ib = &ibs[0]; 124 bool skip_preamble, need_ctx_switch; 125 unsigned patch_offset = ~0; 126 struct amdgpu_vm *vm; 127 uint64_t fence_ctx; 128 uint32_t status = 0, alloc_size; 129 130 unsigned i; 131 int r = 0; 132 133 if (num_ibs == 0) 134 return -EINVAL; 135 136 /* ring tests don't use a job */ 137 if (job) { 138 vm = job->vm; 139 fence_ctx = job->fence_ctx; 140 } else { 141 vm = NULL; 142 fence_ctx = 0; 143 } 144 145 if (!ring->ready) { 146 dev_err(adev->dev, "couldn't schedule ib on ring <%s>\n", ring->name); 147 return -EINVAL; 148 } 149 150 if (vm && !job->vm_id) { 151 dev_err(adev->dev, "VM IB without ID\n"); 152 return -EINVAL; 153 } 154 155 alloc_size = ring->funcs->emit_frame_size + num_ibs * 156 ring->funcs->emit_ib_size; 157 158 r = amdgpu_ring_alloc(ring, alloc_size); 159 if (r) { 160 dev_err(adev->dev, "scheduling IB failed (%d).\n", r); 161 return r; 162 } 163 if (ring->funcs->emit_pipeline_sync && job && job->need_pipeline_sync) 164 amdgpu_ring_emit_pipeline_sync(ring); 165 166 if (vm) { 167 r = amdgpu_vm_flush(ring, job); 168 if (r) { 169 amdgpu_ring_undo(ring); 170 return r; 171 } 172 } 173 174 if (ring->funcs->init_cond_exec) 175 patch_offset = amdgpu_ring_init_cond_exec(ring); 176 177 if (ring->funcs->emit_hdp_flush 178 #ifdef CONFIG_X86_64 179 && !(adev->flags & AMD_IS_APU) 180 #endif 181 ) 182 amdgpu_ring_emit_hdp_flush(ring); 183 184 skip_preamble = ring->current_ctx == fence_ctx; 185 need_ctx_switch = ring->current_ctx != fence_ctx; 186 if (job && ring->funcs->emit_cntxcntl) { 187 if (need_ctx_switch) 188 status |= AMDGPU_HAVE_CTX_SWITCH; 189 status |= job->preamble_status; 190 191 if (vm) 192 status |= AMDGPU_VM_DOMAIN; 193 amdgpu_ring_emit_cntxcntl(ring, status); 194 } 195 196 for (i = 0; i < num_ibs; ++i) { 197 ib = &ibs[i]; 198 199 /* drop preamble IBs if we don't have a context switch */ 200 if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && 201 skip_preamble && 202 !(status & AMDGPU_PREAMBLE_IB_PRESENT_FIRST) && 203 !amdgpu_sriov_vf(adev)) /* for SRIOV preemption, Preamble CE ib must be inserted anyway */ 204 continue; 205 206 amdgpu_ring_emit_ib(ring, ib, job ? job->vm_id : 0, 207 need_ctx_switch); 208 need_ctx_switch = false; 209 } 210 211 if (ring->funcs->emit_hdp_invalidate 212 #ifdef CONFIG_X86_64 213 && !(adev->flags & AMD_IS_APU) 214 #endif 215 ) 216 amdgpu_ring_emit_hdp_invalidate(ring); 217 218 r = amdgpu_fence_emit(ring, f); 219 if (r) { 220 dev_err(adev->dev, "failed to emit fence (%d)\n", r); 221 if (job && job->vm_id) 222 amdgpu_vm_reset_id(adev, ring->funcs->vmhub, 223 job->vm_id); 224 amdgpu_ring_undo(ring); 225 return r; 226 } 227 228 if (ring->funcs->insert_end) 229 ring->funcs->insert_end(ring); 230 231 /* wrap the last IB with fence */ 232 if (job && job->uf_addr) { 233 amdgpu_ring_emit_fence(ring, job->uf_addr, job->uf_sequence, 234 AMDGPU_FENCE_FLAG_64BIT); 235 } 236 237 if (patch_offset != ~0 && ring->funcs->patch_cond_exec) 238 amdgpu_ring_patch_cond_exec(ring, patch_offset); 239 240 ring->current_ctx = fence_ctx; 241 if (vm && ring->funcs->emit_switch_buffer) 242 amdgpu_ring_emit_switch_buffer(ring); 243 amdgpu_ring_commit(ring); 244 return 0; 245 } 246 247 /** 248 * amdgpu_ib_pool_init - Init the IB (Indirect Buffer) pool 249 * 250 * @adev: amdgpu_device pointer 251 * 252 * Initialize the suballocator to manage a pool of memory 253 * for use as IBs (all asics). 254 * Returns 0 on success, error on failure. 255 */ 256 int amdgpu_ib_pool_init(struct amdgpu_device *adev) 257 { 258 int r; 259 260 if (adev->ib_pool_ready) { 261 return 0; 262 } 263 r = amdgpu_sa_bo_manager_init(adev, &adev->ring_tmp_bo, 264 AMDGPU_IB_POOL_SIZE*64*1024, 265 AMDGPU_GPU_PAGE_SIZE, 266 AMDGPU_GEM_DOMAIN_GTT); 267 if (r) { 268 return r; 269 } 270 271 r = amdgpu_sa_bo_manager_start(adev, &adev->ring_tmp_bo); 272 if (r) { 273 return r; 274 } 275 276 adev->ib_pool_ready = true; 277 if (amdgpu_debugfs_sa_init(adev)) { 278 dev_err(adev->dev, "failed to register debugfs file for SA\n"); 279 } 280 return 0; 281 } 282 283 /** 284 * amdgpu_ib_pool_fini - Free the IB (Indirect Buffer) pool 285 * 286 * @adev: amdgpu_device pointer 287 * 288 * Tear down the suballocator managing the pool of memory 289 * for use as IBs (all asics). 290 */ 291 void amdgpu_ib_pool_fini(struct amdgpu_device *adev) 292 { 293 if (adev->ib_pool_ready) { 294 amdgpu_sa_bo_manager_suspend(adev, &adev->ring_tmp_bo); 295 amdgpu_sa_bo_manager_fini(adev, &adev->ring_tmp_bo); 296 adev->ib_pool_ready = false; 297 } 298 } 299 300 /** 301 * amdgpu_ib_ring_tests - test IBs on the rings 302 * 303 * @adev: amdgpu_device pointer 304 * 305 * Test an IB (Indirect Buffer) on each ring. 306 * If the test fails, disable the ring. 307 * Returns 0 on success, error if the primary GFX ring 308 * IB test fails. 309 */ 310 int amdgpu_ib_ring_tests(struct amdgpu_device *adev) 311 { 312 unsigned i; 313 int r, ret = 0; 314 315 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { 316 struct amdgpu_ring *ring = adev->rings[i]; 317 318 if (!ring || !ring->ready) 319 continue; 320 321 r = amdgpu_ring_test_ib(ring, AMDGPU_IB_TEST_TIMEOUT); 322 if (r) { 323 ring->ready = false; 324 325 if (ring == &adev->gfx.gfx_ring[0]) { 326 /* oh, oh, that's really bad */ 327 DRM_ERROR("amdgpu: failed testing IB on GFX ring (%d).\n", r); 328 adev->accel_working = false; 329 return r; 330 331 } else { 332 /* still not good, but we can live with it */ 333 DRM_ERROR("amdgpu: failed testing IB on ring %d (%d).\n", i, r); 334 ret = r; 335 } 336 } 337 } 338 return ret; 339 } 340 341 /* 342 * Debugfs info 343 */ 344 #if defined(CONFIG_DEBUG_FS) 345 346 static int amdgpu_debugfs_sa_info(struct seq_file *m, void *data) 347 { 348 struct drm_info_node *node = (struct drm_info_node *) m->private; 349 struct drm_device *dev = node->minor->dev; 350 struct amdgpu_device *adev = dev->dev_private; 351 352 amdgpu_sa_bo_dump_debug_info(&adev->ring_tmp_bo, m); 353 354 return 0; 355 356 } 357 358 static const struct drm_info_list amdgpu_debugfs_sa_list[] = { 359 {"amdgpu_sa_info", &amdgpu_debugfs_sa_info, 0, NULL}, 360 }; 361 362 #endif 363 364 static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev) 365 { 366 #if defined(CONFIG_DEBUG_FS) 367 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_sa_list, 1); 368 #else 369 return 0; 370 #endif 371 } 372