1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 * Christian König 28 */ 29 #include <linux/seq_file.h> 30 #include <linux/slab.h> 31 #include <drm/drmP.h> 32 #include <drm/amdgpu_drm.h> 33 #include "amdgpu.h" 34 #include "atom.h" 35 #include "amdgpu_trace.h" 36 37 #define AMDGPU_IB_TEST_TIMEOUT msecs_to_jiffies(1000) 38 #define AMDGPU_IB_TEST_GFX_XGMI_TIMEOUT msecs_to_jiffies(2000) 39 40 /* 41 * IB 42 * IBs (Indirect Buffers) and areas of GPU accessible memory where 43 * commands are stored. You can put a pointer to the IB in the 44 * command ring and the hw will fetch the commands from the IB 45 * and execute them. Generally userspace acceleration drivers 46 * produce command buffers which are send to the kernel and 47 * put in IBs for execution by the requested ring. 48 */ 49 static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev); 50 51 /** 52 * amdgpu_ib_get - request an IB (Indirect Buffer) 53 * 54 * @ring: ring index the IB is associated with 55 * @size: requested IB size 56 * @ib: IB object returned 57 * 58 * Request an IB (all asics). IBs are allocated using the 59 * suballocator. 60 * Returns 0 on success, error on failure. 61 */ 62 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 63 unsigned size, struct amdgpu_ib *ib) 64 { 65 int r; 66 67 if (size) { 68 r = amdgpu_sa_bo_new(&adev->ring_tmp_bo, 69 &ib->sa_bo, size, 256); 70 if (r) { 71 dev_err(adev->dev, "failed to get a new IB (%d)\n", r); 72 return r; 73 } 74 75 ib->ptr = amdgpu_sa_bo_cpu_addr(ib->sa_bo); 76 77 if (!vm) 78 ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo); 79 } 80 81 return 0; 82 } 83 84 /** 85 * amdgpu_ib_free - free an IB (Indirect Buffer) 86 * 87 * @adev: amdgpu_device pointer 88 * @ib: IB object to free 89 * @f: the fence SA bo need wait on for the ib alloation 90 * 91 * Free an IB (all asics). 92 */ 93 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 94 struct dma_fence *f) 95 { 96 amdgpu_sa_bo_free(adev, &ib->sa_bo, f); 97 } 98 99 /** 100 * amdgpu_ib_schedule - schedule an IB (Indirect Buffer) on the ring 101 * 102 * @adev: amdgpu_device pointer 103 * @num_ibs: number of IBs to schedule 104 * @ibs: IB objects to schedule 105 * @f: fence created during this submission 106 * 107 * Schedule an IB on the associated ring (all asics). 108 * Returns 0 on success, error on failure. 109 * 110 * On SI, there are two parallel engines fed from the primary ring, 111 * the CE (Constant Engine) and the DE (Drawing Engine). Since 112 * resource descriptors have moved to memory, the CE allows you to 113 * prime the caches while the DE is updating register state so that 114 * the resource descriptors will be already in cache when the draw is 115 * processed. To accomplish this, the userspace driver submits two 116 * IBs, one for the CE and one for the DE. If there is a CE IB (called 117 * a CONST_IB), it will be put on the ring prior to the DE IB. Prior 118 * to SI there was just a DE IB. 119 */ 120 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 121 struct amdgpu_ib *ibs, struct amdgpu_job *job, 122 struct dma_fence **f) 123 { 124 struct amdgpu_device *adev = ring->adev; 125 struct amdgpu_ib *ib = &ibs[0]; 126 struct dma_fence *tmp = NULL; 127 bool skip_preamble, need_ctx_switch; 128 unsigned patch_offset = ~0; 129 struct amdgpu_vm *vm; 130 uint64_t fence_ctx; 131 uint32_t status = 0, alloc_size; 132 unsigned fence_flags = 0; 133 134 unsigned i; 135 int r = 0; 136 bool need_pipe_sync = false; 137 138 if (num_ibs == 0) 139 return -EINVAL; 140 141 /* ring tests don't use a job */ 142 if (job) { 143 vm = job->vm; 144 fence_ctx = job->base.s_fence->scheduled.context; 145 } else { 146 vm = NULL; 147 fence_ctx = 0; 148 } 149 150 if (!ring->sched.ready) { 151 dev_err(adev->dev, "couldn't schedule ib on ring <%s>\n", ring->name); 152 return -EINVAL; 153 } 154 155 if (vm && !job->vmid) { 156 dev_err(adev->dev, "VM IB without ID\n"); 157 return -EINVAL; 158 } 159 160 alloc_size = ring->funcs->emit_frame_size + num_ibs * 161 ring->funcs->emit_ib_size; 162 163 r = amdgpu_ring_alloc(ring, alloc_size); 164 if (r) { 165 dev_err(adev->dev, "scheduling IB failed (%d).\n", r); 166 return r; 167 } 168 169 need_ctx_switch = ring->current_ctx != fence_ctx; 170 if (ring->funcs->emit_pipeline_sync && job && 171 ((tmp = amdgpu_sync_get_fence(&job->sched_sync, NULL)) || 172 (amdgpu_sriov_vf(adev) && need_ctx_switch) || 173 amdgpu_vm_need_pipeline_sync(ring, job))) { 174 need_pipe_sync = true; 175 176 if (tmp) 177 trace_amdgpu_ib_pipe_sync(job, tmp); 178 179 dma_fence_put(tmp); 180 } 181 182 if (ring->funcs->insert_start) 183 ring->funcs->insert_start(ring); 184 185 if (job) { 186 r = amdgpu_vm_flush(ring, job, need_pipe_sync); 187 if (r) { 188 amdgpu_ring_undo(ring); 189 return r; 190 } 191 } 192 193 if (job && ring->funcs->init_cond_exec) 194 patch_offset = amdgpu_ring_init_cond_exec(ring); 195 196 #ifdef CONFIG_X86_64 197 if (!(adev->flags & AMD_IS_APU)) 198 #endif 199 { 200 if (ring->funcs->emit_hdp_flush) 201 amdgpu_ring_emit_hdp_flush(ring); 202 else 203 amdgpu_asic_flush_hdp(adev, ring); 204 } 205 206 if (need_ctx_switch) 207 status |= AMDGPU_HAVE_CTX_SWITCH; 208 209 skip_preamble = ring->current_ctx == fence_ctx; 210 if (job && ring->funcs->emit_cntxcntl) { 211 status |= job->preamble_status; 212 amdgpu_ring_emit_cntxcntl(ring, status); 213 } 214 215 for (i = 0; i < num_ibs; ++i) { 216 ib = &ibs[i]; 217 218 /* drop preamble IBs if we don't have a context switch */ 219 if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && 220 skip_preamble && 221 !(status & AMDGPU_PREAMBLE_IB_PRESENT_FIRST) && 222 !amdgpu_sriov_vf(adev)) /* for SRIOV preemption, Preamble CE ib must be inserted anyway */ 223 continue; 224 225 amdgpu_ring_emit_ib(ring, job, ib, status); 226 status &= ~AMDGPU_HAVE_CTX_SWITCH; 227 } 228 229 if (ring->funcs->emit_tmz) 230 amdgpu_ring_emit_tmz(ring, false); 231 232 #ifdef CONFIG_X86_64 233 if (!(adev->flags & AMD_IS_APU)) 234 #endif 235 amdgpu_asic_invalidate_hdp(adev, ring); 236 237 if (ib->flags & AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE) 238 fence_flags |= AMDGPU_FENCE_FLAG_TC_WB_ONLY; 239 240 /* wrap the last IB with fence */ 241 if (job && job->uf_addr) { 242 amdgpu_ring_emit_fence(ring, job->uf_addr, job->uf_sequence, 243 fence_flags | AMDGPU_FENCE_FLAG_64BIT); 244 } 245 246 r = amdgpu_fence_emit(ring, f, fence_flags); 247 if (r) { 248 dev_err(adev->dev, "failed to emit fence (%d)\n", r); 249 if (job && job->vmid) 250 amdgpu_vmid_reset(adev, ring->funcs->vmhub, job->vmid); 251 amdgpu_ring_undo(ring); 252 return r; 253 } 254 255 if (ring->funcs->insert_end) 256 ring->funcs->insert_end(ring); 257 258 if (patch_offset != ~0 && ring->funcs->patch_cond_exec) 259 amdgpu_ring_patch_cond_exec(ring, patch_offset); 260 261 ring->current_ctx = fence_ctx; 262 if (vm && ring->funcs->emit_switch_buffer) 263 amdgpu_ring_emit_switch_buffer(ring); 264 amdgpu_ring_commit(ring); 265 return 0; 266 } 267 268 /** 269 * amdgpu_ib_pool_init - Init the IB (Indirect Buffer) pool 270 * 271 * @adev: amdgpu_device pointer 272 * 273 * Initialize the suballocator to manage a pool of memory 274 * for use as IBs (all asics). 275 * Returns 0 on success, error on failure. 276 */ 277 int amdgpu_ib_pool_init(struct amdgpu_device *adev) 278 { 279 int r; 280 281 if (adev->ib_pool_ready) { 282 return 0; 283 } 284 r = amdgpu_sa_bo_manager_init(adev, &adev->ring_tmp_bo, 285 AMDGPU_IB_POOL_SIZE*64*1024, 286 AMDGPU_GPU_PAGE_SIZE, 287 AMDGPU_GEM_DOMAIN_GTT); 288 if (r) { 289 return r; 290 } 291 292 adev->ib_pool_ready = true; 293 if (amdgpu_debugfs_sa_init(adev)) { 294 dev_err(adev->dev, "failed to register debugfs file for SA\n"); 295 } 296 return 0; 297 } 298 299 /** 300 * amdgpu_ib_pool_fini - Free the IB (Indirect Buffer) pool 301 * 302 * @adev: amdgpu_device pointer 303 * 304 * Tear down the suballocator managing the pool of memory 305 * for use as IBs (all asics). 306 */ 307 void amdgpu_ib_pool_fini(struct amdgpu_device *adev) 308 { 309 if (adev->ib_pool_ready) { 310 amdgpu_sa_bo_manager_fini(adev, &adev->ring_tmp_bo); 311 adev->ib_pool_ready = false; 312 } 313 } 314 315 /** 316 * amdgpu_ib_ring_tests - test IBs on the rings 317 * 318 * @adev: amdgpu_device pointer 319 * 320 * Test an IB (Indirect Buffer) on each ring. 321 * If the test fails, disable the ring. 322 * Returns 0 on success, error if the primary GFX ring 323 * IB test fails. 324 */ 325 int amdgpu_ib_ring_tests(struct amdgpu_device *adev) 326 { 327 unsigned i; 328 int r, ret = 0; 329 long tmo_gfx, tmo_mm; 330 331 tmo_mm = tmo_gfx = AMDGPU_IB_TEST_TIMEOUT; 332 if (amdgpu_sriov_vf(adev)) { 333 /* for MM engines in hypervisor side they are not scheduled together 334 * with CP and SDMA engines, so even in exclusive mode MM engine could 335 * still running on other VF thus the IB TEST TIMEOUT for MM engines 336 * under SR-IOV should be set to a long time. 8 sec should be enough 337 * for the MM comes back to this VF. 338 */ 339 tmo_mm = 8 * AMDGPU_IB_TEST_TIMEOUT; 340 } 341 342 if (amdgpu_sriov_runtime(adev)) { 343 /* for CP & SDMA engines since they are scheduled together so 344 * need to make the timeout width enough to cover the time 345 * cost waiting for it coming back under RUNTIME only 346 */ 347 tmo_gfx = 8 * AMDGPU_IB_TEST_TIMEOUT; 348 } else if (adev->gmc.xgmi.hive_id) { 349 tmo_gfx = AMDGPU_IB_TEST_GFX_XGMI_TIMEOUT; 350 } 351 352 for (i = 0; i < adev->num_rings; ++i) { 353 struct amdgpu_ring *ring = adev->rings[i]; 354 long tmo; 355 356 /* KIQ rings don't have an IB test because we never submit IBs 357 * to them and they have no interrupt support. 358 */ 359 if (!ring->sched.ready || !ring->funcs->test_ib) 360 continue; 361 362 /* MM engine need more time */ 363 if (ring->funcs->type == AMDGPU_RING_TYPE_UVD || 364 ring->funcs->type == AMDGPU_RING_TYPE_VCE || 365 ring->funcs->type == AMDGPU_RING_TYPE_UVD_ENC || 366 ring->funcs->type == AMDGPU_RING_TYPE_VCN_DEC || 367 ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC || 368 ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG) 369 tmo = tmo_mm; 370 else 371 tmo = tmo_gfx; 372 373 r = amdgpu_ring_test_ib(ring, tmo); 374 if (!r) { 375 DRM_DEV_DEBUG(adev->dev, "ib test on %s succeeded\n", 376 ring->name); 377 continue; 378 } 379 380 ring->sched.ready = false; 381 DRM_DEV_ERROR(adev->dev, "IB test failed on %s (%d).\n", 382 ring->name, r); 383 384 if (ring == &adev->gfx.gfx_ring[0]) { 385 /* oh, oh, that's really bad */ 386 adev->accel_working = false; 387 return r; 388 389 } else { 390 ret = r; 391 } 392 } 393 return ret; 394 } 395 396 /* 397 * Debugfs info 398 */ 399 #if defined(CONFIG_DEBUG_FS) 400 401 static int amdgpu_debugfs_sa_info(struct seq_file *m, void *data) 402 { 403 struct drm_info_node *node = (struct drm_info_node *) m->private; 404 struct drm_device *dev = node->minor->dev; 405 struct amdgpu_device *adev = dev->dev_private; 406 407 amdgpu_sa_bo_dump_debug_info(&adev->ring_tmp_bo, m); 408 409 return 0; 410 411 } 412 413 static const struct drm_info_list amdgpu_debugfs_sa_list[] = { 414 {"amdgpu_sa_info", &amdgpu_debugfs_sa_info, 0, NULL}, 415 }; 416 417 #endif 418 419 static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev) 420 { 421 #if defined(CONFIG_DEBUG_FS) 422 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_sa_list, 1); 423 #else 424 return 0; 425 #endif 426 } 427