1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 * Christian König 28 */ 29 #include <linux/seq_file.h> 30 #include <linux/slab.h> 31 32 #include <drm/amdgpu_drm.h> 33 34 #include "amdgpu.h" 35 #include "atom.h" 36 #include "amdgpu_trace.h" 37 38 #define AMDGPU_IB_TEST_TIMEOUT msecs_to_jiffies(1000) 39 #define AMDGPU_IB_TEST_GFX_XGMI_TIMEOUT msecs_to_jiffies(2000) 40 41 /* 42 * IB 43 * IBs (Indirect Buffers) and areas of GPU accessible memory where 44 * commands are stored. You can put a pointer to the IB in the 45 * command ring and the hw will fetch the commands from the IB 46 * and execute them. Generally userspace acceleration drivers 47 * produce command buffers which are send to the kernel and 48 * put in IBs for execution by the requested ring. 49 */ 50 51 /** 52 * amdgpu_ib_get - request an IB (Indirect Buffer) 53 * 54 * @adev: amdgpu_device pointer 55 * @vm: amdgpu_vm pointer 56 * @size: requested IB size 57 * @pool_type: IB pool type (delayed, immediate, direct) 58 * @ib: IB object returned 59 * 60 * Request an IB (all asics). IBs are allocated using the 61 * suballocator. 62 * Returns 0 on success, error on failure. 63 */ 64 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 65 unsigned int size, enum amdgpu_ib_pool_type pool_type, 66 struct amdgpu_ib *ib) 67 { 68 int r; 69 70 if (size) { 71 r = amdgpu_sa_bo_new(&adev->ib_pools[pool_type], 72 &ib->sa_bo, size); 73 if (r) { 74 dev_err(adev->dev, "failed to get a new IB (%d)\n", r); 75 return r; 76 } 77 78 ib->ptr = amdgpu_sa_bo_cpu_addr(ib->sa_bo); 79 /* flush the cache before commit the IB */ 80 ib->flags = AMDGPU_IB_FLAG_EMIT_MEM_SYNC; 81 82 if (!vm) 83 ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo); 84 } 85 86 return 0; 87 } 88 89 /** 90 * amdgpu_ib_free - free an IB (Indirect Buffer) 91 * 92 * @ib: IB object to free 93 * @f: the fence SA bo need wait on for the ib alloation 94 * 95 * Free an IB (all asics). 96 */ 97 void amdgpu_ib_free(struct amdgpu_ib *ib, struct dma_fence *f) 98 { 99 amdgpu_sa_bo_free(&ib->sa_bo, f); 100 } 101 102 /** 103 * amdgpu_ib_schedule - schedule an IB (Indirect Buffer) on the ring 104 * 105 * @ring: ring index the IB is associated with 106 * @num_ibs: number of IBs to schedule 107 * @ibs: IB objects to schedule 108 * @job: job to schedule 109 * @f: fence created during this submission 110 * 111 * Schedule an IB on the associated ring (all asics). 112 * Returns 0 on success, error on failure. 113 * 114 * On SI, there are two parallel engines fed from the primary ring, 115 * the CE (Constant Engine) and the DE (Drawing Engine). Since 116 * resource descriptors have moved to memory, the CE allows you to 117 * prime the caches while the DE is updating register state so that 118 * the resource descriptors will be already in cache when the draw is 119 * processed. To accomplish this, the userspace driver submits two 120 * IBs, one for the CE and one for the DE. If there is a CE IB (called 121 * a CONST_IB), it will be put on the ring prior to the DE IB. Prior 122 * to SI there was just a DE IB. 123 */ 124 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, 125 struct amdgpu_ib *ibs, struct amdgpu_job *job, 126 struct dma_fence **f) 127 { 128 struct amdgpu_device *adev = ring->adev; 129 struct amdgpu_ib *ib = &ibs[0]; 130 struct dma_fence *tmp = NULL; 131 struct amdgpu_fence *af; 132 bool need_ctx_switch; 133 struct amdgpu_vm *vm; 134 uint64_t fence_ctx; 135 uint32_t status = 0, alloc_size; 136 unsigned int fence_flags = 0; 137 bool secure, init_shadow; 138 u64 shadow_va, csa_va, gds_va; 139 int vmid = AMDGPU_JOB_GET_VMID(job); 140 bool need_pipe_sync = false; 141 unsigned int cond_exec; 142 unsigned int i; 143 int r = 0; 144 145 if (num_ibs == 0) 146 return -EINVAL; 147 148 /* ring tests don't use a job */ 149 if (job) { 150 vm = job->vm; 151 fence_ctx = job->base.s_fence ? 152 job->base.s_fence->scheduled.context : 0; 153 shadow_va = job->shadow_va; 154 csa_va = job->csa_va; 155 gds_va = job->gds_va; 156 init_shadow = job->init_shadow; 157 af = &job->hw_fence; 158 /* Save the context of the job for reset handling. 159 * The driver needs this so it can skip the ring 160 * contents for guilty contexts. 161 */ 162 af->context = job->base.s_fence ? job->base.s_fence->finished.context : 0; 163 } else { 164 vm = NULL; 165 fence_ctx = 0; 166 shadow_va = 0; 167 csa_va = 0; 168 gds_va = 0; 169 init_shadow = false; 170 af = NULL; 171 } 172 173 if (!ring->sched.ready) { 174 dev_err(adev->dev, "couldn't schedule ib on ring <%s>\n", ring->name); 175 return -EINVAL; 176 } 177 178 if (vm && !job->vmid) { 179 dev_err(adev->dev, "VM IB without ID\n"); 180 return -EINVAL; 181 } 182 183 if ((ib->flags & AMDGPU_IB_FLAGS_SECURE) && 184 (!ring->funcs->secure_submission_supported)) { 185 dev_err(adev->dev, "secure submissions not supported on ring <%s>\n", ring->name); 186 return -EINVAL; 187 } 188 189 alloc_size = ring->funcs->emit_frame_size + num_ibs * 190 ring->funcs->emit_ib_size; 191 192 r = amdgpu_ring_alloc(ring, alloc_size); 193 if (r) { 194 dev_err(adev->dev, "scheduling IB failed (%d).\n", r); 195 return r; 196 } 197 198 need_ctx_switch = ring->current_ctx != fence_ctx; 199 if (ring->funcs->emit_pipeline_sync && job && 200 ((tmp = amdgpu_sync_get_fence(&job->explicit_sync)) || 201 need_ctx_switch || amdgpu_vm_need_pipeline_sync(ring, job))) { 202 203 need_pipe_sync = true; 204 205 if (tmp) 206 trace_amdgpu_ib_pipe_sync(job, tmp); 207 208 dma_fence_put(tmp); 209 } 210 211 if ((ib->flags & AMDGPU_IB_FLAG_EMIT_MEM_SYNC) && ring->funcs->emit_mem_sync) 212 ring->funcs->emit_mem_sync(ring); 213 214 if (ring->funcs->emit_wave_limit && 215 ring->hw_prio == AMDGPU_GFX_PIPE_PRIO_HIGH) 216 ring->funcs->emit_wave_limit(ring, true); 217 218 if (ring->funcs->insert_start) 219 ring->funcs->insert_start(ring); 220 221 if (job) { 222 r = amdgpu_vm_flush(ring, job, need_pipe_sync); 223 if (r) { 224 amdgpu_ring_undo(ring); 225 return r; 226 } 227 } 228 229 amdgpu_ring_ib_begin(ring); 230 231 if (ring->funcs->emit_gfx_shadow) 232 amdgpu_ring_emit_gfx_shadow(ring, shadow_va, csa_va, gds_va, 233 init_shadow, vmid); 234 235 if (ring->funcs->init_cond_exec) 236 cond_exec = amdgpu_ring_init_cond_exec(ring, 237 ring->cond_exe_gpu_addr); 238 239 amdgpu_device_flush_hdp(adev, ring); 240 241 if (need_ctx_switch) 242 status |= AMDGPU_HAVE_CTX_SWITCH; 243 244 if (job && ring->funcs->emit_cntxcntl) { 245 status |= job->preamble_status; 246 status |= job->preemption_status; 247 amdgpu_ring_emit_cntxcntl(ring, status); 248 } 249 250 /* Setup initial TMZiness and send it off. 251 */ 252 secure = false; 253 if (job && ring->funcs->emit_frame_cntl) { 254 secure = ib->flags & AMDGPU_IB_FLAGS_SECURE; 255 amdgpu_ring_emit_frame_cntl(ring, true, secure); 256 } 257 258 for (i = 0; i < num_ibs; ++i) { 259 ib = &ibs[i]; 260 261 if (job && ring->funcs->emit_frame_cntl) { 262 if (secure != !!(ib->flags & AMDGPU_IB_FLAGS_SECURE)) { 263 amdgpu_ring_emit_frame_cntl(ring, false, secure); 264 secure = !secure; 265 amdgpu_ring_emit_frame_cntl(ring, true, secure); 266 } 267 } 268 269 amdgpu_ring_emit_ib(ring, job, ib, status); 270 status &= ~AMDGPU_HAVE_CTX_SWITCH; 271 } 272 273 if (job && ring->funcs->emit_frame_cntl) 274 amdgpu_ring_emit_frame_cntl(ring, false, secure); 275 276 amdgpu_device_invalidate_hdp(adev, ring); 277 278 if (ib->flags & AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE) 279 fence_flags |= AMDGPU_FENCE_FLAG_TC_WB_ONLY; 280 281 /* wrap the last IB with fence */ 282 if (job && job->uf_addr) { 283 amdgpu_ring_emit_fence(ring, job->uf_addr, job->uf_sequence, 284 fence_flags | AMDGPU_FENCE_FLAG_64BIT); 285 } 286 287 if (ring->funcs->emit_gfx_shadow && ring->funcs->init_cond_exec) { 288 amdgpu_ring_emit_gfx_shadow(ring, 0, 0, 0, false, 0); 289 amdgpu_ring_init_cond_exec(ring, ring->cond_exe_gpu_addr); 290 } 291 292 r = amdgpu_fence_emit(ring, f, af, fence_flags); 293 if (r) { 294 dev_err(adev->dev, "failed to emit fence (%d)\n", r); 295 if (job && job->vmid) 296 amdgpu_vmid_reset(adev, ring->vm_hub, job->vmid); 297 amdgpu_ring_undo(ring); 298 return r; 299 } 300 301 if (ring->funcs->insert_end) 302 ring->funcs->insert_end(ring); 303 304 amdgpu_ring_patch_cond_exec(ring, cond_exec); 305 306 ring->current_ctx = fence_ctx; 307 if (job && ring->funcs->emit_switch_buffer) 308 amdgpu_ring_emit_switch_buffer(ring); 309 310 if (ring->funcs->emit_wave_limit && 311 ring->hw_prio == AMDGPU_GFX_PIPE_PRIO_HIGH) 312 ring->funcs->emit_wave_limit(ring, false); 313 314 /* Save the wptr associated with this fence. 315 * This must be last for resets to work properly 316 * as we need to save the wptr associated with this 317 * fence so we know what rings contents to backup 318 * after we reset the queue. 319 */ 320 amdgpu_fence_save_wptr(*f); 321 322 amdgpu_ring_ib_end(ring); 323 amdgpu_ring_commit(ring); 324 325 return 0; 326 } 327 328 /** 329 * amdgpu_ib_pool_init - Init the IB (Indirect Buffer) pool 330 * 331 * @adev: amdgpu_device pointer 332 * 333 * Initialize the suballocator to manage a pool of memory 334 * for use as IBs (all asics). 335 * Returns 0 on success, error on failure. 336 */ 337 int amdgpu_ib_pool_init(struct amdgpu_device *adev) 338 { 339 int r, i; 340 341 if (adev->ib_pool_ready) 342 return 0; 343 344 for (i = 0; i < AMDGPU_IB_POOL_MAX; i++) { 345 r = amdgpu_sa_bo_manager_init(adev, &adev->ib_pools[i], 346 AMDGPU_IB_POOL_SIZE, 256, 347 AMDGPU_GEM_DOMAIN_GTT); 348 if (r) 349 goto error; 350 } 351 adev->ib_pool_ready = true; 352 353 return 0; 354 355 error: 356 while (i--) 357 amdgpu_sa_bo_manager_fini(adev, &adev->ib_pools[i]); 358 return r; 359 } 360 361 /** 362 * amdgpu_ib_pool_fini - Free the IB (Indirect Buffer) pool 363 * 364 * @adev: amdgpu_device pointer 365 * 366 * Tear down the suballocator managing the pool of memory 367 * for use as IBs (all asics). 368 */ 369 void amdgpu_ib_pool_fini(struct amdgpu_device *adev) 370 { 371 int i; 372 373 if (!adev->ib_pool_ready) 374 return; 375 376 for (i = 0; i < AMDGPU_IB_POOL_MAX; i++) 377 amdgpu_sa_bo_manager_fini(adev, &adev->ib_pools[i]); 378 adev->ib_pool_ready = false; 379 } 380 381 /** 382 * amdgpu_ib_ring_tests - test IBs on the rings 383 * 384 * @adev: amdgpu_device pointer 385 * 386 * Test an IB (Indirect Buffer) on each ring. 387 * If the test fails, disable the ring. 388 * Returns 0 on success, error if the primary GFX ring 389 * IB test fails. 390 */ 391 int amdgpu_ib_ring_tests(struct amdgpu_device *adev) 392 { 393 long tmo_gfx, tmo_mm; 394 int r, ret = 0; 395 unsigned int i; 396 397 tmo_mm = tmo_gfx = AMDGPU_IB_TEST_TIMEOUT; 398 if (amdgpu_sriov_vf(adev)) { 399 /* for MM engines in hypervisor side they are not scheduled together 400 * with CP and SDMA engines, so even in exclusive mode MM engine could 401 * still running on other VF thus the IB TEST TIMEOUT for MM engines 402 * under SR-IOV should be set to a long time. 8 sec should be enough 403 * for the MM comes back to this VF. 404 */ 405 tmo_mm = 8 * AMDGPU_IB_TEST_TIMEOUT; 406 } 407 408 if (amdgpu_sriov_runtime(adev)) { 409 /* for CP & SDMA engines since they are scheduled together so 410 * need to make the timeout width enough to cover the time 411 * cost waiting for it coming back under RUNTIME only 412 */ 413 tmo_gfx = 8 * AMDGPU_IB_TEST_TIMEOUT; 414 } else if (adev->gmc.xgmi.hive_id) { 415 tmo_gfx = AMDGPU_IB_TEST_GFX_XGMI_TIMEOUT; 416 } 417 418 for (i = 0; i < adev->num_rings; ++i) { 419 struct amdgpu_ring *ring = adev->rings[i]; 420 long tmo; 421 422 /* KIQ rings don't have an IB test because we never submit IBs 423 * to them and they have no interrupt support. 424 */ 425 if (!ring->sched.ready || !ring->funcs->test_ib) 426 continue; 427 428 if (adev->enable_mes && 429 ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 430 continue; 431 432 /* MM engine need more time */ 433 if (ring->funcs->type == AMDGPU_RING_TYPE_UVD || 434 ring->funcs->type == AMDGPU_RING_TYPE_VCE || 435 ring->funcs->type == AMDGPU_RING_TYPE_UVD_ENC || 436 ring->funcs->type == AMDGPU_RING_TYPE_VCN_DEC || 437 ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC || 438 ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG) 439 tmo = tmo_mm; 440 else 441 tmo = tmo_gfx; 442 443 r = amdgpu_ring_test_ib(ring, tmo); 444 if (!r) { 445 DRM_DEV_DEBUG(adev->dev, "ib test on %s succeeded\n", 446 ring->name); 447 continue; 448 } 449 450 ring->sched.ready = false; 451 DRM_DEV_ERROR(adev->dev, "IB test failed on %s (%d).\n", 452 ring->name, r); 453 454 if (ring == &adev->gfx.gfx_ring[0]) { 455 /* oh, oh, that's really bad */ 456 adev->accel_working = false; 457 return r; 458 459 } else { 460 ret = r; 461 } 462 } 463 return ret; 464 } 465 466 /* 467 * Debugfs info 468 */ 469 #if defined(CONFIG_DEBUG_FS) 470 471 static int amdgpu_debugfs_sa_info_show(struct seq_file *m, void *unused) 472 { 473 struct amdgpu_device *adev = m->private; 474 475 seq_puts(m, "--------------------- DELAYED ---------------------\n"); 476 amdgpu_sa_bo_dump_debug_info(&adev->ib_pools[AMDGPU_IB_POOL_DELAYED], 477 m); 478 seq_puts(m, "-------------------- IMMEDIATE --------------------\n"); 479 amdgpu_sa_bo_dump_debug_info(&adev->ib_pools[AMDGPU_IB_POOL_IMMEDIATE], 480 m); 481 seq_puts(m, "--------------------- DIRECT ----------------------\n"); 482 amdgpu_sa_bo_dump_debug_info(&adev->ib_pools[AMDGPU_IB_POOL_DIRECT], m); 483 484 return 0; 485 } 486 487 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_sa_info); 488 489 #endif 490 491 void amdgpu_debugfs_sa_init(struct amdgpu_device *adev) 492 { 493 #if defined(CONFIG_DEBUG_FS) 494 struct drm_minor *minor = adev_to_drm(adev)->primary; 495 struct dentry *root = minor->debugfs_root; 496 497 debugfs_create_file("amdgpu_sa_info", 0444, root, adev, 498 &amdgpu_debugfs_sa_info_fops); 499 500 #endif 501 } 502