1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 * Christian König 28 */ 29 #include <linux/seq_file.h> 30 #include <linux/slab.h> 31 #include <drm/drmP.h> 32 #include <drm/amdgpu_drm.h> 33 #include "amdgpu.h" 34 #include "atom.h" 35 36 /* 37 * IB 38 * IBs (Indirect Buffers) and areas of GPU accessible memory where 39 * commands are stored. You can put a pointer to the IB in the 40 * command ring and the hw will fetch the commands from the IB 41 * and execute them. Generally userspace acceleration drivers 42 * produce command buffers which are send to the kernel and 43 * put in IBs for execution by the requested ring. 44 */ 45 static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev); 46 47 /** 48 * amdgpu_ib_get - request an IB (Indirect Buffer) 49 * 50 * @ring: ring index the IB is associated with 51 * @size: requested IB size 52 * @ib: IB object returned 53 * 54 * Request an IB (all asics). IBs are allocated using the 55 * suballocator. 56 * Returns 0 on success, error on failure. 57 */ 58 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 59 unsigned size, struct amdgpu_ib *ib) 60 { 61 int r; 62 63 if (size) { 64 r = amdgpu_sa_bo_new(&adev->ring_tmp_bo, 65 &ib->sa_bo, size, 256); 66 if (r) { 67 dev_err(adev->dev, "failed to get a new IB (%d)\n", r); 68 return r; 69 } 70 71 ib->ptr = amdgpu_sa_bo_cpu_addr(ib->sa_bo); 72 73 if (!vm) 74 ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo); 75 } 76 77 ib->vm = vm; 78 ib->vm_id = 0; 79 80 return 0; 81 } 82 83 /** 84 * amdgpu_ib_free - free an IB (Indirect Buffer) 85 * 86 * @adev: amdgpu_device pointer 87 * @ib: IB object to free 88 * @f: the fence SA bo need wait on for the ib alloation 89 * 90 * Free an IB (all asics). 91 */ 92 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, struct fence *f) 93 { 94 amdgpu_sa_bo_free(adev, &ib->sa_bo, f); 95 } 96 97 /** 98 * amdgpu_ib_schedule - schedule an IB (Indirect Buffer) on the ring 99 * 100 * @adev: amdgpu_device pointer 101 * @num_ibs: number of IBs to schedule 102 * @ibs: IB objects to schedule 103 * @f: fence created during this submission 104 * 105 * Schedule an IB on the associated ring (all asics). 106 * Returns 0 on success, error on failure. 107 * 108 * On SI, there are two parallel engines fed from the primary ring, 109 * the CE (Constant Engine) and the DE (Drawing Engine). Since 110 * resource descriptors have moved to memory, the CE allows you to 111 * prime the caches while the DE is updating register state so that 112 * the resource descriptors will be already in cache when the draw is 113 * processed. To accomplish this, the userspace driver submits two 114 * IBs, one for the CE and one for the DE. If there is a CE IB (called 115 * a CONST_IB), it will be put on the ring prior to the DE IB. Prior 116 * to SI there was just a DE IB. 117 */ 118 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 119 struct amdgpu_ib *ibs, struct fence *last_vm_update, 120 struct fence **f) 121 { 122 struct amdgpu_device *adev = ring->adev; 123 struct amdgpu_ib *ib = &ibs[0]; 124 struct amdgpu_ctx *ctx, *old_ctx; 125 struct amdgpu_vm *vm; 126 struct fence *hwf; 127 unsigned i, patch_offset = ~0; 128 129 int r = 0; 130 131 if (num_ibs == 0) 132 return -EINVAL; 133 134 ctx = ibs->ctx; 135 vm = ibs->vm; 136 137 if (!ring->ready) { 138 dev_err(adev->dev, "couldn't schedule ib\n"); 139 return -EINVAL; 140 } 141 142 if (vm && !ibs->vm_id) { 143 dev_err(adev->dev, "VM IB without ID\n"); 144 return -EINVAL; 145 } 146 147 r = amdgpu_ring_alloc(ring, 256 * num_ibs); 148 if (r) { 149 dev_err(adev->dev, "scheduling IB failed (%d).\n", r); 150 return r; 151 } 152 153 if (ring->type == AMDGPU_RING_TYPE_SDMA && ring->funcs->init_cond_exec) 154 patch_offset = amdgpu_ring_init_cond_exec(ring); 155 156 if (vm) { 157 /* do context switch */ 158 r = amdgpu_vm_flush(ring, ib->vm_id, ib->vm_pd_addr, 159 ib->gds_base, ib->gds_size, 160 ib->gws_base, ib->gws_size, 161 ib->oa_base, ib->oa_size); 162 if (r) { 163 amdgpu_ring_undo(ring); 164 return r; 165 } 166 167 if (ring->funcs->emit_hdp_flush) 168 amdgpu_ring_emit_hdp_flush(ring); 169 } 170 171 /* always set cond_exec_polling to CONTINUE */ 172 *ring->cond_exe_cpu_addr = 1; 173 174 old_ctx = ring->current_ctx; 175 for (i = 0; i < num_ibs; ++i) { 176 ib = &ibs[i]; 177 178 if (ib->ctx != ctx || ib->vm != vm) { 179 ring->current_ctx = old_ctx; 180 if (ib->vm_id) 181 amdgpu_vm_reset_id(adev, ib->vm_id); 182 amdgpu_ring_undo(ring); 183 return -EINVAL; 184 } 185 amdgpu_ring_emit_ib(ring, ib); 186 ring->current_ctx = ctx; 187 } 188 189 if (vm) { 190 if (ring->funcs->emit_hdp_invalidate) 191 amdgpu_ring_emit_hdp_invalidate(ring); 192 } 193 194 r = amdgpu_fence_emit(ring, &hwf); 195 if (r) { 196 dev_err(adev->dev, "failed to emit fence (%d)\n", r); 197 ring->current_ctx = old_ctx; 198 if (ib->vm_id) 199 amdgpu_vm_reset_id(adev, ib->vm_id); 200 amdgpu_ring_undo(ring); 201 return r; 202 } 203 204 /* wrap the last IB with fence */ 205 if (ib->user) { 206 uint64_t addr = amdgpu_bo_gpu_offset(ib->user->bo); 207 addr += ib->user->offset; 208 amdgpu_ring_emit_fence(ring, addr, ib->sequence, 209 AMDGPU_FENCE_FLAG_64BIT); 210 } 211 212 if (f) 213 *f = fence_get(hwf); 214 215 if (patch_offset != ~0 && ring->funcs->patch_cond_exec) 216 amdgpu_ring_patch_cond_exec(ring, patch_offset); 217 218 amdgpu_ring_commit(ring); 219 return 0; 220 } 221 222 /** 223 * amdgpu_ib_pool_init - Init the IB (Indirect Buffer) pool 224 * 225 * @adev: amdgpu_device pointer 226 * 227 * Initialize the suballocator to manage a pool of memory 228 * for use as IBs (all asics). 229 * Returns 0 on success, error on failure. 230 */ 231 int amdgpu_ib_pool_init(struct amdgpu_device *adev) 232 { 233 int r; 234 235 if (adev->ib_pool_ready) { 236 return 0; 237 } 238 r = amdgpu_sa_bo_manager_init(adev, &adev->ring_tmp_bo, 239 AMDGPU_IB_POOL_SIZE*64*1024, 240 AMDGPU_GPU_PAGE_SIZE, 241 AMDGPU_GEM_DOMAIN_GTT); 242 if (r) { 243 return r; 244 } 245 246 r = amdgpu_sa_bo_manager_start(adev, &adev->ring_tmp_bo); 247 if (r) { 248 return r; 249 } 250 251 adev->ib_pool_ready = true; 252 if (amdgpu_debugfs_sa_init(adev)) { 253 dev_err(adev->dev, "failed to register debugfs file for SA\n"); 254 } 255 return 0; 256 } 257 258 /** 259 * amdgpu_ib_pool_fini - Free the IB (Indirect Buffer) pool 260 * 261 * @adev: amdgpu_device pointer 262 * 263 * Tear down the suballocator managing the pool of memory 264 * for use as IBs (all asics). 265 */ 266 void amdgpu_ib_pool_fini(struct amdgpu_device *adev) 267 { 268 if (adev->ib_pool_ready) { 269 amdgpu_sa_bo_manager_suspend(adev, &adev->ring_tmp_bo); 270 amdgpu_sa_bo_manager_fini(adev, &adev->ring_tmp_bo); 271 adev->ib_pool_ready = false; 272 } 273 } 274 275 /** 276 * amdgpu_ib_ring_tests - test IBs on the rings 277 * 278 * @adev: amdgpu_device pointer 279 * 280 * Test an IB (Indirect Buffer) on each ring. 281 * If the test fails, disable the ring. 282 * Returns 0 on success, error if the primary GFX ring 283 * IB test fails. 284 */ 285 int amdgpu_ib_ring_tests(struct amdgpu_device *adev) 286 { 287 unsigned i; 288 int r; 289 290 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { 291 struct amdgpu_ring *ring = adev->rings[i]; 292 293 if (!ring || !ring->ready) 294 continue; 295 296 r = amdgpu_ring_test_ib(ring); 297 if (r) { 298 ring->ready = false; 299 300 if (ring == &adev->gfx.gfx_ring[0]) { 301 /* oh, oh, that's really bad */ 302 DRM_ERROR("amdgpu: failed testing IB on GFX ring (%d).\n", r); 303 adev->accel_working = false; 304 return r; 305 306 } else { 307 /* still not good, but we can live with it */ 308 DRM_ERROR("amdgpu: failed testing IB on ring %d (%d).\n", i, r); 309 } 310 } 311 } 312 return 0; 313 } 314 315 /* 316 * Debugfs info 317 */ 318 #if defined(CONFIG_DEBUG_FS) 319 320 static int amdgpu_debugfs_sa_info(struct seq_file *m, void *data) 321 { 322 struct drm_info_node *node = (struct drm_info_node *) m->private; 323 struct drm_device *dev = node->minor->dev; 324 struct amdgpu_device *adev = dev->dev_private; 325 326 amdgpu_sa_bo_dump_debug_info(&adev->ring_tmp_bo, m); 327 328 return 0; 329 330 } 331 332 static const struct drm_info_list amdgpu_debugfs_sa_list[] = { 333 {"amdgpu_sa_info", &amdgpu_debugfs_sa_info, 0, NULL}, 334 }; 335 336 #endif 337 338 static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev) 339 { 340 #if defined(CONFIG_DEBUG_FS) 341 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_sa_list, 1); 342 #else 343 return 0; 344 #endif 345 } 346