1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include <linux/export.h> 27 28 #include <drm/drmP.h> 29 #include <drm/drm_edid.h> 30 #include <drm/amdgpu_drm.h> 31 #include "amdgpu.h" 32 #include "amdgpu_i2c.h" 33 #include "amdgpu_atombios.h" 34 #include "atom.h" 35 #include "atombios_dp.h" 36 #include "atombios_i2c.h" 37 38 /* bit banging i2c */ 39 static int amdgpu_i2c_pre_xfer(struct i2c_adapter *i2c_adap) 40 { 41 struct amdgpu_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 42 struct amdgpu_device *adev = i2c->dev->dev_private; 43 struct amdgpu_i2c_bus_rec *rec = &i2c->rec; 44 uint32_t temp; 45 46 mutex_lock(&i2c->mutex); 47 48 /* switch the pads to ddc mode */ 49 if (rec->hw_capable) { 50 temp = RREG32(rec->mask_clk_reg); 51 temp &= ~(1 << 16); 52 WREG32(rec->mask_clk_reg, temp); 53 } 54 55 /* clear the output pin values */ 56 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask; 57 WREG32(rec->a_clk_reg, temp); 58 59 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask; 60 WREG32(rec->a_data_reg, temp); 61 62 /* set the pins to input */ 63 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; 64 WREG32(rec->en_clk_reg, temp); 65 66 temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask; 67 WREG32(rec->en_data_reg, temp); 68 69 /* mask the gpio pins for software use */ 70 temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask; 71 WREG32(rec->mask_clk_reg, temp); 72 temp = RREG32(rec->mask_clk_reg); 73 74 temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask; 75 WREG32(rec->mask_data_reg, temp); 76 temp = RREG32(rec->mask_data_reg); 77 78 return 0; 79 } 80 81 static void amdgpu_i2c_post_xfer(struct i2c_adapter *i2c_adap) 82 { 83 struct amdgpu_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 84 struct amdgpu_device *adev = i2c->dev->dev_private; 85 struct amdgpu_i2c_bus_rec *rec = &i2c->rec; 86 uint32_t temp; 87 88 /* unmask the gpio pins for software use */ 89 temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask; 90 WREG32(rec->mask_clk_reg, temp); 91 temp = RREG32(rec->mask_clk_reg); 92 93 temp = RREG32(rec->mask_data_reg) & ~rec->mask_data_mask; 94 WREG32(rec->mask_data_reg, temp); 95 temp = RREG32(rec->mask_data_reg); 96 97 mutex_unlock(&i2c->mutex); 98 } 99 100 static int amdgpu_i2c_get_clock(void *i2c_priv) 101 { 102 struct amdgpu_i2c_chan *i2c = i2c_priv; 103 struct amdgpu_device *adev = i2c->dev->dev_private; 104 struct amdgpu_i2c_bus_rec *rec = &i2c->rec; 105 uint32_t val; 106 107 /* read the value off the pin */ 108 val = RREG32(rec->y_clk_reg); 109 val &= rec->y_clk_mask; 110 111 return (val != 0); 112 } 113 114 115 static int amdgpu_i2c_get_data(void *i2c_priv) 116 { 117 struct amdgpu_i2c_chan *i2c = i2c_priv; 118 struct amdgpu_device *adev = i2c->dev->dev_private; 119 struct amdgpu_i2c_bus_rec *rec = &i2c->rec; 120 uint32_t val; 121 122 /* read the value off the pin */ 123 val = RREG32(rec->y_data_reg); 124 val &= rec->y_data_mask; 125 126 return (val != 0); 127 } 128 129 static void amdgpu_i2c_set_clock(void *i2c_priv, int clock) 130 { 131 struct amdgpu_i2c_chan *i2c = i2c_priv; 132 struct amdgpu_device *adev = i2c->dev->dev_private; 133 struct amdgpu_i2c_bus_rec *rec = &i2c->rec; 134 uint32_t val; 135 136 /* set pin direction */ 137 val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; 138 val |= clock ? 0 : rec->en_clk_mask; 139 WREG32(rec->en_clk_reg, val); 140 } 141 142 static void amdgpu_i2c_set_data(void *i2c_priv, int data) 143 { 144 struct amdgpu_i2c_chan *i2c = i2c_priv; 145 struct amdgpu_device *adev = i2c->dev->dev_private; 146 struct amdgpu_i2c_bus_rec *rec = &i2c->rec; 147 uint32_t val; 148 149 /* set pin direction */ 150 val = RREG32(rec->en_data_reg) & ~rec->en_data_mask; 151 val |= data ? 0 : rec->en_data_mask; 152 WREG32(rec->en_data_reg, val); 153 } 154 155 static const struct i2c_algorithm amdgpu_atombios_i2c_algo = { 156 .master_xfer = amdgpu_atombios_i2c_xfer, 157 .functionality = amdgpu_atombios_i2c_func, 158 }; 159 160 struct amdgpu_i2c_chan *amdgpu_i2c_create(struct drm_device *dev, 161 struct amdgpu_i2c_bus_rec *rec, 162 const char *name) 163 { 164 struct amdgpu_i2c_chan *i2c; 165 int ret; 166 167 /* don't add the mm_i2c bus unless hw_i2c is enabled */ 168 if (rec->mm_i2c && (amdgpu_hw_i2c == 0)) 169 return NULL; 170 171 i2c = kzalloc(sizeof(struct amdgpu_i2c_chan), GFP_KERNEL); 172 if (i2c == NULL) 173 return NULL; 174 175 i2c->rec = *rec; 176 i2c->adapter.owner = THIS_MODULE; 177 i2c->adapter.class = I2C_CLASS_DDC; 178 i2c->adapter.dev.parent = &dev->pdev->dev; 179 i2c->dev = dev; 180 i2c_set_adapdata(&i2c->adapter, i2c); 181 mutex_init(&i2c->mutex); 182 if (rec->hw_capable && 183 amdgpu_hw_i2c) { 184 /* hw i2c using atom */ 185 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 186 "AMDGPU i2c hw bus %s", name); 187 i2c->adapter.algo = &amdgpu_atombios_i2c_algo; 188 ret = i2c_add_adapter(&i2c->adapter); 189 if (ret) { 190 DRM_ERROR("Failed to register hw i2c %s\n", name); 191 goto out_free; 192 } 193 } else { 194 /* set the amdgpu bit adapter */ 195 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 196 "AMDGPU i2c bit bus %s", name); 197 i2c->adapter.algo_data = &i2c->bit; 198 i2c->bit.pre_xfer = amdgpu_i2c_pre_xfer; 199 i2c->bit.post_xfer = amdgpu_i2c_post_xfer; 200 i2c->bit.setsda = amdgpu_i2c_set_data; 201 i2c->bit.setscl = amdgpu_i2c_set_clock; 202 i2c->bit.getsda = amdgpu_i2c_get_data; 203 i2c->bit.getscl = amdgpu_i2c_get_clock; 204 i2c->bit.udelay = 10; 205 i2c->bit.timeout = usecs_to_jiffies(2200); /* from VESA */ 206 i2c->bit.data = i2c; 207 ret = i2c_bit_add_bus(&i2c->adapter); 208 if (ret) { 209 DRM_ERROR("Failed to register bit i2c %s\n", name); 210 goto out_free; 211 } 212 } 213 214 return i2c; 215 out_free: 216 kfree(i2c); 217 return NULL; 218 219 } 220 221 void amdgpu_i2c_destroy(struct amdgpu_i2c_chan *i2c) 222 { 223 if (!i2c) 224 return; 225 i2c_del_adapter(&i2c->adapter); 226 kfree(i2c); 227 } 228 229 /* Add the default buses */ 230 void amdgpu_i2c_init(struct amdgpu_device *adev) 231 { 232 if (amdgpu_hw_i2c) 233 DRM_INFO("hw_i2c forced on, you may experience display detection problems!\n"); 234 235 if (adev->is_atom_bios) 236 amdgpu_atombios_i2c_init(adev); 237 } 238 239 /* remove all the buses */ 240 void amdgpu_i2c_fini(struct amdgpu_device *adev) 241 { 242 int i; 243 244 for (i = 0; i < AMDGPU_MAX_I2C_BUS; i++) { 245 if (adev->i2c_bus[i]) { 246 amdgpu_i2c_destroy(adev->i2c_bus[i]); 247 adev->i2c_bus[i] = NULL; 248 } 249 } 250 } 251 252 /* Add additional buses */ 253 void amdgpu_i2c_add(struct amdgpu_device *adev, 254 struct amdgpu_i2c_bus_rec *rec, 255 const char *name) 256 { 257 struct drm_device *dev = adev->ddev; 258 int i; 259 260 for (i = 0; i < AMDGPU_MAX_I2C_BUS; i++) { 261 if (!adev->i2c_bus[i]) { 262 adev->i2c_bus[i] = amdgpu_i2c_create(dev, rec, name); 263 return; 264 } 265 } 266 } 267 268 /* looks up bus based on id */ 269 struct amdgpu_i2c_chan * 270 amdgpu_i2c_lookup(struct amdgpu_device *adev, 271 struct amdgpu_i2c_bus_rec *i2c_bus) 272 { 273 int i; 274 275 for (i = 0; i < AMDGPU_MAX_I2C_BUS; i++) { 276 if (adev->i2c_bus[i] && 277 (adev->i2c_bus[i]->rec.i2c_id == i2c_bus->i2c_id)) { 278 return adev->i2c_bus[i]; 279 } 280 } 281 return NULL; 282 } 283 284 static void amdgpu_i2c_get_byte(struct amdgpu_i2c_chan *i2c_bus, 285 u8 slave_addr, 286 u8 addr, 287 u8 *val) 288 { 289 u8 out_buf[2]; 290 u8 in_buf[2]; 291 struct i2c_msg msgs[] = { 292 { 293 .addr = slave_addr, 294 .flags = 0, 295 .len = 1, 296 .buf = out_buf, 297 }, 298 { 299 .addr = slave_addr, 300 .flags = I2C_M_RD, 301 .len = 1, 302 .buf = in_buf, 303 } 304 }; 305 306 out_buf[0] = addr; 307 out_buf[1] = 0; 308 309 if (i2c_transfer(&i2c_bus->adapter, msgs, 2) == 2) { 310 *val = in_buf[0]; 311 DRM_DEBUG("val = 0x%02x\n", *val); 312 } else { 313 DRM_DEBUG("i2c 0x%02x 0x%02x read failed\n", 314 addr, *val); 315 } 316 } 317 318 static void amdgpu_i2c_put_byte(struct amdgpu_i2c_chan *i2c_bus, 319 u8 slave_addr, 320 u8 addr, 321 u8 val) 322 { 323 uint8_t out_buf[2]; 324 struct i2c_msg msg = { 325 .addr = slave_addr, 326 .flags = 0, 327 .len = 2, 328 .buf = out_buf, 329 }; 330 331 out_buf[0] = addr; 332 out_buf[1] = val; 333 334 if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1) 335 DRM_DEBUG("i2c 0x%02x 0x%02x write failed\n", 336 addr, val); 337 } 338 339 /* ddc router switching */ 340 void 341 amdgpu_i2c_router_select_ddc_port(struct amdgpu_connector *amdgpu_connector) 342 { 343 u8 val; 344 345 if (!amdgpu_connector->router.ddc_valid) 346 return; 347 348 if (!amdgpu_connector->router_bus) 349 return; 350 351 amdgpu_i2c_get_byte(amdgpu_connector->router_bus, 352 amdgpu_connector->router.i2c_addr, 353 0x3, &val); 354 val &= ~amdgpu_connector->router.ddc_mux_control_pin; 355 amdgpu_i2c_put_byte(amdgpu_connector->router_bus, 356 amdgpu_connector->router.i2c_addr, 357 0x3, val); 358 amdgpu_i2c_get_byte(amdgpu_connector->router_bus, 359 amdgpu_connector->router.i2c_addr, 360 0x1, &val); 361 val &= ~amdgpu_connector->router.ddc_mux_control_pin; 362 val |= amdgpu_connector->router.ddc_mux_state; 363 amdgpu_i2c_put_byte(amdgpu_connector->router_bus, 364 amdgpu_connector->router.i2c_addr, 365 0x1, val); 366 } 367 368 /* clock/data router switching */ 369 void 370 amdgpu_i2c_router_select_cd_port(struct amdgpu_connector *amdgpu_connector) 371 { 372 u8 val; 373 374 if (!amdgpu_connector->router.cd_valid) 375 return; 376 377 if (!amdgpu_connector->router_bus) 378 return; 379 380 amdgpu_i2c_get_byte(amdgpu_connector->router_bus, 381 amdgpu_connector->router.i2c_addr, 382 0x3, &val); 383 val &= ~amdgpu_connector->router.cd_mux_control_pin; 384 amdgpu_i2c_put_byte(amdgpu_connector->router_bus, 385 amdgpu_connector->router.i2c_addr, 386 0x3, val); 387 amdgpu_i2c_get_byte(amdgpu_connector->router_bus, 388 amdgpu_connector->router.i2c_addr, 389 0x1, &val); 390 val &= ~amdgpu_connector->router.cd_mux_control_pin; 391 val |= amdgpu_connector->router.cd_mux_state; 392 amdgpu_i2c_put_byte(amdgpu_connector->router_bus, 393 amdgpu_connector->router.i2c_addr, 394 0x1, val); 395 } 396