1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Christian König <christian.koenig@amd.com> 29 */ 30 31 /** 32 * DOC: MMU Notifier 33 * 34 * For coherent userptr handling registers an MMU notifier to inform the driver 35 * about updates on the page tables of a process. 36 * 37 * When somebody tries to invalidate the page tables we block the update until 38 * all operations on the pages in question are completed, then those pages are 39 * marked as accessed and also dirty if it wasn't a read only access. 40 * 41 * New command submissions using the userptrs in question are delayed until all 42 * page table invalidation are completed and we once more see a coherent process 43 * address space. 44 */ 45 46 #include <linux/firmware.h> 47 #include <linux/module.h> 48 #include <drm/drm.h> 49 50 #include "amdgpu.h" 51 #include "amdgpu_amdkfd.h" 52 #include "amdgpu_hmm.h" 53 54 /** 55 * amdgpu_hmm_invalidate_gfx - callback to notify about mm change 56 * 57 * @mni: the range (mm) is about to update 58 * @range: details on the invalidation 59 * @cur_seq: Value to pass to mmu_interval_set_seq() 60 * 61 * Block for operations on BOs to finish and mark pages as accessed and 62 * potentially dirty. 63 */ 64 static bool amdgpu_hmm_invalidate_gfx(struct mmu_interval_notifier *mni, 65 const struct mmu_notifier_range *range, 66 unsigned long cur_seq) 67 { 68 struct amdgpu_bo *bo = container_of(mni, struct amdgpu_bo, notifier); 69 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 70 struct amdgpu_bo *vm_root = bo->vm_bo->vm->root.bo; 71 long r; 72 73 if (!mmu_notifier_range_blockable(range)) 74 return false; 75 76 mutex_lock(&adev->notifier_lock); 77 78 mmu_interval_set_seq(mni, cur_seq); 79 80 amdgpu_vm_bo_invalidate(bo, false); 81 r = dma_resv_wait_timeout(vm_root->tbo.base.resv, 82 DMA_RESV_USAGE_BOOKKEEP, false, 83 MAX_SCHEDULE_TIMEOUT); 84 mutex_unlock(&adev->notifier_lock); 85 if (r <= 0) 86 DRM_ERROR("(%ld) failed to wait for user bo\n", r); 87 return true; 88 } 89 90 static const struct mmu_interval_notifier_ops amdgpu_hmm_gfx_ops = { 91 .invalidate = amdgpu_hmm_invalidate_gfx, 92 }; 93 94 /** 95 * amdgpu_hmm_invalidate_hsa - callback to notify about mm change 96 * 97 * @mni: the range (mm) is about to update 98 * @range: details on the invalidation 99 * @cur_seq: Value to pass to mmu_interval_set_seq() 100 * 101 * We temporarily evict the BO attached to this range. This necessitates 102 * evicting all user-mode queues of the process. 103 */ 104 static bool amdgpu_hmm_invalidate_hsa(struct mmu_interval_notifier *mni, 105 const struct mmu_notifier_range *range, 106 unsigned long cur_seq) 107 { 108 struct amdgpu_bo *bo = container_of(mni, struct amdgpu_bo, notifier); 109 110 if (!mmu_notifier_range_blockable(range)) 111 return false; 112 113 amdgpu_amdkfd_evict_userptr(mni, cur_seq, bo->kfd_bo); 114 115 return true; 116 } 117 118 static const struct mmu_interval_notifier_ops amdgpu_hmm_hsa_ops = { 119 .invalidate = amdgpu_hmm_invalidate_hsa, 120 }; 121 122 /** 123 * amdgpu_hmm_register - register a BO for notifier updates 124 * 125 * @bo: amdgpu buffer object 126 * @addr: userptr addr we should monitor 127 * 128 * Registers a mmu_notifier for the given BO at the specified address. 129 * Returns 0 on success, -ERRNO if anything goes wrong. 130 */ 131 int amdgpu_hmm_register(struct amdgpu_bo *bo, unsigned long addr) 132 { 133 int r; 134 135 if (bo->kfd_bo) 136 r = mmu_interval_notifier_insert(&bo->notifier, current->mm, 137 addr, amdgpu_bo_size(bo), 138 &amdgpu_hmm_hsa_ops); 139 else 140 r = mmu_interval_notifier_insert(&bo->notifier, current->mm, addr, 141 amdgpu_bo_size(bo), 142 &amdgpu_hmm_gfx_ops); 143 if (r) 144 /* 145 * Make sure amdgpu_hmm_unregister() doesn't call 146 * mmu_interval_notifier_remove() when the notifier isn't properly 147 * initialized. 148 */ 149 bo->notifier.mm = NULL; 150 151 return r; 152 } 153 154 /** 155 * amdgpu_hmm_unregister - unregister a BO for notifier updates 156 * 157 * @bo: amdgpu buffer object 158 * 159 * Remove any registration of mmu notifier updates from the buffer object. 160 */ 161 void amdgpu_hmm_unregister(struct amdgpu_bo *bo) 162 { 163 if (!bo->notifier.mm) 164 return; 165 mmu_interval_notifier_remove(&bo->notifier); 166 bo->notifier.mm = NULL; 167 } 168 169 int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier, 170 uint64_t start, uint64_t npages, bool readonly, 171 void *owner, 172 struct amdgpu_hmm_range *range) 173 { 174 const u64 max_bytes = SZ_2G; 175 176 struct hmm_range *hmm_range = &range->hmm_range; 177 unsigned long *pfns; 178 unsigned long end; 179 int r; 180 181 pfns = kvmalloc_array(npages, sizeof(*pfns), GFP_KERNEL); 182 if (unlikely(!pfns)) { 183 r = -ENOMEM; 184 goto out_free_range; 185 } 186 187 hmm_range->notifier = notifier; 188 hmm_range->default_flags = HMM_PFN_REQ_FAULT; 189 if (!readonly) 190 hmm_range->default_flags |= HMM_PFN_REQ_WRITE; 191 hmm_range->hmm_pfns = pfns; 192 hmm_range->start = start; 193 end = start + npages * PAGE_SIZE; 194 hmm_range->dev_private_owner = owner; 195 196 hmm_range->notifier_seq = mmu_interval_read_begin(notifier); 197 do { 198 hmm_range->end = min(hmm_range->start + max_bytes, end); 199 200 pr_debug("hmm range: start = 0x%lx, end = 0x%lx", 201 hmm_range->start, hmm_range->end); 202 203 r = hmm_range_fault(hmm_range); 204 if (unlikely(r)) 205 goto out_free_pfns; 206 207 if (hmm_range->end == end) 208 break; 209 hmm_range->hmm_pfns += max_bytes >> PAGE_SHIFT; 210 hmm_range->start = hmm_range->end; 211 } while (hmm_range->end < end); 212 213 hmm_range->start = start; 214 hmm_range->hmm_pfns = pfns; 215 216 return 0; 217 218 out_free_pfns: 219 kvfree(pfns); 220 hmm_range->hmm_pfns = NULL; 221 out_free_range: 222 if (r == -EBUSY) 223 r = -EAGAIN; 224 return r; 225 } 226 227 /** 228 * amdgpu_hmm_range_valid - check if an HMM range is still valid 229 * @range: pointer to the &struct amdgpu_hmm_range to validate 230 * 231 * Determines whether the given HMM range @range is still valid by 232 * checking for invalidations via the MMU notifier sequence. This is 233 * typically used to verify that the range has not been invalidated 234 * by concurrent address space updates before it is accessed. 235 * 236 * Return: 237 * * true if @range is valid and can be used safely 238 * * false if @range is NULL or has been invalidated 239 */ 240 bool amdgpu_hmm_range_valid(struct amdgpu_hmm_range *range) 241 { 242 if (!range) 243 return false; 244 245 return !mmu_interval_read_retry(range->hmm_range.notifier, 246 range->hmm_range.notifier_seq); 247 } 248 249 /** 250 * amdgpu_hmm_range_alloc - allocate and initialize an AMDGPU HMM range 251 * @bo: optional buffer object to associate with this HMM range 252 * 253 * Allocates memory for amdgpu_hmm_range and associates it with the @bo passed. 254 * The reference count of the @bo is incremented. 255 * 256 * Return: 257 * Pointer to a newly allocated struct amdgpu_hmm_range on success, 258 * or NULL if memory allocation fails. 259 */ 260 struct amdgpu_hmm_range *amdgpu_hmm_range_alloc(struct amdgpu_bo *bo) 261 { 262 struct amdgpu_hmm_range *range; 263 264 range = kzalloc_obj(*range); 265 if (!range) 266 return NULL; 267 268 range->bo = amdgpu_bo_ref(bo); 269 return range; 270 } 271 272 /** 273 * amdgpu_hmm_range_free - release an AMDGPU HMM range 274 * @range: pointer to the range object to free 275 * 276 * Releases all resources held by @range, including the associated 277 * hmm_pfns and the dropping reference of associated bo if any. 278 * 279 * Return: void 280 */ 281 void amdgpu_hmm_range_free(struct amdgpu_hmm_range *range) 282 { 283 if (!range) 284 return; 285 286 kvfree(range->hmm_range.hmm_pfns); 287 amdgpu_bo_unref(&range->bo); 288 kfree(range); 289 } 290