1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Christian König <christian.koenig@amd.com> 29 */ 30 31 /** 32 * DOC: MMU Notifier 33 * 34 * For coherent userptr handling registers an MMU notifier to inform the driver 35 * about updates on the page tables of a process. 36 * 37 * When somebody tries to invalidate the page tables we block the update until 38 * all operations on the pages in question are completed, then those pages are 39 * marked as accessed and also dirty if it wasn't a read only access. 40 * 41 * New command submissions using the userptrs in question are delayed until all 42 * page table invalidation are completed and we once more see a coherent process 43 * address space. 44 */ 45 46 #include <linux/firmware.h> 47 #include <linux/module.h> 48 #include <drm/drm.h> 49 50 #include "amdgpu.h" 51 #include "amdgpu_amdkfd.h" 52 #include "amdgpu_hmm.h" 53 54 /** 55 * amdgpu_hmm_invalidate_gfx - callback to notify about mm change 56 * 57 * @mni: the range (mm) is about to update 58 * @range: details on the invalidation 59 * @cur_seq: Value to pass to mmu_interval_set_seq() 60 * 61 * Block for operations on BOs to finish and mark pages as accessed and 62 * potentially dirty. 63 */ 64 static bool amdgpu_hmm_invalidate_gfx(struct mmu_interval_notifier *mni, 65 const struct mmu_notifier_range *range, 66 unsigned long cur_seq) 67 { 68 struct amdgpu_bo *bo = container_of(mni, struct amdgpu_bo, notifier); 69 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 70 long r; 71 72 if (!mmu_notifier_range_blockable(range)) 73 return false; 74 75 mutex_lock(&adev->notifier_lock); 76 77 mmu_interval_set_seq(mni, cur_seq); 78 79 amdgpu_vm_bo_invalidate(bo, false); 80 r = dma_resv_wait_timeout(bo->parent->tbo.base.resv, 81 DMA_RESV_USAGE_BOOKKEEP, false, 82 MAX_SCHEDULE_TIMEOUT); 83 mutex_unlock(&adev->notifier_lock); 84 if (r <= 0) 85 DRM_ERROR("(%ld) failed to wait for user bo\n", r); 86 return true; 87 } 88 89 static const struct mmu_interval_notifier_ops amdgpu_hmm_gfx_ops = { 90 .invalidate = amdgpu_hmm_invalidate_gfx, 91 }; 92 93 /** 94 * amdgpu_hmm_invalidate_hsa - callback to notify about mm change 95 * 96 * @mni: the range (mm) is about to update 97 * @range: details on the invalidation 98 * @cur_seq: Value to pass to mmu_interval_set_seq() 99 * 100 * We temporarily evict the BO attached to this range. This necessitates 101 * evicting all user-mode queues of the process. 102 */ 103 static bool amdgpu_hmm_invalidate_hsa(struct mmu_interval_notifier *mni, 104 const struct mmu_notifier_range *range, 105 unsigned long cur_seq) 106 { 107 struct amdgpu_bo *bo = container_of(mni, struct amdgpu_bo, notifier); 108 109 if (!mmu_notifier_range_blockable(range)) 110 return false; 111 112 amdgpu_amdkfd_evict_userptr(mni, cur_seq, bo->kfd_bo); 113 114 return true; 115 } 116 117 static const struct mmu_interval_notifier_ops amdgpu_hmm_hsa_ops = { 118 .invalidate = amdgpu_hmm_invalidate_hsa, 119 }; 120 121 /** 122 * amdgpu_hmm_register - register a BO for notifier updates 123 * 124 * @bo: amdgpu buffer object 125 * @addr: userptr addr we should monitor 126 * 127 * Registers a mmu_notifier for the given BO at the specified address. 128 * Returns 0 on success, -ERRNO if anything goes wrong. 129 */ 130 int amdgpu_hmm_register(struct amdgpu_bo *bo, unsigned long addr) 131 { 132 int r; 133 134 if (bo->kfd_bo) 135 r = mmu_interval_notifier_insert(&bo->notifier, current->mm, 136 addr, amdgpu_bo_size(bo), 137 &amdgpu_hmm_hsa_ops); 138 else 139 r = mmu_interval_notifier_insert(&bo->notifier, current->mm, addr, 140 amdgpu_bo_size(bo), 141 &amdgpu_hmm_gfx_ops); 142 if (r) 143 /* 144 * Make sure amdgpu_hmm_unregister() doesn't call 145 * mmu_interval_notifier_remove() when the notifier isn't properly 146 * initialized. 147 */ 148 bo->notifier.mm = NULL; 149 150 return r; 151 } 152 153 /** 154 * amdgpu_hmm_unregister - unregister a BO for notifier updates 155 * 156 * @bo: amdgpu buffer object 157 * 158 * Remove any registration of mmu notifier updates from the buffer object. 159 */ 160 void amdgpu_hmm_unregister(struct amdgpu_bo *bo) 161 { 162 if (!bo->notifier.mm) 163 return; 164 mmu_interval_notifier_remove(&bo->notifier); 165 bo->notifier.mm = NULL; 166 } 167 168 int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier, 169 uint64_t start, uint64_t npages, bool readonly, 170 void *owner, 171 struct amdgpu_hmm_range *range) 172 { 173 const u64 max_bytes = SZ_2G; 174 175 struct hmm_range *hmm_range = &range->hmm_range; 176 unsigned long *pfns; 177 unsigned long end; 178 int r; 179 180 pfns = kvmalloc_array(npages, sizeof(*pfns), GFP_KERNEL); 181 if (unlikely(!pfns)) { 182 r = -ENOMEM; 183 goto out_free_range; 184 } 185 186 hmm_range->notifier = notifier; 187 hmm_range->default_flags = HMM_PFN_REQ_FAULT; 188 if (!readonly) 189 hmm_range->default_flags |= HMM_PFN_REQ_WRITE; 190 hmm_range->hmm_pfns = pfns; 191 hmm_range->start = start; 192 end = start + npages * PAGE_SIZE; 193 hmm_range->dev_private_owner = owner; 194 195 hmm_range->notifier_seq = mmu_interval_read_begin(notifier); 196 do { 197 hmm_range->end = min(hmm_range->start + max_bytes, end); 198 199 pr_debug("hmm range: start = 0x%lx, end = 0x%lx", 200 hmm_range->start, hmm_range->end); 201 202 r = hmm_range_fault(hmm_range); 203 if (unlikely(r)) 204 goto out_free_pfns; 205 206 if (hmm_range->end == end) 207 break; 208 hmm_range->hmm_pfns += max_bytes >> PAGE_SHIFT; 209 hmm_range->start = hmm_range->end; 210 } while (hmm_range->end < end); 211 212 hmm_range->start = start; 213 hmm_range->hmm_pfns = pfns; 214 215 return 0; 216 217 out_free_pfns: 218 kvfree(pfns); 219 hmm_range->hmm_pfns = NULL; 220 out_free_range: 221 if (r == -EBUSY) 222 r = -EAGAIN; 223 return r; 224 } 225 226 /** 227 * amdgpu_hmm_range_valid - check if an HMM range is still valid 228 * @range: pointer to the &struct amdgpu_hmm_range to validate 229 * 230 * Determines whether the given HMM range @range is still valid by 231 * checking for invalidations via the MMU notifier sequence. This is 232 * typically used to verify that the range has not been invalidated 233 * by concurrent address space updates before it is accessed. 234 * 235 * Return: 236 * * true if @range is valid and can be used safely 237 * * false if @range is NULL or has been invalidated 238 */ 239 bool amdgpu_hmm_range_valid(struct amdgpu_hmm_range *range) 240 { 241 if (!range) 242 return false; 243 244 return !mmu_interval_read_retry(range->hmm_range.notifier, 245 range->hmm_range.notifier_seq); 246 } 247 248 /** 249 * amdgpu_hmm_range_alloc - allocate and initialize an AMDGPU HMM range 250 * @bo: optional buffer object to associate with this HMM range 251 * 252 * Allocates memory for amdgpu_hmm_range and associates it with the @bo passed. 253 * The reference count of the @bo is incremented. 254 * 255 * Return: 256 * Pointer to a newly allocated struct amdgpu_hmm_range on success, 257 * or NULL if memory allocation fails. 258 */ 259 struct amdgpu_hmm_range *amdgpu_hmm_range_alloc(struct amdgpu_bo *bo) 260 { 261 struct amdgpu_hmm_range *range; 262 263 range = kzalloc_obj(*range); 264 if (!range) 265 return NULL; 266 267 range->bo = amdgpu_bo_ref(bo); 268 return range; 269 } 270 271 /** 272 * amdgpu_hmm_range_free - release an AMDGPU HMM range 273 * @range: pointer to the range object to free 274 * 275 * Releases all resources held by @range, including the associated 276 * hmm_pfns and the dropping reference of associated bo if any. 277 * 278 * Return: void 279 */ 280 void amdgpu_hmm_range_free(struct amdgpu_hmm_range *range) 281 { 282 if (!range) 283 return; 284 285 kvfree(range->hmm_range.hmm_pfns); 286 amdgpu_bo_unref(&range->bo); 287 kfree(range); 288 } 289