1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 #ifndef __AMDGPU_GMC_H__ 27 #define __AMDGPU_GMC_H__ 28 29 #include <linux/types.h> 30 31 #include "amdgpu_irq.h" 32 #include "amdgpu_xgmi.h" 33 #include "amdgpu_ras.h" 34 35 /* VA hole for 48bit addresses on Vega10 */ 36 #define AMDGPU_GMC_HOLE_START 0x0000800000000000ULL 37 #define AMDGPU_GMC_HOLE_END 0xffff800000000000ULL 38 39 /* 40 * Hardware is programmed as if the hole doesn't exists with start and end 41 * address values. 42 * 43 * This mask is used to remove the upper 16bits of the VA and so come up with 44 * the linear addr value. 45 */ 46 #define AMDGPU_GMC_HOLE_MASK 0x0000ffffffffffffULL 47 48 /* 49 * Ring size as power of two for the log of recent faults. 50 */ 51 #define AMDGPU_GMC_FAULT_RING_ORDER 8 52 #define AMDGPU_GMC_FAULT_RING_SIZE (1 << AMDGPU_GMC_FAULT_RING_ORDER) 53 54 /* 55 * Hash size as power of two for the log of recent faults 56 */ 57 #define AMDGPU_GMC_FAULT_HASH_ORDER 8 58 #define AMDGPU_GMC_FAULT_HASH_SIZE (1 << AMDGPU_GMC_FAULT_HASH_ORDER) 59 60 /* 61 * Number of IH timestamp ticks until a fault is considered handled 62 */ 63 #define AMDGPU_GMC_FAULT_TIMEOUT 5000ULL 64 65 struct firmware; 66 67 enum amdgpu_memory_partition { 68 UNKNOWN_MEMORY_PARTITION_MODE = 0, 69 AMDGPU_NPS1_PARTITION_MODE = 1, 70 AMDGPU_NPS2_PARTITION_MODE = 2, 71 AMDGPU_NPS3_PARTITION_MODE = 3, 72 AMDGPU_NPS4_PARTITION_MODE = 4, 73 AMDGPU_NPS6_PARTITION_MODE = 6, 74 AMDGPU_NPS8_PARTITION_MODE = 8, 75 }; 76 77 #define AMDGPU_ALL_NPS_MASK \ 78 (BIT(AMDGPU_NPS1_PARTITION_MODE) | BIT(AMDGPU_NPS2_PARTITION_MODE) | \ 79 BIT(AMDGPU_NPS3_PARTITION_MODE) | BIT(AMDGPU_NPS4_PARTITION_MODE) | \ 80 BIT(AMDGPU_NPS6_PARTITION_MODE) | BIT(AMDGPU_NPS8_PARTITION_MODE)) 81 82 #define AMDGPU_GMC_INIT_RESET_NPS BIT(0) 83 84 /* 85 * GMC page fault information 86 */ 87 struct amdgpu_gmc_fault { 88 uint64_t timestamp:48; 89 uint64_t next:AMDGPU_GMC_FAULT_RING_ORDER; 90 atomic64_t key; 91 uint64_t timestamp_expiry:48; 92 }; 93 94 /* 95 * VMHUB structures, functions & helpers 96 */ 97 struct amdgpu_vmhub_funcs { 98 void (*print_l2_protection_fault_status)(struct amdgpu_device *adev, 99 uint32_t status); 100 uint32_t (*get_invalidate_req)(unsigned int vmid, uint32_t flush_type); 101 }; 102 103 struct amdgpu_vmhub { 104 uint32_t ctx0_ptb_addr_lo32; 105 uint32_t ctx0_ptb_addr_hi32; 106 uint32_t vm_inv_eng0_sem; 107 uint32_t vm_inv_eng0_req; 108 uint32_t vm_inv_eng0_ack; 109 uint32_t vm_context0_cntl; 110 uint32_t vm_l2_pro_fault_status; 111 uint32_t vm_l2_pro_fault_cntl; 112 113 /* 114 * store the register distances between two continuous context domain 115 * and invalidation engine. 116 */ 117 uint32_t ctx_distance; 118 uint32_t ctx_addr_distance; /* include LO32/HI32 */ 119 uint32_t eng_distance; 120 uint32_t eng_addr_distance; /* include LO32/HI32 */ 121 122 uint32_t vm_cntx_cntl; 123 uint32_t vm_cntx_cntl_vm_fault; 124 uint32_t vm_l2_bank_select_reserved_cid2; 125 126 uint32_t vm_contexts_disable; 127 128 bool sdma_invalidation_workaround; 129 130 const struct amdgpu_vmhub_funcs *vmhub_funcs; 131 }; 132 133 /* 134 * GPU MC structures, functions & helpers 135 */ 136 struct amdgpu_gmc_funcs { 137 /* flush the vm tlb via mmio */ 138 void (*flush_gpu_tlb)(struct amdgpu_device *adev, uint32_t vmid, 139 uint32_t vmhub, uint32_t flush_type); 140 /* flush the vm tlb via pasid */ 141 void (*flush_gpu_tlb_pasid)(struct amdgpu_device *adev, uint16_t pasid, 142 uint32_t flush_type, bool all_hub, 143 uint32_t inst); 144 /* flush the vm tlb via ring */ 145 uint64_t (*emit_flush_gpu_tlb)(struct amdgpu_ring *ring, unsigned vmid, 146 uint64_t pd_addr); 147 /* Change the VMID -> PASID mapping */ 148 void (*emit_pasid_mapping)(struct amdgpu_ring *ring, unsigned vmid, 149 unsigned pasid); 150 /* enable/disable PRT support */ 151 void (*set_prt)(struct amdgpu_device *adev, bool enable); 152 /* map mtype to hardware flags */ 153 uint64_t (*map_mtype)(struct amdgpu_device *adev, uint32_t flags); 154 /* get the pde for a given mc addr */ 155 void (*get_vm_pde)(struct amdgpu_device *adev, int level, 156 u64 *dst, u64 *flags); 157 /* get the pte flags to use for a BO VA mapping */ 158 void (*get_vm_pte)(struct amdgpu_device *adev, 159 struct amdgpu_bo_va_mapping *mapping, 160 uint64_t *flags); 161 /* override per-page pte flags */ 162 void (*override_vm_pte_flags)(struct amdgpu_device *dev, 163 struct amdgpu_vm *vm, 164 uint64_t addr, uint64_t *flags); 165 /* get the amount of memory used by the vbios for pre-OS console */ 166 unsigned int (*get_vbios_fb_size)(struct amdgpu_device *adev); 167 /* get the DCC buffer alignment */ 168 unsigned int (*get_dcc_alignment)(struct amdgpu_device *adev); 169 170 enum amdgpu_memory_partition (*query_mem_partition_mode)( 171 struct amdgpu_device *adev); 172 /* Request NPS mode */ 173 int (*request_mem_partition_mode)(struct amdgpu_device *adev, 174 int nps_mode); 175 bool (*need_reset_on_init)(struct amdgpu_device *adev); 176 }; 177 178 struct amdgpu_mem_partition_info { 179 union { 180 struct { 181 uint32_t fpfn; 182 uint32_t lpfn; 183 } range; 184 struct { 185 int node; 186 } numa; 187 }; 188 uint64_t size; 189 }; 190 191 #define INVALID_PFN -1 192 193 struct amdgpu_gmc_memrange { 194 uint64_t base_address; 195 uint64_t limit_address; 196 uint32_t flags; 197 int nid_mask; 198 }; 199 200 enum amdgpu_gart_placement { 201 AMDGPU_GART_PLACEMENT_BEST_FIT = 0, 202 AMDGPU_GART_PLACEMENT_HIGH, 203 AMDGPU_GART_PLACEMENT_LOW, 204 }; 205 206 struct amdgpu_gmc { 207 /* FB's physical address in MMIO space (for CPU to 208 * map FB). This is different compared to the agp/ 209 * gart/vram_start/end field as the later is from 210 * GPU's view and aper_base is from CPU's view. 211 */ 212 resource_size_t aper_size; 213 resource_size_t aper_base; 214 /* for some chips with <= 32MB we need to lie 215 * about vram size near mc fb location */ 216 u64 mc_vram_size; 217 u64 visible_vram_size; 218 /* AGP aperture start and end in MC address space 219 * Driver find a hole in the MC address space 220 * to place AGP by setting MC_VM_AGP_BOT/TOP registers 221 * Under VMID0, logical address == MC address. AGP 222 * aperture maps to physical bus or IOVA addressed. 223 * AGP aperture is used to simulate FB in ZFB case. 224 * AGP aperture is also used for page table in system 225 * memory (mainly for APU). 226 * 227 */ 228 u64 agp_size; 229 u64 agp_start; 230 u64 agp_end; 231 /* GART aperture start and end in MC address space 232 * Driver find a hole in the MC address space 233 * to place GART by setting VM_CONTEXT0_PAGE_TABLE_START/END_ADDR 234 * registers 235 * Under VMID0, logical address inside GART aperture will 236 * be translated through gpuvm gart page table to access 237 * paged system memory 238 */ 239 u64 gart_size; 240 u64 gart_start; 241 u64 gart_end; 242 /* Frame buffer aperture of this GPU device. Different from 243 * fb_start (see below), this only covers the local GPU device. 244 * If driver uses FB aperture to access FB, driver get fb_start from 245 * MC_VM_FB_LOCATION_BASE (set by vbios) and calculate vram_start 246 * of this local device by adding an offset inside the XGMI hive. 247 * If driver uses GART table for VMID0 FB access, driver finds a hole in 248 * VMID0's virtual address space to place the SYSVM aperture inside 249 * which the first part is vram and the second part is gart (covering 250 * system ram). 251 */ 252 u64 vram_start; 253 u64 vram_end; 254 /* FB region , it's same as local vram region in single GPU, in XGMI 255 * configuration, this region covers all GPUs in the same hive , 256 * each GPU in the hive has the same view of this FB region . 257 * GPU0's vram starts at offset (0 * segment size) , 258 * GPU1 starts at offset (1 * segment size), etc. 259 */ 260 u64 fb_start; 261 u64 fb_end; 262 unsigned vram_width; 263 u64 real_vram_size; 264 int vram_mtrr; 265 u64 mc_mask; 266 const struct firmware *fw; /* MC firmware */ 267 uint32_t fw_version; 268 struct amdgpu_irq_src vm_fault; 269 uint32_t vram_type; 270 uint8_t vram_vendor; 271 uint32_t srbm_soft_reset; 272 bool prt_warning; 273 uint32_t sdpif_register; 274 /* apertures */ 275 u64 shared_aperture_start; 276 u64 shared_aperture_end; 277 u64 private_aperture_start; 278 u64 private_aperture_end; 279 /* protects concurrent invalidation */ 280 spinlock_t invalidate_lock; 281 bool translate_further; 282 struct kfd_vm_fault_info *vm_fault_info; 283 atomic_t vm_fault_info_updated; 284 285 struct amdgpu_gmc_fault fault_ring[AMDGPU_GMC_FAULT_RING_SIZE]; 286 struct { 287 uint64_t idx:AMDGPU_GMC_FAULT_RING_ORDER; 288 } fault_hash[AMDGPU_GMC_FAULT_HASH_SIZE]; 289 uint64_t last_fault:AMDGPU_GMC_FAULT_RING_ORDER; 290 291 bool tmz_enabled; 292 bool is_app_apu; 293 294 struct amdgpu_mem_partition_info *mem_partitions; 295 uint8_t num_mem_partitions; 296 const struct amdgpu_gmc_funcs *gmc_funcs; 297 enum amdgpu_memory_partition requested_nps_mode; 298 uint32_t supported_nps_modes; 299 uint32_t reset_flags; 300 301 struct amdgpu_xgmi xgmi; 302 struct amdgpu_irq_src ecc_irq; 303 int noretry; 304 305 uint32_t vmid0_page_table_block_size; 306 uint32_t vmid0_page_table_depth; 307 struct amdgpu_bo *pdb0_bo; 308 /* CPU kmapped address of pdb0*/ 309 void *ptr_pdb0; 310 311 /* MALL size */ 312 u64 mall_size; 313 uint32_t m_half_use; 314 315 /* number of UMC instances */ 316 int num_umc; 317 /* mode2 save restore */ 318 u64 VM_L2_CNTL; 319 u64 VM_L2_CNTL2; 320 u64 VM_DUMMY_PAGE_FAULT_CNTL; 321 u64 VM_DUMMY_PAGE_FAULT_ADDR_LO32; 322 u64 VM_DUMMY_PAGE_FAULT_ADDR_HI32; 323 u64 VM_L2_PROTECTION_FAULT_CNTL; 324 u64 VM_L2_PROTECTION_FAULT_CNTL2; 325 u64 VM_L2_PROTECTION_FAULT_MM_CNTL3; 326 u64 VM_L2_PROTECTION_FAULT_MM_CNTL4; 327 u64 VM_L2_PROTECTION_FAULT_ADDR_LO32; 328 u64 VM_L2_PROTECTION_FAULT_ADDR_HI32; 329 u64 VM_DEBUG; 330 u64 VM_L2_MM_GROUP_RT_CLASSES; 331 u64 VM_L2_BANK_SELECT_RESERVED_CID; 332 u64 VM_L2_BANK_SELECT_RESERVED_CID2; 333 u64 VM_L2_CACHE_PARITY_CNTL; 334 u64 VM_L2_IH_LOG_CNTL; 335 u64 VM_CONTEXT_CNTL[16]; 336 u64 VM_CONTEXT_PAGE_TABLE_BASE_ADDR_LO32[16]; 337 u64 VM_CONTEXT_PAGE_TABLE_BASE_ADDR_HI32[16]; 338 u64 VM_CONTEXT_PAGE_TABLE_START_ADDR_LO32[16]; 339 u64 VM_CONTEXT_PAGE_TABLE_START_ADDR_HI32[16]; 340 u64 VM_CONTEXT_PAGE_TABLE_END_ADDR_LO32[16]; 341 u64 VM_CONTEXT_PAGE_TABLE_END_ADDR_HI32[16]; 342 u64 MC_VM_MX_L1_TLB_CNTL; 343 344 u64 noretry_flags; 345 346 bool flush_tlb_needs_extra_type_0; 347 bool flush_tlb_needs_extra_type_2; 348 bool flush_pasid_uses_kiq; 349 }; 350 351 #define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (addr)) 352 #define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping((r), (vmid), (pasid)) 353 #define amdgpu_gmc_map_mtype(adev, flags) (adev)->gmc.gmc_funcs->map_mtype((adev),(flags)) 354 #define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) (adev)->gmc.gmc_funcs->get_vm_pde((adev), (level), (dst), (flags)) 355 #define amdgpu_gmc_get_vm_pte(adev, mapping, flags) (adev)->gmc.gmc_funcs->get_vm_pte((adev), (mapping), (flags)) 356 #define amdgpu_gmc_override_vm_pte_flags(adev, vm, addr, pte_flags) \ 357 (adev)->gmc.gmc_funcs->override_vm_pte_flags \ 358 ((adev), (vm), (addr), (pte_flags)) 359 #define amdgpu_gmc_get_vbios_fb_size(adev) (adev)->gmc.gmc_funcs->get_vbios_fb_size((adev)) 360 #define amdgpu_gmc_get_dcc_alignment(adev) ({ \ 361 typeof(adev) _adev = (adev); \ 362 _adev->gmc.gmc_funcs->get_dcc_alignment(_adev); \ 363 }) 364 365 /** 366 * amdgpu_gmc_vram_full_visible - Check if full VRAM is visible through the BAR 367 * 368 * @adev: amdgpu_device pointer 369 * 370 * Returns: 371 * True if full VRAM is visible through the BAR 372 */ 373 static inline bool amdgpu_gmc_vram_full_visible(struct amdgpu_gmc *gmc) 374 { 375 WARN_ON(gmc->real_vram_size < gmc->visible_vram_size); 376 377 return (gmc->real_vram_size == gmc->visible_vram_size); 378 } 379 380 /** 381 * amdgpu_gmc_sign_extend - sign extend the given gmc address 382 * 383 * @addr: address to extend 384 */ 385 static inline uint64_t amdgpu_gmc_sign_extend(uint64_t addr) 386 { 387 if (addr >= AMDGPU_GMC_HOLE_START) 388 addr |= AMDGPU_GMC_HOLE_END; 389 390 return addr; 391 } 392 393 int amdgpu_gmc_pdb0_alloc(struct amdgpu_device *adev); 394 void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level, 395 uint64_t *addr, uint64_t *flags); 396 int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr, 397 uint32_t gpu_page_idx, uint64_t addr, 398 uint64_t flags); 399 uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo); 400 uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo); 401 void amdgpu_gmc_sysvm_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc); 402 void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc, 403 u64 base); 404 void amdgpu_gmc_gart_location(struct amdgpu_device *adev, 405 struct amdgpu_gmc *mc, 406 enum amdgpu_gart_placement gart_placement); 407 void amdgpu_gmc_agp_location(struct amdgpu_device *adev, 408 struct amdgpu_gmc *mc); 409 void amdgpu_gmc_set_agp_default(struct amdgpu_device *adev, 410 struct amdgpu_gmc *mc); 411 bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, 412 struct amdgpu_ih_ring *ih, uint64_t addr, 413 uint16_t pasid, uint64_t timestamp); 414 void amdgpu_gmc_filter_faults_remove(struct amdgpu_device *adev, uint64_t addr, 415 uint16_t pasid); 416 int amdgpu_gmc_ras_sw_init(struct amdgpu_device *adev); 417 int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev); 418 void amdgpu_gmc_ras_fini(struct amdgpu_device *adev); 419 int amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_device *adev); 420 void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 421 uint32_t vmhub, uint32_t flush_type); 422 int amdgpu_gmc_flush_gpu_tlb_pasid(struct amdgpu_device *adev, uint16_t pasid, 423 uint32_t flush_type, bool all_hub, 424 uint32_t inst); 425 void amdgpu_gmc_fw_reg_write_reg_wait(struct amdgpu_device *adev, 426 uint32_t reg0, uint32_t reg1, 427 uint32_t ref, uint32_t mask, 428 uint32_t xcc_inst); 429 430 extern void amdgpu_gmc_tmz_set(struct amdgpu_device *adev); 431 extern void amdgpu_gmc_noretry_set(struct amdgpu_device *adev); 432 433 extern void 434 amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device *adev, int hub_type, 435 bool enable); 436 437 void amdgpu_gmc_get_vbios_allocations(struct amdgpu_device *adev); 438 439 void amdgpu_gmc_init_pdb0(struct amdgpu_device *adev); 440 uint64_t amdgpu_gmc_vram_mc2pa(struct amdgpu_device *adev, uint64_t mc_addr); 441 uint64_t amdgpu_gmc_vram_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo); 442 int amdgpu_gmc_vram_checking(struct amdgpu_device *adev); 443 int amdgpu_gmc_sysfs_init(struct amdgpu_device *adev); 444 void amdgpu_gmc_sysfs_fini(struct amdgpu_device *adev); 445 446 int amdgpu_gmc_get_nps_memranges(struct amdgpu_device *adev, 447 struct amdgpu_mem_partition_info *mem_ranges, 448 uint8_t *exp_ranges); 449 450 int amdgpu_gmc_request_memory_partition(struct amdgpu_device *adev, 451 int nps_mode); 452 void amdgpu_gmc_prepare_nps_mode_change(struct amdgpu_device *adev); 453 bool amdgpu_gmc_need_reset_on_init(struct amdgpu_device *adev); 454 455 #endif 456