1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 #ifndef __AMDGPU_GMC_H__ 27 #define __AMDGPU_GMC_H__ 28 29 #include <linux/types.h> 30 31 #include "amdgpu_irq.h" 32 #include "amdgpu_xgmi.h" 33 #include "amdgpu_ras.h" 34 35 /* VA hole for 48bit addresses on Vega10 */ 36 #define AMDGPU_GMC_HOLE_START 0x0000800000000000ULL 37 #define AMDGPU_GMC_HOLE_END 0xffff800000000000ULL 38 39 /* 40 * Hardware is programmed as if the hole doesn't exists with start and end 41 * address values. 42 * 43 * This mask is used to remove the upper 16bits of the VA and so come up with 44 * the linear addr value. 45 */ 46 #define AMDGPU_GMC_HOLE_MASK 0x0000ffffffffffffULL 47 48 /* 49 * Ring size as power of two for the log of recent faults. 50 */ 51 #define AMDGPU_GMC_FAULT_RING_ORDER 8 52 #define AMDGPU_GMC_FAULT_RING_SIZE (1 << AMDGPU_GMC_FAULT_RING_ORDER) 53 54 /* 55 * Hash size as power of two for the log of recent faults 56 */ 57 #define AMDGPU_GMC_FAULT_HASH_ORDER 8 58 #define AMDGPU_GMC_FAULT_HASH_SIZE (1 << AMDGPU_GMC_FAULT_HASH_ORDER) 59 60 /* 61 * Number of IH timestamp ticks until a fault is considered handled 62 */ 63 #define AMDGPU_GMC_FAULT_TIMEOUT 5000ULL 64 65 /* XNACK flags */ 66 #define AMDGPU_GMC_XNACK_FLAG_CHAIN BIT(0) 67 68 struct firmware; 69 70 enum amdgpu_memory_partition { 71 UNKNOWN_MEMORY_PARTITION_MODE = 0, 72 AMDGPU_NPS1_PARTITION_MODE = 1, 73 AMDGPU_NPS2_PARTITION_MODE = 2, 74 AMDGPU_NPS3_PARTITION_MODE = 3, 75 AMDGPU_NPS4_PARTITION_MODE = 4, 76 AMDGPU_NPS6_PARTITION_MODE = 6, 77 AMDGPU_NPS8_PARTITION_MODE = 8, 78 }; 79 80 #define AMDGPU_ALL_NPS_MASK \ 81 (BIT(AMDGPU_NPS1_PARTITION_MODE) | BIT(AMDGPU_NPS2_PARTITION_MODE) | \ 82 BIT(AMDGPU_NPS3_PARTITION_MODE) | BIT(AMDGPU_NPS4_PARTITION_MODE) | \ 83 BIT(AMDGPU_NPS6_PARTITION_MODE) | BIT(AMDGPU_NPS8_PARTITION_MODE)) 84 85 #define AMDGPU_GMC_INIT_RESET_NPS BIT(0) 86 87 /* 88 * GMC page fault information 89 */ 90 struct amdgpu_gmc_fault { 91 uint64_t timestamp:48; 92 uint64_t next:AMDGPU_GMC_FAULT_RING_ORDER; 93 atomic64_t key; 94 uint64_t timestamp_expiry:48; 95 }; 96 97 /* 98 * VMHUB structures, functions & helpers 99 */ 100 struct amdgpu_vmhub_funcs { 101 void (*print_l2_protection_fault_status)(struct amdgpu_device *adev, 102 uint32_t status); 103 uint32_t (*get_invalidate_req)(unsigned int vmid, uint32_t flush_type); 104 }; 105 106 struct amdgpu_vmhub { 107 uint32_t ctx0_ptb_addr_lo32; 108 uint32_t ctx0_ptb_addr_hi32; 109 uint32_t vm_inv_eng0_sem; 110 uint32_t vm_inv_eng0_req; 111 uint32_t vm_inv_eng0_ack; 112 uint32_t vm_context0_cntl; 113 uint32_t vm_l2_pro_fault_status; 114 uint32_t vm_l2_pro_fault_cntl; 115 116 /* 117 * store the register distances between two continuous context domain 118 * and invalidation engine. 119 */ 120 uint32_t ctx_distance; 121 uint32_t ctx_addr_distance; /* include LO32/HI32 */ 122 uint32_t eng_distance; 123 uint32_t eng_addr_distance; /* include LO32/HI32 */ 124 125 uint32_t vm_cntx_cntl; 126 uint32_t vm_cntx_cntl_vm_fault; 127 uint32_t vm_l2_bank_select_reserved_cid2; 128 129 uint32_t vm_contexts_disable; 130 131 bool sdma_invalidation_workaround; 132 133 const struct amdgpu_vmhub_funcs *vmhub_funcs; 134 }; 135 136 /* 137 * GPU MC structures, functions & helpers 138 */ 139 struct amdgpu_gmc_funcs { 140 /* flush the vm tlb via mmio */ 141 void (*flush_gpu_tlb)(struct amdgpu_device *adev, uint32_t vmid, 142 uint32_t vmhub, uint32_t flush_type); 143 /* flush the vm tlb via pasid */ 144 void (*flush_gpu_tlb_pasid)(struct amdgpu_device *adev, uint16_t pasid, 145 uint32_t flush_type, bool all_hub, 146 uint32_t inst); 147 /* flush the vm tlb via ring */ 148 uint64_t (*emit_flush_gpu_tlb)(struct amdgpu_ring *ring, unsigned vmid, 149 uint64_t pd_addr); 150 /* Change the VMID -> PASID mapping */ 151 void (*emit_pasid_mapping)(struct amdgpu_ring *ring, unsigned vmid, 152 unsigned pasid); 153 /* enable/disable PRT support */ 154 void (*set_prt)(struct amdgpu_device *adev, bool enable); 155 /* map mtype to hardware flags */ 156 uint64_t (*map_mtype)(struct amdgpu_device *adev, uint32_t flags); 157 /* get the pde for a given mc addr */ 158 void (*get_vm_pde)(struct amdgpu_device *adev, int level, 159 u64 *dst, u64 *flags); 160 /* get the pte flags to use for a BO VA mapping */ 161 void (*get_vm_pte)(struct amdgpu_device *adev, 162 struct amdgpu_bo_va_mapping *mapping, 163 uint64_t *flags); 164 /* override per-page pte flags */ 165 void (*override_vm_pte_flags)(struct amdgpu_device *dev, 166 struct amdgpu_vm *vm, 167 uint64_t addr, uint64_t *flags); 168 /* get the amount of memory used by the vbios for pre-OS console */ 169 unsigned int (*get_vbios_fb_size)(struct amdgpu_device *adev); 170 /* get the DCC buffer alignment */ 171 unsigned int (*get_dcc_alignment)(struct amdgpu_device *adev); 172 173 enum amdgpu_memory_partition (*query_mem_partition_mode)( 174 struct amdgpu_device *adev); 175 /* Request NPS mode */ 176 int (*request_mem_partition_mode)(struct amdgpu_device *adev, 177 int nps_mode); 178 bool (*need_reset_on_init)(struct amdgpu_device *adev); 179 }; 180 181 struct amdgpu_mem_partition_info { 182 union { 183 struct { 184 uint32_t fpfn; 185 uint32_t lpfn; 186 } range; 187 struct { 188 int node; 189 } numa; 190 }; 191 uint64_t size; 192 }; 193 194 #define INVALID_PFN -1 195 196 struct amdgpu_gmc_memrange { 197 uint64_t base_address; 198 uint64_t limit_address; 199 uint32_t flags; 200 int nid_mask; 201 }; 202 203 enum amdgpu_gart_placement { 204 AMDGPU_GART_PLACEMENT_BEST_FIT = 0, 205 AMDGPU_GART_PLACEMENT_HIGH, 206 AMDGPU_GART_PLACEMENT_LOW, 207 }; 208 209 struct amdgpu_gmc { 210 /* FB's physical address in MMIO space (for CPU to 211 * map FB). This is different compared to the agp/ 212 * gart/vram_start/end field as the later is from 213 * GPU's view and aper_base is from CPU's view. 214 */ 215 resource_size_t aper_size; 216 resource_size_t aper_base; 217 /* for some chips with <= 32MB we need to lie 218 * about vram size near mc fb location */ 219 u64 mc_vram_size; 220 u64 visible_vram_size; 221 /* AGP aperture start and end in MC address space 222 * Driver find a hole in the MC address space 223 * to place AGP by setting MC_VM_AGP_BOT/TOP registers 224 * Under VMID0, logical address == MC address. AGP 225 * aperture maps to physical bus or IOVA addressed. 226 * AGP aperture is used to simulate FB in ZFB case. 227 * AGP aperture is also used for page table in system 228 * memory (mainly for APU). 229 * 230 */ 231 u64 agp_size; 232 u64 agp_start; 233 u64 agp_end; 234 /* GART aperture start and end in MC address space 235 * Driver find a hole in the MC address space 236 * to place GART by setting VM_CONTEXT0_PAGE_TABLE_START/END_ADDR 237 * registers 238 * Under VMID0, logical address inside GART aperture will 239 * be translated through gpuvm gart page table to access 240 * paged system memory 241 */ 242 u64 gart_size; 243 u64 gart_start; 244 u64 gart_end; 245 /* Frame buffer aperture of this GPU device. Different from 246 * fb_start (see below), this only covers the local GPU device. 247 * If driver uses FB aperture to access FB, driver get fb_start from 248 * MC_VM_FB_LOCATION_BASE (set by vbios) and calculate vram_start 249 * of this local device by adding an offset inside the XGMI hive. 250 * If driver uses GART table for VMID0 FB access, driver finds a hole in 251 * VMID0's virtual address space to place the SYSVM aperture inside 252 * which the first part is vram and the second part is gart (covering 253 * system ram). 254 */ 255 u64 vram_start; 256 u64 vram_end; 257 /* FB region , it's same as local vram region in single GPU, in XGMI 258 * configuration, this region covers all GPUs in the same hive , 259 * each GPU in the hive has the same view of this FB region . 260 * GPU0's vram starts at offset (0 * segment size) , 261 * GPU1 starts at offset (1 * segment size), etc. 262 */ 263 u64 fb_start; 264 u64 fb_end; 265 unsigned vram_width; 266 u64 real_vram_size; 267 int vram_mtrr; 268 u64 mc_mask; 269 const struct firmware *fw; /* MC firmware */ 270 uint32_t fw_version; 271 struct amdgpu_irq_src vm_fault; 272 uint32_t vram_type; 273 uint8_t vram_vendor; 274 uint32_t srbm_soft_reset; 275 bool prt_warning; 276 uint32_t sdpif_register; 277 /* apertures */ 278 u64 shared_aperture_start; 279 u64 shared_aperture_end; 280 u64 private_aperture_start; 281 u64 private_aperture_end; 282 /* protects concurrent invalidation */ 283 spinlock_t invalidate_lock; 284 bool translate_further; 285 struct kfd_vm_fault_info *vm_fault_info; 286 atomic_t vm_fault_info_updated; 287 288 struct amdgpu_gmc_fault fault_ring[AMDGPU_GMC_FAULT_RING_SIZE]; 289 struct { 290 uint64_t idx:AMDGPU_GMC_FAULT_RING_ORDER; 291 } fault_hash[AMDGPU_GMC_FAULT_HASH_SIZE]; 292 uint64_t last_fault:AMDGPU_GMC_FAULT_RING_ORDER; 293 294 bool tmz_enabled; 295 bool is_app_apu; 296 297 struct amdgpu_mem_partition_info *mem_partitions; 298 uint8_t num_mem_partitions; 299 const struct amdgpu_gmc_funcs *gmc_funcs; 300 enum amdgpu_memory_partition requested_nps_mode; 301 uint32_t supported_nps_modes; 302 uint32_t reset_flags; 303 304 struct amdgpu_xgmi xgmi; 305 struct amdgpu_irq_src ecc_irq; 306 int noretry; 307 uint32_t xnack_flags; 308 309 uint32_t vmid0_page_table_block_size; 310 uint32_t vmid0_page_table_depth; 311 struct amdgpu_bo *pdb0_bo; 312 /* CPU kmapped address of pdb0*/ 313 void *ptr_pdb0; 314 315 /* MALL size */ 316 u64 mall_size; 317 uint32_t m_half_use; 318 319 /* number of UMC instances */ 320 int num_umc; 321 /* mode2 save restore */ 322 u64 VM_L2_CNTL; 323 u64 VM_L2_CNTL2; 324 u64 VM_DUMMY_PAGE_FAULT_CNTL; 325 u64 VM_DUMMY_PAGE_FAULT_ADDR_LO32; 326 u64 VM_DUMMY_PAGE_FAULT_ADDR_HI32; 327 u64 VM_L2_PROTECTION_FAULT_CNTL; 328 u64 VM_L2_PROTECTION_FAULT_CNTL2; 329 u64 VM_L2_PROTECTION_FAULT_MM_CNTL3; 330 u64 VM_L2_PROTECTION_FAULT_MM_CNTL4; 331 u64 VM_L2_PROTECTION_FAULT_ADDR_LO32; 332 u64 VM_L2_PROTECTION_FAULT_ADDR_HI32; 333 u64 VM_DEBUG; 334 u64 VM_L2_MM_GROUP_RT_CLASSES; 335 u64 VM_L2_BANK_SELECT_RESERVED_CID; 336 u64 VM_L2_BANK_SELECT_RESERVED_CID2; 337 u64 VM_L2_CACHE_PARITY_CNTL; 338 u64 VM_L2_IH_LOG_CNTL; 339 u64 VM_CONTEXT_CNTL[16]; 340 u64 VM_CONTEXT_PAGE_TABLE_BASE_ADDR_LO32[16]; 341 u64 VM_CONTEXT_PAGE_TABLE_BASE_ADDR_HI32[16]; 342 u64 VM_CONTEXT_PAGE_TABLE_START_ADDR_LO32[16]; 343 u64 VM_CONTEXT_PAGE_TABLE_START_ADDR_HI32[16]; 344 u64 VM_CONTEXT_PAGE_TABLE_END_ADDR_LO32[16]; 345 u64 VM_CONTEXT_PAGE_TABLE_END_ADDR_HI32[16]; 346 u64 MC_VM_MX_L1_TLB_CNTL; 347 348 u64 noretry_flags; 349 350 bool flush_tlb_needs_extra_type_0; 351 bool flush_tlb_needs_extra_type_2; 352 bool flush_pasid_uses_kiq; 353 }; 354 355 #define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (addr)) 356 #define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping((r), (vmid), (pasid)) 357 #define amdgpu_gmc_map_mtype(adev, flags) (adev)->gmc.gmc_funcs->map_mtype((adev),(flags)) 358 #define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) (adev)->gmc.gmc_funcs->get_vm_pde((adev), (level), (dst), (flags)) 359 #define amdgpu_gmc_get_vm_pte(adev, mapping, flags) (adev)->gmc.gmc_funcs->get_vm_pte((adev), (mapping), (flags)) 360 #define amdgpu_gmc_override_vm_pte_flags(adev, vm, addr, pte_flags) \ 361 (adev)->gmc.gmc_funcs->override_vm_pte_flags \ 362 ((adev), (vm), (addr), (pte_flags)) 363 #define amdgpu_gmc_get_vbios_fb_size(adev) (adev)->gmc.gmc_funcs->get_vbios_fb_size((adev)) 364 #define amdgpu_gmc_get_dcc_alignment(adev) ({ \ 365 typeof(adev) _adev = (adev); \ 366 _adev->gmc.gmc_funcs->get_dcc_alignment(_adev); \ 367 }) 368 369 /** 370 * amdgpu_gmc_vram_full_visible - Check if full VRAM is visible through the BAR 371 * 372 * @adev: amdgpu_device pointer 373 * 374 * Returns: 375 * True if full VRAM is visible through the BAR 376 */ 377 static inline bool amdgpu_gmc_vram_full_visible(struct amdgpu_gmc *gmc) 378 { 379 WARN_ON(gmc->real_vram_size < gmc->visible_vram_size); 380 381 return (gmc->real_vram_size == gmc->visible_vram_size); 382 } 383 384 /** 385 * amdgpu_gmc_sign_extend - sign extend the given gmc address 386 * 387 * @addr: address to extend 388 */ 389 static inline uint64_t amdgpu_gmc_sign_extend(uint64_t addr) 390 { 391 if (addr >= AMDGPU_GMC_HOLE_START) 392 addr |= AMDGPU_GMC_HOLE_END; 393 394 return addr; 395 } 396 397 int amdgpu_gmc_pdb0_alloc(struct amdgpu_device *adev); 398 void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level, 399 uint64_t *addr, uint64_t *flags); 400 int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr, 401 uint32_t gpu_page_idx, uint64_t addr, 402 uint64_t flags); 403 uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo); 404 uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo); 405 void amdgpu_gmc_sysvm_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc); 406 void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc, 407 u64 base); 408 void amdgpu_gmc_gart_location(struct amdgpu_device *adev, 409 struct amdgpu_gmc *mc, 410 enum amdgpu_gart_placement gart_placement); 411 void amdgpu_gmc_agp_location(struct amdgpu_device *adev, 412 struct amdgpu_gmc *mc); 413 void amdgpu_gmc_set_agp_default(struct amdgpu_device *adev, 414 struct amdgpu_gmc *mc); 415 bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, 416 struct amdgpu_ih_ring *ih, uint64_t addr, 417 uint16_t pasid, uint64_t timestamp); 418 void amdgpu_gmc_filter_faults_remove(struct amdgpu_device *adev, uint64_t addr, 419 uint16_t pasid); 420 int amdgpu_gmc_ras_sw_init(struct amdgpu_device *adev); 421 int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev); 422 void amdgpu_gmc_ras_fini(struct amdgpu_device *adev); 423 int amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_device *adev); 424 void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 425 uint32_t vmhub, uint32_t flush_type); 426 int amdgpu_gmc_flush_gpu_tlb_pasid(struct amdgpu_device *adev, uint16_t pasid, 427 uint32_t flush_type, bool all_hub, 428 uint32_t inst); 429 void amdgpu_gmc_fw_reg_write_reg_wait(struct amdgpu_device *adev, 430 uint32_t reg0, uint32_t reg1, 431 uint32_t ref, uint32_t mask, 432 uint32_t xcc_inst); 433 434 extern void amdgpu_gmc_tmz_set(struct amdgpu_device *adev); 435 extern void amdgpu_gmc_noretry_set(struct amdgpu_device *adev); 436 437 extern void 438 amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device *adev, int hub_type, 439 bool enable); 440 441 void amdgpu_gmc_get_vbios_allocations(struct amdgpu_device *adev); 442 443 void amdgpu_gmc_init_pdb0(struct amdgpu_device *adev); 444 uint64_t amdgpu_gmc_vram_mc2pa(struct amdgpu_device *adev, uint64_t mc_addr); 445 uint64_t amdgpu_gmc_vram_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo); 446 int amdgpu_gmc_vram_checking(struct amdgpu_device *adev); 447 int amdgpu_gmc_sysfs_init(struct amdgpu_device *adev); 448 void amdgpu_gmc_sysfs_fini(struct amdgpu_device *adev); 449 450 int amdgpu_gmc_get_nps_memranges(struct amdgpu_device *adev, 451 struct amdgpu_mem_partition_info *mem_ranges, 452 uint8_t *exp_ranges); 453 454 int amdgpu_gmc_request_memory_partition(struct amdgpu_device *adev, 455 int nps_mode); 456 void amdgpu_gmc_prepare_nps_mode_change(struct amdgpu_device *adev); 457 bool amdgpu_gmc_need_reset_on_init(struct amdgpu_device *adev); 458 459 #endif 460