1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 #ifndef __AMDGPU_GMC_H__ 27 #define __AMDGPU_GMC_H__ 28 29 #include <linux/types.h> 30 31 #include "amdgpu_irq.h" 32 #include "amdgpu_ras.h" 33 34 /* VA hole for 48bit addresses on Vega10 */ 35 #define AMDGPU_GMC_HOLE_START 0x0000800000000000ULL 36 #define AMDGPU_GMC_HOLE_END 0xffff800000000000ULL 37 38 /* 39 * Hardware is programmed as if the hole doesn't exists with start and end 40 * address values. 41 * 42 * This mask is used to remove the upper 16bits of the VA and so come up with 43 * the linear addr value. 44 */ 45 #define AMDGPU_GMC_HOLE_MASK 0x0000ffffffffffffULL 46 47 /* 48 * Ring size as power of two for the log of recent faults. 49 */ 50 #define AMDGPU_GMC_FAULT_RING_ORDER 8 51 #define AMDGPU_GMC_FAULT_RING_SIZE (1 << AMDGPU_GMC_FAULT_RING_ORDER) 52 53 /* 54 * Hash size as power of two for the log of recent faults 55 */ 56 #define AMDGPU_GMC_FAULT_HASH_ORDER 8 57 #define AMDGPU_GMC_FAULT_HASH_SIZE (1 << AMDGPU_GMC_FAULT_HASH_ORDER) 58 59 /* 60 * Number of IH timestamp ticks until a fault is considered handled 61 */ 62 #define AMDGPU_GMC_FAULT_TIMEOUT 5000ULL 63 64 struct firmware; 65 66 enum amdgpu_memory_partition { 67 UNKNOWN_MEMORY_PARTITION_MODE = 0, 68 AMDGPU_NPS1_PARTITION_MODE = 1, 69 AMDGPU_NPS2_PARTITION_MODE = 2, 70 AMDGPU_NPS3_PARTITION_MODE = 3, 71 AMDGPU_NPS4_PARTITION_MODE = 4, 72 AMDGPU_NPS6_PARTITION_MODE = 6, 73 AMDGPU_NPS8_PARTITION_MODE = 8, 74 }; 75 76 #define AMDGPU_ALL_NPS_MASK \ 77 (BIT(AMDGPU_NPS1_PARTITION_MODE) | BIT(AMDGPU_NPS2_PARTITION_MODE) | \ 78 BIT(AMDGPU_NPS3_PARTITION_MODE) | BIT(AMDGPU_NPS4_PARTITION_MODE) | \ 79 BIT(AMDGPU_NPS6_PARTITION_MODE) | BIT(AMDGPU_NPS8_PARTITION_MODE)) 80 81 #define AMDGPU_GMC_INIT_RESET_NPS BIT(0) 82 83 /* 84 * GMC page fault information 85 */ 86 struct amdgpu_gmc_fault { 87 uint64_t timestamp:48; 88 uint64_t next:AMDGPU_GMC_FAULT_RING_ORDER; 89 atomic64_t key; 90 uint64_t timestamp_expiry:48; 91 }; 92 93 /* 94 * VMHUB structures, functions & helpers 95 */ 96 struct amdgpu_vmhub_funcs { 97 void (*print_l2_protection_fault_status)(struct amdgpu_device *adev, 98 uint32_t status); 99 uint32_t (*get_invalidate_req)(unsigned int vmid, uint32_t flush_type); 100 }; 101 102 struct amdgpu_vmhub { 103 uint32_t ctx0_ptb_addr_lo32; 104 uint32_t ctx0_ptb_addr_hi32; 105 uint32_t vm_inv_eng0_sem; 106 uint32_t vm_inv_eng0_req; 107 uint32_t vm_inv_eng0_ack; 108 uint32_t vm_context0_cntl; 109 uint32_t vm_l2_pro_fault_status; 110 uint32_t vm_l2_pro_fault_cntl; 111 112 /* 113 * store the register distances between two continuous context domain 114 * and invalidation engine. 115 */ 116 uint32_t ctx_distance; 117 uint32_t ctx_addr_distance; /* include LO32/HI32 */ 118 uint32_t eng_distance; 119 uint32_t eng_addr_distance; /* include LO32/HI32 */ 120 121 uint32_t vm_cntx_cntl; 122 uint32_t vm_cntx_cntl_vm_fault; 123 uint32_t vm_l2_bank_select_reserved_cid2; 124 125 uint32_t vm_contexts_disable; 126 127 bool sdma_invalidation_workaround; 128 129 const struct amdgpu_vmhub_funcs *vmhub_funcs; 130 }; 131 132 /* 133 * GPU MC structures, functions & helpers 134 */ 135 struct amdgpu_gmc_funcs { 136 /* flush the vm tlb via mmio */ 137 void (*flush_gpu_tlb)(struct amdgpu_device *adev, uint32_t vmid, 138 uint32_t vmhub, uint32_t flush_type); 139 /* flush the vm tlb via pasid */ 140 void (*flush_gpu_tlb_pasid)(struct amdgpu_device *adev, uint16_t pasid, 141 uint32_t flush_type, bool all_hub, 142 uint32_t inst); 143 /* flush the vm tlb via ring */ 144 uint64_t (*emit_flush_gpu_tlb)(struct amdgpu_ring *ring, unsigned vmid, 145 uint64_t pd_addr); 146 /* Change the VMID -> PASID mapping */ 147 void (*emit_pasid_mapping)(struct amdgpu_ring *ring, unsigned vmid, 148 unsigned pasid); 149 /* enable/disable PRT support */ 150 void (*set_prt)(struct amdgpu_device *adev, bool enable); 151 /* map mtype to hardware flags */ 152 uint64_t (*map_mtype)(struct amdgpu_device *adev, uint32_t flags); 153 /* get the pde for a given mc addr */ 154 void (*get_vm_pde)(struct amdgpu_device *adev, int level, 155 u64 *dst, u64 *flags); 156 /* get the pte flags to use for a BO VA mapping */ 157 void (*get_vm_pte)(struct amdgpu_device *adev, 158 struct amdgpu_bo_va_mapping *mapping, 159 uint64_t *flags); 160 /* override per-page pte flags */ 161 void (*override_vm_pte_flags)(struct amdgpu_device *dev, 162 struct amdgpu_vm *vm, 163 uint64_t addr, uint64_t *flags); 164 /* get the amount of memory used by the vbios for pre-OS console */ 165 unsigned int (*get_vbios_fb_size)(struct amdgpu_device *adev); 166 /* get the DCC buffer alignment */ 167 unsigned int (*get_dcc_alignment)(struct amdgpu_device *adev); 168 169 enum amdgpu_memory_partition (*query_mem_partition_mode)( 170 struct amdgpu_device *adev); 171 /* Request NPS mode */ 172 int (*request_mem_partition_mode)(struct amdgpu_device *adev, 173 int nps_mode); 174 bool (*need_reset_on_init)(struct amdgpu_device *adev); 175 }; 176 177 struct amdgpu_xgmi_ras { 178 struct amdgpu_ras_block_object ras_block; 179 }; 180 181 struct amdgpu_xgmi { 182 /* from psp */ 183 u64 node_id; 184 u64 hive_id; 185 /* fixed per family */ 186 u64 node_segment_size; 187 /* physical node (0-3) */ 188 unsigned physical_node_id; 189 /* number of nodes (0-4) */ 190 unsigned num_physical_nodes; 191 /* gpu list in the same hive */ 192 struct list_head head; 193 bool supported; 194 struct ras_common_if *ras_if; 195 bool connected_to_cpu; 196 struct amdgpu_xgmi_ras *ras; 197 }; 198 199 struct amdgpu_mem_partition_info { 200 union { 201 struct { 202 uint32_t fpfn; 203 uint32_t lpfn; 204 } range; 205 struct { 206 int node; 207 } numa; 208 }; 209 uint64_t size; 210 }; 211 212 #define INVALID_PFN -1 213 214 struct amdgpu_gmc_memrange { 215 uint64_t base_address; 216 uint64_t limit_address; 217 uint32_t flags; 218 int nid_mask; 219 }; 220 221 enum amdgpu_gart_placement { 222 AMDGPU_GART_PLACEMENT_BEST_FIT = 0, 223 AMDGPU_GART_PLACEMENT_HIGH, 224 AMDGPU_GART_PLACEMENT_LOW, 225 }; 226 227 struct amdgpu_gmc { 228 /* FB's physical address in MMIO space (for CPU to 229 * map FB). This is different compared to the agp/ 230 * gart/vram_start/end field as the later is from 231 * GPU's view and aper_base is from CPU's view. 232 */ 233 resource_size_t aper_size; 234 resource_size_t aper_base; 235 /* for some chips with <= 32MB we need to lie 236 * about vram size near mc fb location */ 237 u64 mc_vram_size; 238 u64 visible_vram_size; 239 /* AGP aperture start and end in MC address space 240 * Driver find a hole in the MC address space 241 * to place AGP by setting MC_VM_AGP_BOT/TOP registers 242 * Under VMID0, logical address == MC address. AGP 243 * aperture maps to physical bus or IOVA addressed. 244 * AGP aperture is used to simulate FB in ZFB case. 245 * AGP aperture is also used for page table in system 246 * memory (mainly for APU). 247 * 248 */ 249 u64 agp_size; 250 u64 agp_start; 251 u64 agp_end; 252 /* GART aperture start and end in MC address space 253 * Driver find a hole in the MC address space 254 * to place GART by setting VM_CONTEXT0_PAGE_TABLE_START/END_ADDR 255 * registers 256 * Under VMID0, logical address inside GART aperture will 257 * be translated through gpuvm gart page table to access 258 * paged system memory 259 */ 260 u64 gart_size; 261 u64 gart_start; 262 u64 gart_end; 263 /* Frame buffer aperture of this GPU device. Different from 264 * fb_start (see below), this only covers the local GPU device. 265 * If driver uses FB aperture to access FB, driver get fb_start from 266 * MC_VM_FB_LOCATION_BASE (set by vbios) and calculate vram_start 267 * of this local device by adding an offset inside the XGMI hive. 268 * If driver uses GART table for VMID0 FB access, driver finds a hole in 269 * VMID0's virtual address space to place the SYSVM aperture inside 270 * which the first part is vram and the second part is gart (covering 271 * system ram). 272 */ 273 u64 vram_start; 274 u64 vram_end; 275 /* FB region , it's same as local vram region in single GPU, in XGMI 276 * configuration, this region covers all GPUs in the same hive , 277 * each GPU in the hive has the same view of this FB region . 278 * GPU0's vram starts at offset (0 * segment size) , 279 * GPU1 starts at offset (1 * segment size), etc. 280 */ 281 u64 fb_start; 282 u64 fb_end; 283 unsigned vram_width; 284 u64 real_vram_size; 285 int vram_mtrr; 286 u64 mc_mask; 287 const struct firmware *fw; /* MC firmware */ 288 uint32_t fw_version; 289 struct amdgpu_irq_src vm_fault; 290 uint32_t vram_type; 291 uint8_t vram_vendor; 292 uint32_t srbm_soft_reset; 293 bool prt_warning; 294 uint32_t sdpif_register; 295 /* apertures */ 296 u64 shared_aperture_start; 297 u64 shared_aperture_end; 298 u64 private_aperture_start; 299 u64 private_aperture_end; 300 /* protects concurrent invalidation */ 301 spinlock_t invalidate_lock; 302 bool translate_further; 303 struct kfd_vm_fault_info *vm_fault_info; 304 atomic_t vm_fault_info_updated; 305 306 struct amdgpu_gmc_fault fault_ring[AMDGPU_GMC_FAULT_RING_SIZE]; 307 struct { 308 uint64_t idx:AMDGPU_GMC_FAULT_RING_ORDER; 309 } fault_hash[AMDGPU_GMC_FAULT_HASH_SIZE]; 310 uint64_t last_fault:AMDGPU_GMC_FAULT_RING_ORDER; 311 312 bool tmz_enabled; 313 bool is_app_apu; 314 315 struct amdgpu_mem_partition_info *mem_partitions; 316 uint8_t num_mem_partitions; 317 const struct amdgpu_gmc_funcs *gmc_funcs; 318 enum amdgpu_memory_partition requested_nps_mode; 319 uint32_t supported_nps_modes; 320 uint32_t reset_flags; 321 322 struct amdgpu_xgmi xgmi; 323 struct amdgpu_irq_src ecc_irq; 324 int noretry; 325 326 uint32_t vmid0_page_table_block_size; 327 uint32_t vmid0_page_table_depth; 328 struct amdgpu_bo *pdb0_bo; 329 /* CPU kmapped address of pdb0*/ 330 void *ptr_pdb0; 331 332 /* MALL size */ 333 u64 mall_size; 334 uint32_t m_half_use; 335 336 /* number of UMC instances */ 337 int num_umc; 338 /* mode2 save restore */ 339 u64 VM_L2_CNTL; 340 u64 VM_L2_CNTL2; 341 u64 VM_DUMMY_PAGE_FAULT_CNTL; 342 u64 VM_DUMMY_PAGE_FAULT_ADDR_LO32; 343 u64 VM_DUMMY_PAGE_FAULT_ADDR_HI32; 344 u64 VM_L2_PROTECTION_FAULT_CNTL; 345 u64 VM_L2_PROTECTION_FAULT_CNTL2; 346 u64 VM_L2_PROTECTION_FAULT_MM_CNTL3; 347 u64 VM_L2_PROTECTION_FAULT_MM_CNTL4; 348 u64 VM_L2_PROTECTION_FAULT_ADDR_LO32; 349 u64 VM_L2_PROTECTION_FAULT_ADDR_HI32; 350 u64 VM_DEBUG; 351 u64 VM_L2_MM_GROUP_RT_CLASSES; 352 u64 VM_L2_BANK_SELECT_RESERVED_CID; 353 u64 VM_L2_BANK_SELECT_RESERVED_CID2; 354 u64 VM_L2_CACHE_PARITY_CNTL; 355 u64 VM_L2_IH_LOG_CNTL; 356 u64 VM_CONTEXT_CNTL[16]; 357 u64 VM_CONTEXT_PAGE_TABLE_BASE_ADDR_LO32[16]; 358 u64 VM_CONTEXT_PAGE_TABLE_BASE_ADDR_HI32[16]; 359 u64 VM_CONTEXT_PAGE_TABLE_START_ADDR_LO32[16]; 360 u64 VM_CONTEXT_PAGE_TABLE_START_ADDR_HI32[16]; 361 u64 VM_CONTEXT_PAGE_TABLE_END_ADDR_LO32[16]; 362 u64 VM_CONTEXT_PAGE_TABLE_END_ADDR_HI32[16]; 363 u64 MC_VM_MX_L1_TLB_CNTL; 364 365 u64 noretry_flags; 366 367 bool flush_tlb_needs_extra_type_0; 368 bool flush_tlb_needs_extra_type_2; 369 bool flush_pasid_uses_kiq; 370 }; 371 372 #define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (addr)) 373 #define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping((r), (vmid), (pasid)) 374 #define amdgpu_gmc_map_mtype(adev, flags) (adev)->gmc.gmc_funcs->map_mtype((adev),(flags)) 375 #define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) (adev)->gmc.gmc_funcs->get_vm_pde((adev), (level), (dst), (flags)) 376 #define amdgpu_gmc_get_vm_pte(adev, mapping, flags) (adev)->gmc.gmc_funcs->get_vm_pte((adev), (mapping), (flags)) 377 #define amdgpu_gmc_override_vm_pte_flags(adev, vm, addr, pte_flags) \ 378 (adev)->gmc.gmc_funcs->override_vm_pte_flags \ 379 ((adev), (vm), (addr), (pte_flags)) 380 #define amdgpu_gmc_get_vbios_fb_size(adev) (adev)->gmc.gmc_funcs->get_vbios_fb_size((adev)) 381 #define amdgpu_gmc_get_dcc_alignment(adev) ({ \ 382 typeof(adev) _adev = (adev); \ 383 _adev->gmc.gmc_funcs->get_dcc_alignment(_adev); \ 384 }) 385 386 /** 387 * amdgpu_gmc_vram_full_visible - Check if full VRAM is visible through the BAR 388 * 389 * @adev: amdgpu_device pointer 390 * 391 * Returns: 392 * True if full VRAM is visible through the BAR 393 */ 394 static inline bool amdgpu_gmc_vram_full_visible(struct amdgpu_gmc *gmc) 395 { 396 WARN_ON(gmc->real_vram_size < gmc->visible_vram_size); 397 398 return (gmc->real_vram_size == gmc->visible_vram_size); 399 } 400 401 /** 402 * amdgpu_gmc_sign_extend - sign extend the given gmc address 403 * 404 * @addr: address to extend 405 */ 406 static inline uint64_t amdgpu_gmc_sign_extend(uint64_t addr) 407 { 408 if (addr >= AMDGPU_GMC_HOLE_START) 409 addr |= AMDGPU_GMC_HOLE_END; 410 411 return addr; 412 } 413 414 int amdgpu_gmc_pdb0_alloc(struct amdgpu_device *adev); 415 void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level, 416 uint64_t *addr, uint64_t *flags); 417 int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr, 418 uint32_t gpu_page_idx, uint64_t addr, 419 uint64_t flags); 420 uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo); 421 uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo); 422 void amdgpu_gmc_sysvm_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc); 423 void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc, 424 u64 base); 425 void amdgpu_gmc_gart_location(struct amdgpu_device *adev, 426 struct amdgpu_gmc *mc, 427 enum amdgpu_gart_placement gart_placement); 428 void amdgpu_gmc_agp_location(struct amdgpu_device *adev, 429 struct amdgpu_gmc *mc); 430 void amdgpu_gmc_set_agp_default(struct amdgpu_device *adev, 431 struct amdgpu_gmc *mc); 432 bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, 433 struct amdgpu_ih_ring *ih, uint64_t addr, 434 uint16_t pasid, uint64_t timestamp); 435 void amdgpu_gmc_filter_faults_remove(struct amdgpu_device *adev, uint64_t addr, 436 uint16_t pasid); 437 int amdgpu_gmc_ras_sw_init(struct amdgpu_device *adev); 438 int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev); 439 void amdgpu_gmc_ras_fini(struct amdgpu_device *adev); 440 int amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_device *adev); 441 void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 442 uint32_t vmhub, uint32_t flush_type); 443 int amdgpu_gmc_flush_gpu_tlb_pasid(struct amdgpu_device *adev, uint16_t pasid, 444 uint32_t flush_type, bool all_hub, 445 uint32_t inst); 446 void amdgpu_gmc_fw_reg_write_reg_wait(struct amdgpu_device *adev, 447 uint32_t reg0, uint32_t reg1, 448 uint32_t ref, uint32_t mask, 449 uint32_t xcc_inst); 450 451 extern void amdgpu_gmc_tmz_set(struct amdgpu_device *adev); 452 extern void amdgpu_gmc_noretry_set(struct amdgpu_device *adev); 453 454 extern void 455 amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device *adev, int hub_type, 456 bool enable); 457 458 void amdgpu_gmc_get_vbios_allocations(struct amdgpu_device *adev); 459 460 void amdgpu_gmc_init_pdb0(struct amdgpu_device *adev); 461 uint64_t amdgpu_gmc_vram_mc2pa(struct amdgpu_device *adev, uint64_t mc_addr); 462 uint64_t amdgpu_gmc_vram_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo); 463 int amdgpu_gmc_vram_checking(struct amdgpu_device *adev); 464 int amdgpu_gmc_sysfs_init(struct amdgpu_device *adev); 465 void amdgpu_gmc_sysfs_fini(struct amdgpu_device *adev); 466 467 int amdgpu_gmc_get_nps_memranges(struct amdgpu_device *adev, 468 struct amdgpu_mem_partition_info *mem_ranges, 469 uint8_t *exp_ranges); 470 471 int amdgpu_gmc_request_memory_partition(struct amdgpu_device *adev, 472 int nps_mode); 473 void amdgpu_gmc_prepare_nps_mode_change(struct amdgpu_device *adev); 474 bool amdgpu_gmc_need_reset_on_init(struct amdgpu_device *adev); 475 476 #endif 477