1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 #ifndef __AMDGPU_GMC_H__ 27 #define __AMDGPU_GMC_H__ 28 29 #include <linux/types.h> 30 31 #include "amdgpu_irq.h" 32 #include "amdgpu_xgmi.h" 33 #include "amdgpu_ras.h" 34 35 /* VA hole for 48bit and 57bit addresses */ 36 #define AMDGPU_GMC_HOLE_START (adev->vm_manager.max_level == 4 ?\ 37 0x0100000000000000ULL : 0x0000800000000000ULL) 38 #define AMDGPU_GMC_HOLE_END (adev->vm_manager.max_level == 4 ?\ 39 0xff00000000000000ULL : 0xffff800000000000ULL) 40 41 /* 42 * Hardware is programmed as if the hole doesn't exists with start and end 43 * address values. 44 * 45 * This mask is used to remove the upper 16bits of the VA and so come up with 46 * the linear addr value. 47 */ 48 #define AMDGPU_GMC_HOLE_MASK (adev->vm_manager.max_level == 4 ?\ 49 0x01ffffffffffffffULL : 0x0000ffffffffffffULL) 50 51 /* 52 * Ring size as power of two for the log of recent faults. 53 */ 54 #define AMDGPU_GMC_FAULT_RING_ORDER 8 55 #define AMDGPU_GMC_FAULT_RING_SIZE (1 << AMDGPU_GMC_FAULT_RING_ORDER) 56 57 /* 58 * Hash size as power of two for the log of recent faults 59 */ 60 #define AMDGPU_GMC_FAULT_HASH_ORDER 8 61 #define AMDGPU_GMC_FAULT_HASH_SIZE (1 << AMDGPU_GMC_FAULT_HASH_ORDER) 62 63 /* 64 * Number of IH timestamp ticks until a fault is considered handled 65 */ 66 #define AMDGPU_GMC_FAULT_TIMEOUT 5000ULL 67 68 /* XNACK flags */ 69 #define AMDGPU_GMC_XNACK_FLAG_CHAIN BIT(0) 70 71 struct firmware; 72 73 enum amdgpu_memory_partition { 74 UNKNOWN_MEMORY_PARTITION_MODE = 0, 75 AMDGPU_NPS1_PARTITION_MODE = 1, 76 AMDGPU_NPS2_PARTITION_MODE = 2, 77 AMDGPU_NPS3_PARTITION_MODE = 3, 78 AMDGPU_NPS4_PARTITION_MODE = 4, 79 AMDGPU_NPS6_PARTITION_MODE = 6, 80 AMDGPU_NPS8_PARTITION_MODE = 8, 81 }; 82 83 #define AMDGPU_ALL_NPS_MASK \ 84 (BIT(AMDGPU_NPS1_PARTITION_MODE) | BIT(AMDGPU_NPS2_PARTITION_MODE) | \ 85 BIT(AMDGPU_NPS3_PARTITION_MODE) | BIT(AMDGPU_NPS4_PARTITION_MODE) | \ 86 BIT(AMDGPU_NPS6_PARTITION_MODE) | BIT(AMDGPU_NPS8_PARTITION_MODE)) 87 88 #define AMDGPU_GMC_INIT_RESET_NPS BIT(0) 89 90 #define AMDGPU_MAX_MEM_RANGES 8 91 92 #define AMDGPU_GMC9_FAULT_SOURCE_DATA_RETRY 0x80 93 #define AMDGPU_GMC9_FAULT_SOURCE_DATA_READ 0x40 94 #define AMDGPU_GMC9_FAULT_SOURCE_DATA_WRITE 0x20 95 #define AMDGPU_GMC9_FAULT_SOURCE_DATA_EXE 0x10 96 97 #define AMDGPU_GMC121_FAULT_SOURCE_DATA_READ 0x400000 98 #define AMDGPU_GMC121_FAULT_SOURCE_DATA_WRITE 0x200000 99 #define AMDGPU_GMC121_FAULT_SOURCE_DATA_EXE 0x100000 100 101 /* 102 * GMC page fault information 103 */ 104 struct amdgpu_gmc_fault { 105 uint64_t timestamp:48; 106 uint64_t next:AMDGPU_GMC_FAULT_RING_ORDER; 107 atomic64_t key; 108 uint64_t timestamp_expiry:48; 109 }; 110 111 /* 112 * VMHUB structures, functions & helpers 113 */ 114 struct amdgpu_vmhub_funcs { 115 void (*print_l2_protection_fault_status)(struct amdgpu_device *adev, 116 uint32_t status); 117 void (*print_l2_protection_fault_status_hi)(struct amdgpu_device *adev, 118 uint32_t status); 119 uint32_t (*get_invalidate_req)(unsigned int vmid, uint32_t flush_type); 120 }; 121 122 struct amdgpu_vmhub { 123 uint32_t ctx0_ptb_addr_lo32; 124 uint32_t ctx0_ptb_addr_hi32; 125 uint32_t vm_inv_eng0_sem; 126 uint32_t vm_inv_eng0_req; 127 uint32_t vm_inv_eng0_ack; 128 uint32_t vm_context0_cntl; 129 uint32_t vm_l2_pro_fault_status; 130 uint32_t vm_l2_pro_fault_status_hi; 131 uint32_t vm_l2_pro_fault_cntl; 132 133 /* 134 * store the register distances between two continuous context domain 135 * and invalidation engine. 136 */ 137 uint32_t ctx_distance; 138 uint32_t ctx_addr_distance; /* include LO32/HI32 */ 139 uint32_t eng_distance; 140 uint32_t eng_addr_distance; /* include LO32/HI32 */ 141 142 uint32_t vm_cntx_cntl; 143 uint32_t vm_cntx_cntl_vm_fault; 144 uint32_t vm_l2_bank_select_reserved_cid2; 145 146 uint32_t vm_contexts_disable; 147 148 bool sdma_invalidation_workaround; 149 150 const struct amdgpu_vmhub_funcs *vmhub_funcs; 151 }; 152 153 /* 154 * GPU MC structures, functions & helpers 155 */ 156 struct amdgpu_gmc_funcs { 157 /* flush the vm tlb via mmio */ 158 void (*flush_gpu_tlb)(struct amdgpu_device *adev, uint32_t vmid, 159 uint32_t vmhub, uint32_t flush_type); 160 /* flush the vm tlb via pasid */ 161 void (*flush_gpu_tlb_pasid)(struct amdgpu_device *adev, uint16_t pasid, 162 uint32_t flush_type, bool all_hub, 163 uint32_t inst); 164 /* flush the vm tlb via ring */ 165 uint64_t (*emit_flush_gpu_tlb)(struct amdgpu_ring *ring, unsigned vmid, 166 uint64_t pd_addr); 167 /* Change the VMID -> PASID mapping */ 168 void (*emit_pasid_mapping)(struct amdgpu_ring *ring, unsigned vmid, 169 unsigned pasid); 170 /* enable/disable PRT support */ 171 void (*set_prt)(struct amdgpu_device *adev, bool enable); 172 /* get the pde for a given mc addr */ 173 void (*get_vm_pde)(struct amdgpu_device *adev, int level, 174 u64 *dst, u64 *flags); 175 /* get the pte flags to use for PTEs */ 176 void (*get_vm_pte)(struct amdgpu_device *adev, 177 struct amdgpu_vm *vm, 178 struct amdgpu_bo *bo, 179 uint32_t vm_flags, 180 uint64_t *pte_flags); 181 /* override per-page pte flags */ 182 void (*override_vm_pte_flags)(struct amdgpu_device *dev, 183 struct amdgpu_vm *vm, 184 uint64_t addr, uint64_t *flags); 185 /* get the amount of memory used by the vbios for pre-OS console */ 186 unsigned int (*get_vbios_fb_size)(struct amdgpu_device *adev); 187 /* get the DCC buffer alignment */ 188 unsigned int (*get_dcc_alignment)(struct amdgpu_device *adev); 189 190 enum amdgpu_memory_partition (*query_mem_partition_mode)( 191 struct amdgpu_device *adev); 192 /* Request NPS mode */ 193 int (*request_mem_partition_mode)(struct amdgpu_device *adev, 194 int nps_mode); 195 bool (*need_reset_on_init)(struct amdgpu_device *adev); 196 }; 197 198 struct amdgpu_mem_partition_info { 199 union { 200 struct { 201 uint32_t fpfn; 202 uint32_t lpfn; 203 } range; 204 struct { 205 int node; 206 } numa; 207 }; 208 uint64_t size; 209 }; 210 211 #define INVALID_PFN -1 212 213 struct amdgpu_gmc_memrange { 214 uint64_t base_address; 215 uint64_t limit_address; 216 uint32_t flags; 217 int nid_mask; 218 }; 219 220 enum amdgpu_gart_placement { 221 AMDGPU_GART_PLACEMENT_BEST_FIT = 0, 222 AMDGPU_GART_PLACEMENT_HIGH, 223 AMDGPU_GART_PLACEMENT_LOW, 224 }; 225 226 struct amdgpu_gmc { 227 /* FB's physical address in MMIO space (for CPU to 228 * map FB). This is different compared to the agp/ 229 * gart/vram_start/end field as the later is from 230 * GPU's view and aper_base is from CPU's view. 231 */ 232 resource_size_t aper_size; 233 resource_size_t aper_base; 234 /* for some chips with <= 32MB we need to lie 235 * about vram size near mc fb location */ 236 u64 mc_vram_size; 237 u64 visible_vram_size; 238 /* AGP aperture start and end in MC address space 239 * Driver find a hole in the MC address space 240 * to place AGP by setting MC_VM_AGP_BOT/TOP registers 241 * Under VMID0, logical address == MC address. AGP 242 * aperture maps to physical bus or IOVA addressed. 243 * AGP aperture is used to simulate FB in ZFB case. 244 * AGP aperture is also used for page table in system 245 * memory (mainly for APU). 246 * 247 */ 248 u64 agp_size; 249 u64 agp_start; 250 u64 agp_end; 251 /* GART aperture start and end in MC address space 252 * Driver find a hole in the MC address space 253 * to place GART by setting VM_CONTEXT0_PAGE_TABLE_START/END_ADDR 254 * registers 255 * Under VMID0, logical address inside GART aperture will 256 * be translated through gpuvm gart page table to access 257 * paged system memory 258 */ 259 u64 gart_size; 260 u64 gart_start; 261 u64 gart_end; 262 /* Frame buffer aperture of this GPU device. Different from 263 * fb_start (see below), this only covers the local GPU device. 264 * If driver uses FB aperture to access FB, driver get fb_start from 265 * MC_VM_FB_LOCATION_BASE (set by vbios) and calculate vram_start 266 * of this local device by adding an offset inside the XGMI hive. 267 * If driver uses GART table for VMID0 FB access, driver finds a hole in 268 * VMID0's virtual address space to place the SYSVM aperture inside 269 * which the first part is vram and the second part is gart (covering 270 * system ram). 271 */ 272 u64 vram_start; 273 u64 vram_end; 274 /* FB region , it's same as local vram region in single GPU, in XGMI 275 * configuration, this region covers all GPUs in the same hive , 276 * each GPU in the hive has the same view of this FB region . 277 * GPU0's vram starts at offset (0 * segment size) , 278 * GPU1 starts at offset (1 * segment size), etc. 279 */ 280 u64 fb_start; 281 u64 fb_end; 282 unsigned vram_width; 283 u64 real_vram_size; 284 int vram_mtrr; 285 u64 mc_mask; 286 uint64_t pte_addr_mask; 287 const struct firmware *fw; /* MC firmware */ 288 uint32_t fw_version; 289 struct amdgpu_irq_src vm_fault; 290 uint32_t vram_type; 291 uint8_t vram_vendor; 292 bool prt_warning; 293 uint32_t sdpif_register; 294 /* apertures */ 295 u64 shared_aperture_start; 296 u64 shared_aperture_end; 297 u64 private_aperture_start; 298 u64 private_aperture_end; 299 /* protects concurrent invalidation */ 300 spinlock_t invalidate_lock; 301 bool translate_further; 302 struct kfd_vm_fault_info *vm_fault_info; 303 atomic_t vm_fault_info_updated; 304 305 struct amdgpu_gmc_fault fault_ring[AMDGPU_GMC_FAULT_RING_SIZE]; 306 struct { 307 uint64_t idx:AMDGPU_GMC_FAULT_RING_ORDER; 308 } fault_hash[AMDGPU_GMC_FAULT_HASH_SIZE]; 309 uint64_t last_fault:AMDGPU_GMC_FAULT_RING_ORDER; 310 311 bool tmz_enabled; 312 bool is_app_apu; 313 314 struct amdgpu_mem_partition_info *mem_partitions; 315 uint8_t num_mem_partitions; 316 const struct amdgpu_gmc_funcs *gmc_funcs; 317 enum amdgpu_memory_partition requested_nps_mode; 318 uint32_t supported_nps_modes; 319 uint32_t reset_flags; 320 321 struct amdgpu_xgmi xgmi; 322 struct amdgpu_irq_src ecc_irq; 323 int noretry; 324 uint32_t xnack_flags; 325 326 uint32_t vmid0_page_table_block_size; 327 uint32_t vmid0_page_table_depth; 328 struct amdgpu_bo *pdb0_bo; 329 /* CPU kmapped address of pdb0*/ 330 void *ptr_pdb0; 331 332 /* MALL size */ 333 u64 mall_size; 334 uint32_t m_half_use; 335 336 /* number of UMC instances */ 337 int num_umc; 338 /* mode2 save restore */ 339 u64 VM_L2_CNTL; 340 u64 VM_L2_CNTL2; 341 u64 VM_DUMMY_PAGE_FAULT_CNTL; 342 u64 VM_DUMMY_PAGE_FAULT_ADDR_LO32; 343 u64 VM_DUMMY_PAGE_FAULT_ADDR_HI32; 344 u64 VM_L2_PROTECTION_FAULT_CNTL; 345 u64 VM_L2_PROTECTION_FAULT_CNTL2; 346 u64 VM_L2_PROTECTION_FAULT_MM_CNTL3; 347 u64 VM_L2_PROTECTION_FAULT_MM_CNTL4; 348 u64 VM_L2_PROTECTION_FAULT_ADDR_LO32; 349 u64 VM_L2_PROTECTION_FAULT_ADDR_HI32; 350 u64 VM_DEBUG; 351 u64 VM_L2_MM_GROUP_RT_CLASSES; 352 u64 VM_L2_BANK_SELECT_RESERVED_CID; 353 u64 VM_L2_BANK_SELECT_RESERVED_CID2; 354 u64 VM_L2_CACHE_PARITY_CNTL; 355 u64 VM_L2_IH_LOG_CNTL; 356 u64 VM_CONTEXT_CNTL[16]; 357 u64 VM_CONTEXT_PAGE_TABLE_BASE_ADDR_LO32[16]; 358 u64 VM_CONTEXT_PAGE_TABLE_BASE_ADDR_HI32[16]; 359 u64 VM_CONTEXT_PAGE_TABLE_START_ADDR_LO32[16]; 360 u64 VM_CONTEXT_PAGE_TABLE_START_ADDR_HI32[16]; 361 u64 VM_CONTEXT_PAGE_TABLE_END_ADDR_LO32[16]; 362 u64 VM_CONTEXT_PAGE_TABLE_END_ADDR_HI32[16]; 363 u64 MC_VM_MX_L1_TLB_CNTL; 364 365 u64 noretry_flags; 366 u64 init_pte_flags; 367 368 bool flush_tlb_needs_extra_type_0; 369 bool flush_tlb_needs_extra_type_2; 370 bool flush_pasid_uses_kiq; 371 372 bool override_pte; 373 }; 374 375 #define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (addr)) 376 #define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping((r), (vmid), (pasid)) 377 #define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) (adev)->gmc.gmc_funcs->get_vm_pde((adev), (level), (dst), (flags)) 378 #define amdgpu_gmc_get_vm_pte(adev, vm, bo, vm_flags, pte_flags) \ 379 ((adev)->gmc.gmc_funcs->get_vm_pte((adev), (vm), (bo), (vm_flags), \ 380 (pte_flags))) 381 #define amdgpu_gmc_override_vm_pte_flags(adev, vm, addr, pte_flags) \ 382 (adev)->gmc.gmc_funcs->override_vm_pte_flags \ 383 ((adev), (vm), (addr), (pte_flags)) 384 #define amdgpu_gmc_get_vbios_fb_size(adev) (adev)->gmc.gmc_funcs->get_vbios_fb_size((adev)) 385 #define amdgpu_gmc_get_dcc_alignment(adev) ({ \ 386 typeof(adev) _adev = (adev); \ 387 _adev->gmc.gmc_funcs->get_dcc_alignment(_adev); \ 388 }) 389 390 /** 391 * amdgpu_gmc_vram_full_visible - Check if full VRAM is visible through the BAR 392 * 393 * @adev: amdgpu_device pointer 394 * 395 * Returns: 396 * True if full VRAM is visible through the BAR 397 */ 398 static inline bool amdgpu_gmc_vram_full_visible(struct amdgpu_gmc *gmc) 399 { 400 WARN_ON(gmc->real_vram_size < gmc->visible_vram_size); 401 402 return (gmc->real_vram_size == gmc->visible_vram_size); 403 } 404 405 /** 406 * amdgpu_gmc_sign_extend - sign extend the given gmc address 407 * 408 * @addr: address to extend 409 */ 410 #define amdgpu_gmc_sign_extend(addr) ((addr) >= AMDGPU_GMC_HOLE_START ?\ 411 ((addr) | AMDGPU_GMC_HOLE_END) : (addr)) 412 413 bool amdgpu_gmc_is_pdb0_enabled(struct amdgpu_device *adev); 414 int amdgpu_gmc_pdb0_alloc(struct amdgpu_device *adev); 415 void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level, 416 uint64_t *addr, uint64_t *flags); 417 int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr, 418 uint32_t gpu_page_idx, uint64_t addr, 419 uint64_t flags); 420 uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo); 421 uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo); 422 void amdgpu_gmc_sysvm_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc); 423 void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc, 424 u64 base); 425 void amdgpu_gmc_gart_location(struct amdgpu_device *adev, 426 struct amdgpu_gmc *mc, 427 enum amdgpu_gart_placement gart_placement); 428 void amdgpu_gmc_agp_location(struct amdgpu_device *adev, 429 struct amdgpu_gmc *mc); 430 void amdgpu_gmc_set_agp_default(struct amdgpu_device *adev, 431 struct amdgpu_gmc *mc); 432 bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, 433 struct amdgpu_ih_ring *ih, uint64_t addr, 434 uint16_t pasid, uint64_t timestamp); 435 void amdgpu_gmc_filter_faults_remove(struct amdgpu_device *adev, uint64_t addr, 436 uint16_t pasid); 437 int amdgpu_gmc_handle_retry_fault(struct amdgpu_device *adev, 438 struct amdgpu_iv_entry *entry, 439 u64 addr, 440 u32 cam_index, 441 u32 node_id, 442 bool write_fault); 443 int amdgpu_gmc_ras_sw_init(struct amdgpu_device *adev); 444 int amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_device *adev); 445 void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 446 uint32_t vmhub, uint32_t flush_type); 447 int amdgpu_gmc_flush_gpu_tlb_pasid(struct amdgpu_device *adev, u16 pasid, 448 u32 flush_type, bool all_hub, u32 inst); 449 int amdgpu_gmc_flush_gpu_tlb_pasid_xccs(struct amdgpu_device *adev, u16 pasid, 450 u32 flush_type, bool all_hub, 451 u32 xcc_mask); 452 void amdgpu_gmc_fw_reg_write_reg_wait(struct amdgpu_device *adev, 453 uint32_t reg0, uint32_t reg1, 454 uint32_t ref, uint32_t mask, 455 uint32_t xcc_inst); 456 457 extern void amdgpu_gmc_tmz_set(struct amdgpu_device *adev); 458 extern void amdgpu_gmc_noretry_set(struct amdgpu_device *adev); 459 460 extern void 461 amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device *adev, int hub_type, 462 bool enable); 463 464 void amdgpu_gmc_init_vga_resv_regions(struct amdgpu_device *adev); 465 466 void amdgpu_gmc_init_pdb0(struct amdgpu_device *adev); 467 uint64_t amdgpu_gmc_vram_mc2pa(struct amdgpu_device *adev, uint64_t mc_addr); 468 uint64_t amdgpu_gmc_vram_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo); 469 int amdgpu_gmc_vram_checking(struct amdgpu_device *adev); 470 int amdgpu_gmc_sysfs_init(struct amdgpu_device *adev); 471 void amdgpu_gmc_sysfs_fini(struct amdgpu_device *adev); 472 473 int amdgpu_gmc_get_nps_memranges(struct amdgpu_device *adev, 474 struct amdgpu_mem_partition_info *mem_ranges, 475 uint8_t *exp_ranges); 476 477 int amdgpu_gmc_request_memory_partition(struct amdgpu_device *adev, 478 int nps_mode); 479 void amdgpu_gmc_prepare_nps_mode_change(struct amdgpu_device *adev); 480 bool amdgpu_gmc_need_reset_on_init(struct amdgpu_device *adev); 481 enum amdgpu_memory_partition 482 amdgpu_gmc_get_vf_memory_partition(struct amdgpu_device *adev); 483 enum amdgpu_memory_partition 484 amdgpu_gmc_get_memory_partition(struct amdgpu_device *adev, u32 *supp_modes); 485 enum amdgpu_memory_partition 486 amdgpu_gmc_query_memory_partition(struct amdgpu_device *adev); 487 int amdgpu_gmc_init_mem_ranges(struct amdgpu_device *adev); 488 void amdgpu_gmc_init_sw_mem_ranges(struct amdgpu_device *adev, 489 struct amdgpu_mem_partition_info *mem_ranges); 490 int amdgpu_gmc_get_vram_info(struct amdgpu_device *adev, 491 int *vram_width, int *vram_type, int *vram_vendor); 492 493 void amdgpu_gmc_set_gart_size(struct amdgpu_device *adev, u64 default_size); 494 #endif 495