1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 #ifndef __AMDGPU_GMC_H__ 27 #define __AMDGPU_GMC_H__ 28 29 #include <linux/types.h> 30 31 #include "amdgpu_irq.h" 32 #include "amdgpu_xgmi.h" 33 #include "amdgpu_ras.h" 34 35 /* VA hole for 48bit addresses on Vega10 */ 36 #define AMDGPU_GMC_HOLE_START 0x0000800000000000ULL 37 #define AMDGPU_GMC_HOLE_END 0xffff800000000000ULL 38 39 /* 40 * Hardware is programmed as if the hole doesn't exists with start and end 41 * address values. 42 * 43 * This mask is used to remove the upper 16bits of the VA and so come up with 44 * the linear addr value. 45 */ 46 #define AMDGPU_GMC_HOLE_MASK 0x0000ffffffffffffULL 47 48 /* 49 * Ring size as power of two for the log of recent faults. 50 */ 51 #define AMDGPU_GMC_FAULT_RING_ORDER 8 52 #define AMDGPU_GMC_FAULT_RING_SIZE (1 << AMDGPU_GMC_FAULT_RING_ORDER) 53 54 /* 55 * Hash size as power of two for the log of recent faults 56 */ 57 #define AMDGPU_GMC_FAULT_HASH_ORDER 8 58 #define AMDGPU_GMC_FAULT_HASH_SIZE (1 << AMDGPU_GMC_FAULT_HASH_ORDER) 59 60 /* 61 * Number of IH timestamp ticks until a fault is considered handled 62 */ 63 #define AMDGPU_GMC_FAULT_TIMEOUT 5000ULL 64 65 /* XNACK flags */ 66 #define AMDGPU_GMC_XNACK_FLAG_CHAIN BIT(0) 67 68 struct firmware; 69 70 enum amdgpu_memory_partition { 71 UNKNOWN_MEMORY_PARTITION_MODE = 0, 72 AMDGPU_NPS1_PARTITION_MODE = 1, 73 AMDGPU_NPS2_PARTITION_MODE = 2, 74 AMDGPU_NPS3_PARTITION_MODE = 3, 75 AMDGPU_NPS4_PARTITION_MODE = 4, 76 AMDGPU_NPS6_PARTITION_MODE = 6, 77 AMDGPU_NPS8_PARTITION_MODE = 8, 78 }; 79 80 #define AMDGPU_ALL_NPS_MASK \ 81 (BIT(AMDGPU_NPS1_PARTITION_MODE) | BIT(AMDGPU_NPS2_PARTITION_MODE) | \ 82 BIT(AMDGPU_NPS3_PARTITION_MODE) | BIT(AMDGPU_NPS4_PARTITION_MODE) | \ 83 BIT(AMDGPU_NPS6_PARTITION_MODE) | BIT(AMDGPU_NPS8_PARTITION_MODE)) 84 85 #define AMDGPU_GMC_INIT_RESET_NPS BIT(0) 86 87 #define AMDGPU_MAX_MEM_RANGES 8 88 89 /* 90 * GMC page fault information 91 */ 92 struct amdgpu_gmc_fault { 93 uint64_t timestamp:48; 94 uint64_t next:AMDGPU_GMC_FAULT_RING_ORDER; 95 atomic64_t key; 96 uint64_t timestamp_expiry:48; 97 }; 98 99 /* 100 * VMHUB structures, functions & helpers 101 */ 102 struct amdgpu_vmhub_funcs { 103 void (*print_l2_protection_fault_status)(struct amdgpu_device *adev, 104 uint32_t status); 105 uint32_t (*get_invalidate_req)(unsigned int vmid, uint32_t flush_type); 106 }; 107 108 struct amdgpu_vmhub { 109 uint32_t ctx0_ptb_addr_lo32; 110 uint32_t ctx0_ptb_addr_hi32; 111 uint32_t vm_inv_eng0_sem; 112 uint32_t vm_inv_eng0_req; 113 uint32_t vm_inv_eng0_ack; 114 uint32_t vm_context0_cntl; 115 uint32_t vm_l2_pro_fault_status; 116 uint32_t vm_l2_pro_fault_cntl; 117 118 /* 119 * store the register distances between two continuous context domain 120 * and invalidation engine. 121 */ 122 uint32_t ctx_distance; 123 uint32_t ctx_addr_distance; /* include LO32/HI32 */ 124 uint32_t eng_distance; 125 uint32_t eng_addr_distance; /* include LO32/HI32 */ 126 127 uint32_t vm_cntx_cntl; 128 uint32_t vm_cntx_cntl_vm_fault; 129 uint32_t vm_l2_bank_select_reserved_cid2; 130 131 uint32_t vm_contexts_disable; 132 133 bool sdma_invalidation_workaround; 134 135 const struct amdgpu_vmhub_funcs *vmhub_funcs; 136 }; 137 138 /* 139 * GPU MC structures, functions & helpers 140 */ 141 struct amdgpu_gmc_funcs { 142 /* flush the vm tlb via mmio */ 143 void (*flush_gpu_tlb)(struct amdgpu_device *adev, uint32_t vmid, 144 uint32_t vmhub, uint32_t flush_type); 145 /* flush the vm tlb via pasid */ 146 void (*flush_gpu_tlb_pasid)(struct amdgpu_device *adev, uint16_t pasid, 147 uint32_t flush_type, bool all_hub, 148 uint32_t inst); 149 /* flush the vm tlb via ring */ 150 uint64_t (*emit_flush_gpu_tlb)(struct amdgpu_ring *ring, unsigned vmid, 151 uint64_t pd_addr); 152 /* Change the VMID -> PASID mapping */ 153 void (*emit_pasid_mapping)(struct amdgpu_ring *ring, unsigned vmid, 154 unsigned pasid); 155 /* enable/disable PRT support */ 156 void (*set_prt)(struct amdgpu_device *adev, bool enable); 157 /* map mtype to hardware flags */ 158 uint64_t (*map_mtype)(struct amdgpu_device *adev, uint32_t flags); 159 /* get the pde for a given mc addr */ 160 void (*get_vm_pde)(struct amdgpu_device *adev, int level, 161 u64 *dst, u64 *flags); 162 /* get the pte flags to use for a BO VA mapping */ 163 void (*get_vm_pte)(struct amdgpu_device *adev, 164 struct amdgpu_bo_va_mapping *mapping, 165 uint64_t *flags); 166 /* override per-page pte flags */ 167 void (*override_vm_pte_flags)(struct amdgpu_device *dev, 168 struct amdgpu_vm *vm, 169 uint64_t addr, uint64_t *flags); 170 /* get the amount of memory used by the vbios for pre-OS console */ 171 unsigned int (*get_vbios_fb_size)(struct amdgpu_device *adev); 172 /* get the DCC buffer alignment */ 173 unsigned int (*get_dcc_alignment)(struct amdgpu_device *adev); 174 175 enum amdgpu_memory_partition (*query_mem_partition_mode)( 176 struct amdgpu_device *adev); 177 /* Request NPS mode */ 178 int (*request_mem_partition_mode)(struct amdgpu_device *adev, 179 int nps_mode); 180 bool (*need_reset_on_init)(struct amdgpu_device *adev); 181 }; 182 183 struct amdgpu_mem_partition_info { 184 union { 185 struct { 186 uint32_t fpfn; 187 uint32_t lpfn; 188 } range; 189 struct { 190 int node; 191 } numa; 192 }; 193 uint64_t size; 194 }; 195 196 #define INVALID_PFN -1 197 198 struct amdgpu_gmc_memrange { 199 uint64_t base_address; 200 uint64_t limit_address; 201 uint32_t flags; 202 int nid_mask; 203 }; 204 205 enum amdgpu_gart_placement { 206 AMDGPU_GART_PLACEMENT_BEST_FIT = 0, 207 AMDGPU_GART_PLACEMENT_HIGH, 208 AMDGPU_GART_PLACEMENT_LOW, 209 }; 210 211 struct amdgpu_gmc { 212 /* FB's physical address in MMIO space (for CPU to 213 * map FB). This is different compared to the agp/ 214 * gart/vram_start/end field as the later is from 215 * GPU's view and aper_base is from CPU's view. 216 */ 217 resource_size_t aper_size; 218 resource_size_t aper_base; 219 /* for some chips with <= 32MB we need to lie 220 * about vram size near mc fb location */ 221 u64 mc_vram_size; 222 u64 visible_vram_size; 223 /* AGP aperture start and end in MC address space 224 * Driver find a hole in the MC address space 225 * to place AGP by setting MC_VM_AGP_BOT/TOP registers 226 * Under VMID0, logical address == MC address. AGP 227 * aperture maps to physical bus or IOVA addressed. 228 * AGP aperture is used to simulate FB in ZFB case. 229 * AGP aperture is also used for page table in system 230 * memory (mainly for APU). 231 * 232 */ 233 u64 agp_size; 234 u64 agp_start; 235 u64 agp_end; 236 /* GART aperture start and end in MC address space 237 * Driver find a hole in the MC address space 238 * to place GART by setting VM_CONTEXT0_PAGE_TABLE_START/END_ADDR 239 * registers 240 * Under VMID0, logical address inside GART aperture will 241 * be translated through gpuvm gart page table to access 242 * paged system memory 243 */ 244 u64 gart_size; 245 u64 gart_start; 246 u64 gart_end; 247 /* Frame buffer aperture of this GPU device. Different from 248 * fb_start (see below), this only covers the local GPU device. 249 * If driver uses FB aperture to access FB, driver get fb_start from 250 * MC_VM_FB_LOCATION_BASE (set by vbios) and calculate vram_start 251 * of this local device by adding an offset inside the XGMI hive. 252 * If driver uses GART table for VMID0 FB access, driver finds a hole in 253 * VMID0's virtual address space to place the SYSVM aperture inside 254 * which the first part is vram and the second part is gart (covering 255 * system ram). 256 */ 257 u64 vram_start; 258 u64 vram_end; 259 /* FB region , it's same as local vram region in single GPU, in XGMI 260 * configuration, this region covers all GPUs in the same hive , 261 * each GPU in the hive has the same view of this FB region . 262 * GPU0's vram starts at offset (0 * segment size) , 263 * GPU1 starts at offset (1 * segment size), etc. 264 */ 265 u64 fb_start; 266 u64 fb_end; 267 unsigned vram_width; 268 u64 real_vram_size; 269 int vram_mtrr; 270 u64 mc_mask; 271 const struct firmware *fw; /* MC firmware */ 272 uint32_t fw_version; 273 struct amdgpu_irq_src vm_fault; 274 uint32_t vram_type; 275 uint8_t vram_vendor; 276 uint32_t srbm_soft_reset; 277 bool prt_warning; 278 uint32_t sdpif_register; 279 /* apertures */ 280 u64 shared_aperture_start; 281 u64 shared_aperture_end; 282 u64 private_aperture_start; 283 u64 private_aperture_end; 284 /* protects concurrent invalidation */ 285 spinlock_t invalidate_lock; 286 bool translate_further; 287 struct kfd_vm_fault_info *vm_fault_info; 288 atomic_t vm_fault_info_updated; 289 290 struct amdgpu_gmc_fault fault_ring[AMDGPU_GMC_FAULT_RING_SIZE]; 291 struct { 292 uint64_t idx:AMDGPU_GMC_FAULT_RING_ORDER; 293 } fault_hash[AMDGPU_GMC_FAULT_HASH_SIZE]; 294 uint64_t last_fault:AMDGPU_GMC_FAULT_RING_ORDER; 295 296 bool tmz_enabled; 297 bool is_app_apu; 298 299 struct amdgpu_mem_partition_info *mem_partitions; 300 uint8_t num_mem_partitions; 301 const struct amdgpu_gmc_funcs *gmc_funcs; 302 enum amdgpu_memory_partition requested_nps_mode; 303 uint32_t supported_nps_modes; 304 uint32_t reset_flags; 305 306 struct amdgpu_xgmi xgmi; 307 struct amdgpu_irq_src ecc_irq; 308 int noretry; 309 uint32_t xnack_flags; 310 311 uint32_t vmid0_page_table_block_size; 312 uint32_t vmid0_page_table_depth; 313 struct amdgpu_bo *pdb0_bo; 314 /* CPU kmapped address of pdb0*/ 315 void *ptr_pdb0; 316 317 /* MALL size */ 318 u64 mall_size; 319 uint32_t m_half_use; 320 321 /* number of UMC instances */ 322 int num_umc; 323 /* mode2 save restore */ 324 u64 VM_L2_CNTL; 325 u64 VM_L2_CNTL2; 326 u64 VM_DUMMY_PAGE_FAULT_CNTL; 327 u64 VM_DUMMY_PAGE_FAULT_ADDR_LO32; 328 u64 VM_DUMMY_PAGE_FAULT_ADDR_HI32; 329 u64 VM_L2_PROTECTION_FAULT_CNTL; 330 u64 VM_L2_PROTECTION_FAULT_CNTL2; 331 u64 VM_L2_PROTECTION_FAULT_MM_CNTL3; 332 u64 VM_L2_PROTECTION_FAULT_MM_CNTL4; 333 u64 VM_L2_PROTECTION_FAULT_ADDR_LO32; 334 u64 VM_L2_PROTECTION_FAULT_ADDR_HI32; 335 u64 VM_DEBUG; 336 u64 VM_L2_MM_GROUP_RT_CLASSES; 337 u64 VM_L2_BANK_SELECT_RESERVED_CID; 338 u64 VM_L2_BANK_SELECT_RESERVED_CID2; 339 u64 VM_L2_CACHE_PARITY_CNTL; 340 u64 VM_L2_IH_LOG_CNTL; 341 u64 VM_CONTEXT_CNTL[16]; 342 u64 VM_CONTEXT_PAGE_TABLE_BASE_ADDR_LO32[16]; 343 u64 VM_CONTEXT_PAGE_TABLE_BASE_ADDR_HI32[16]; 344 u64 VM_CONTEXT_PAGE_TABLE_START_ADDR_LO32[16]; 345 u64 VM_CONTEXT_PAGE_TABLE_START_ADDR_HI32[16]; 346 u64 VM_CONTEXT_PAGE_TABLE_END_ADDR_LO32[16]; 347 u64 VM_CONTEXT_PAGE_TABLE_END_ADDR_HI32[16]; 348 u64 MC_VM_MX_L1_TLB_CNTL; 349 350 u64 noretry_flags; 351 352 bool flush_tlb_needs_extra_type_0; 353 bool flush_tlb_needs_extra_type_2; 354 bool flush_pasid_uses_kiq; 355 }; 356 357 #define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (addr)) 358 #define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping((r), (vmid), (pasid)) 359 #define amdgpu_gmc_map_mtype(adev, flags) (adev)->gmc.gmc_funcs->map_mtype((adev),(flags)) 360 #define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) (adev)->gmc.gmc_funcs->get_vm_pde((adev), (level), (dst), (flags)) 361 #define amdgpu_gmc_get_vm_pte(adev, mapping, flags) (adev)->gmc.gmc_funcs->get_vm_pte((adev), (mapping), (flags)) 362 #define amdgpu_gmc_override_vm_pte_flags(adev, vm, addr, pte_flags) \ 363 (adev)->gmc.gmc_funcs->override_vm_pte_flags \ 364 ((adev), (vm), (addr), (pte_flags)) 365 #define amdgpu_gmc_get_vbios_fb_size(adev) (adev)->gmc.gmc_funcs->get_vbios_fb_size((adev)) 366 #define amdgpu_gmc_get_dcc_alignment(adev) ({ \ 367 typeof(adev) _adev = (adev); \ 368 _adev->gmc.gmc_funcs->get_dcc_alignment(_adev); \ 369 }) 370 371 /** 372 * amdgpu_gmc_vram_full_visible - Check if full VRAM is visible through the BAR 373 * 374 * @adev: amdgpu_device pointer 375 * 376 * Returns: 377 * True if full VRAM is visible through the BAR 378 */ 379 static inline bool amdgpu_gmc_vram_full_visible(struct amdgpu_gmc *gmc) 380 { 381 WARN_ON(gmc->real_vram_size < gmc->visible_vram_size); 382 383 return (gmc->real_vram_size == gmc->visible_vram_size); 384 } 385 386 /** 387 * amdgpu_gmc_sign_extend - sign extend the given gmc address 388 * 389 * @addr: address to extend 390 */ 391 static inline uint64_t amdgpu_gmc_sign_extend(uint64_t addr) 392 { 393 if (addr >= AMDGPU_GMC_HOLE_START) 394 addr |= AMDGPU_GMC_HOLE_END; 395 396 return addr; 397 } 398 399 bool amdgpu_gmc_is_pdb0_enabled(struct amdgpu_device *adev); 400 int amdgpu_gmc_pdb0_alloc(struct amdgpu_device *adev); 401 void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level, 402 uint64_t *addr, uint64_t *flags); 403 int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr, 404 uint32_t gpu_page_idx, uint64_t addr, 405 uint64_t flags); 406 uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo); 407 uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo); 408 void amdgpu_gmc_sysvm_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc); 409 void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc, 410 u64 base); 411 void amdgpu_gmc_gart_location(struct amdgpu_device *adev, 412 struct amdgpu_gmc *mc, 413 enum amdgpu_gart_placement gart_placement); 414 void amdgpu_gmc_agp_location(struct amdgpu_device *adev, 415 struct amdgpu_gmc *mc); 416 void amdgpu_gmc_set_agp_default(struct amdgpu_device *adev, 417 struct amdgpu_gmc *mc); 418 bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, 419 struct amdgpu_ih_ring *ih, uint64_t addr, 420 uint16_t pasid, uint64_t timestamp); 421 void amdgpu_gmc_filter_faults_remove(struct amdgpu_device *adev, uint64_t addr, 422 uint16_t pasid); 423 int amdgpu_gmc_ras_sw_init(struct amdgpu_device *adev); 424 int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev); 425 void amdgpu_gmc_ras_fini(struct amdgpu_device *adev); 426 int amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_device *adev); 427 void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 428 uint32_t vmhub, uint32_t flush_type); 429 int amdgpu_gmc_flush_gpu_tlb_pasid(struct amdgpu_device *adev, uint16_t pasid, 430 uint32_t flush_type, bool all_hub, 431 uint32_t inst); 432 void amdgpu_gmc_fw_reg_write_reg_wait(struct amdgpu_device *adev, 433 uint32_t reg0, uint32_t reg1, 434 uint32_t ref, uint32_t mask, 435 uint32_t xcc_inst); 436 437 extern void amdgpu_gmc_tmz_set(struct amdgpu_device *adev); 438 extern void amdgpu_gmc_noretry_set(struct amdgpu_device *adev); 439 440 extern void 441 amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device *adev, int hub_type, 442 bool enable); 443 444 void amdgpu_gmc_get_vbios_allocations(struct amdgpu_device *adev); 445 446 void amdgpu_gmc_init_pdb0(struct amdgpu_device *adev); 447 uint64_t amdgpu_gmc_vram_mc2pa(struct amdgpu_device *adev, uint64_t mc_addr); 448 uint64_t amdgpu_gmc_vram_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo); 449 int amdgpu_gmc_vram_checking(struct amdgpu_device *adev); 450 int amdgpu_gmc_sysfs_init(struct amdgpu_device *adev); 451 void amdgpu_gmc_sysfs_fini(struct amdgpu_device *adev); 452 453 int amdgpu_gmc_get_nps_memranges(struct amdgpu_device *adev, 454 struct amdgpu_mem_partition_info *mem_ranges, 455 uint8_t *exp_ranges); 456 457 int amdgpu_gmc_request_memory_partition(struct amdgpu_device *adev, 458 int nps_mode); 459 void amdgpu_gmc_prepare_nps_mode_change(struct amdgpu_device *adev); 460 bool amdgpu_gmc_need_reset_on_init(struct amdgpu_device *adev); 461 enum amdgpu_memory_partition 462 amdgpu_gmc_get_vf_memory_partition(struct amdgpu_device *adev); 463 enum amdgpu_memory_partition 464 amdgpu_gmc_get_memory_partition(struct amdgpu_device *adev, u32 *supp_modes); 465 enum amdgpu_memory_partition 466 amdgpu_gmc_query_memory_partition(struct amdgpu_device *adev); 467 int amdgpu_gmc_init_mem_ranges(struct amdgpu_device *adev); 468 void amdgpu_gmc_init_sw_mem_ranges(struct amdgpu_device *adev, 469 struct amdgpu_mem_partition_info *mem_ranges); 470 #endif 471