1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 27 #include <linux/io-64-nonatomic-lo-hi.h> 28 #ifdef CONFIG_X86 29 #include <asm/hypervisor.h> 30 #endif 31 32 #include "amdgpu.h" 33 #include "amdgpu_gmc.h" 34 #include "amdgpu_ras.h" 35 #include "amdgpu_reset.h" 36 #include "amdgpu_xgmi.h" 37 38 #include <drm/drm_drv.h> 39 #include <drm/ttm/ttm_tt.h> 40 41 /** 42 * amdgpu_gmc_pdb0_alloc - allocate vram for pdb0 43 * 44 * @adev: amdgpu_device pointer 45 * 46 * Allocate video memory for pdb0 and map it for CPU access 47 * Returns 0 for success, error for failure. 48 */ 49 int amdgpu_gmc_pdb0_alloc(struct amdgpu_device *adev) 50 { 51 int r; 52 struct amdgpu_bo_param bp; 53 u64 vram_size = adev->gmc.xgmi.node_segment_size * adev->gmc.xgmi.num_physical_nodes; 54 uint32_t pde0_page_shift = adev->gmc.vmid0_page_table_block_size + 21; 55 uint32_t npdes = (vram_size + (1ULL << pde0_page_shift) -1) >> pde0_page_shift; 56 57 memset(&bp, 0, sizeof(bp)); 58 bp.size = PAGE_ALIGN((npdes + 1) * 8); 59 bp.byte_align = PAGE_SIZE; 60 bp.domain = AMDGPU_GEM_DOMAIN_VRAM; 61 bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 62 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 63 bp.type = ttm_bo_type_kernel; 64 bp.resv = NULL; 65 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 66 67 r = amdgpu_bo_create(adev, &bp, &adev->gmc.pdb0_bo); 68 if (r) 69 return r; 70 71 r = amdgpu_bo_reserve(adev->gmc.pdb0_bo, false); 72 if (unlikely(r != 0)) 73 goto bo_reserve_failure; 74 75 r = amdgpu_bo_pin(adev->gmc.pdb0_bo, AMDGPU_GEM_DOMAIN_VRAM); 76 if (r) 77 goto bo_pin_failure; 78 r = amdgpu_bo_kmap(adev->gmc.pdb0_bo, &adev->gmc.ptr_pdb0); 79 if (r) 80 goto bo_kmap_failure; 81 82 amdgpu_bo_unreserve(adev->gmc.pdb0_bo); 83 return 0; 84 85 bo_kmap_failure: 86 amdgpu_bo_unpin(adev->gmc.pdb0_bo); 87 bo_pin_failure: 88 amdgpu_bo_unreserve(adev->gmc.pdb0_bo); 89 bo_reserve_failure: 90 amdgpu_bo_unref(&adev->gmc.pdb0_bo); 91 return r; 92 } 93 94 /** 95 * amdgpu_gmc_get_pde_for_bo - get the PDE for a BO 96 * 97 * @bo: the BO to get the PDE for 98 * @level: the level in the PD hirarchy 99 * @addr: resulting addr 100 * @flags: resulting flags 101 * 102 * Get the address and flags to be used for a PDE (Page Directory Entry). 103 */ 104 void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level, 105 uint64_t *addr, uint64_t *flags) 106 { 107 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 108 109 switch (bo->tbo.resource->mem_type) { 110 case TTM_PL_TT: 111 *addr = bo->tbo.ttm->dma_address[0]; 112 break; 113 case TTM_PL_VRAM: 114 *addr = amdgpu_bo_gpu_offset(bo); 115 break; 116 default: 117 *addr = 0; 118 break; 119 } 120 *flags = amdgpu_ttm_tt_pde_flags(bo->tbo.ttm, bo->tbo.resource); 121 amdgpu_gmc_get_vm_pde(adev, level, addr, flags); 122 } 123 124 /* 125 * amdgpu_gmc_pd_addr - return the address of the root directory 126 */ 127 uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo) 128 { 129 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 130 uint64_t pd_addr; 131 132 /* TODO: move that into ASIC specific code */ 133 if (adev->asic_type >= CHIP_VEGA10) { 134 uint64_t flags = AMDGPU_PTE_VALID; 135 136 amdgpu_gmc_get_pde_for_bo(bo, -1, &pd_addr, &flags); 137 pd_addr |= flags; 138 } else { 139 pd_addr = amdgpu_bo_gpu_offset(bo); 140 } 141 return pd_addr; 142 } 143 144 /** 145 * amdgpu_gmc_set_pte_pde - update the page tables using CPU 146 * 147 * @adev: amdgpu_device pointer 148 * @cpu_pt_addr: cpu address of the page table 149 * @gpu_page_idx: entry in the page table to update 150 * @addr: dst addr to write into pte/pde 151 * @flags: access flags 152 * 153 * Update the page tables using CPU. 154 */ 155 int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr, 156 uint32_t gpu_page_idx, uint64_t addr, 157 uint64_t flags) 158 { 159 void __iomem *ptr = (void *)cpu_pt_addr; 160 uint64_t value; 161 162 /* 163 * The following is for PTE only. GART does not have PDEs. 164 */ 165 value = addr & 0x0000FFFFFFFFF000ULL; 166 value |= flags; 167 writeq(value, ptr + (gpu_page_idx * 8)); 168 169 return 0; 170 } 171 172 /** 173 * amdgpu_gmc_agp_addr - return the address in the AGP address space 174 * 175 * @bo: TTM BO which needs the address, must be in GTT domain 176 * 177 * Tries to figure out how to access the BO through the AGP aperture. Returns 178 * AMDGPU_BO_INVALID_OFFSET if that is not possible. 179 */ 180 uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo) 181 { 182 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 183 184 if (bo->ttm->num_pages != 1 || bo->ttm->caching == ttm_cached) 185 return AMDGPU_BO_INVALID_OFFSET; 186 187 if (bo->ttm->dma_address[0] + PAGE_SIZE >= adev->gmc.agp_size) 188 return AMDGPU_BO_INVALID_OFFSET; 189 190 return adev->gmc.agp_start + bo->ttm->dma_address[0]; 191 } 192 193 /** 194 * amdgpu_gmc_vram_location - try to find VRAM location 195 * 196 * @adev: amdgpu device structure holding all necessary information 197 * @mc: memory controller structure holding memory information 198 * @base: base address at which to put VRAM 199 * 200 * Function will try to place VRAM at base address provided 201 * as parameter. 202 */ 203 void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc, 204 u64 base) 205 { 206 uint64_t vis_limit = (uint64_t)amdgpu_vis_vram_limit << 20; 207 uint64_t limit = (uint64_t)amdgpu_vram_limit << 20; 208 209 mc->vram_start = base; 210 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 211 if (limit < mc->real_vram_size) 212 mc->real_vram_size = limit; 213 214 if (vis_limit && vis_limit < mc->visible_vram_size) 215 mc->visible_vram_size = vis_limit; 216 217 if (mc->real_vram_size < mc->visible_vram_size) 218 mc->visible_vram_size = mc->real_vram_size; 219 220 if (mc->xgmi.num_physical_nodes == 0) { 221 mc->fb_start = mc->vram_start; 222 mc->fb_end = mc->vram_end; 223 } 224 dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", 225 mc->mc_vram_size >> 20, mc->vram_start, 226 mc->vram_end, mc->real_vram_size >> 20); 227 } 228 229 /** amdgpu_gmc_sysvm_location - place vram and gart in sysvm aperture 230 * 231 * @adev: amdgpu device structure holding all necessary information 232 * @mc: memory controller structure holding memory information 233 * 234 * This function is only used if use GART for FB translation. In such 235 * case, we use sysvm aperture (vmid0 page tables) for both vram 236 * and gart (aka system memory) access. 237 * 238 * GPUVM (and our organization of vmid0 page tables) require sysvm 239 * aperture to be placed at a location aligned with 8 times of native 240 * page size. For example, if vm_context0_cntl.page_table_block_size 241 * is 12, then native page size is 8G (2M*2^12), sysvm should start 242 * with a 64G aligned address. For simplicity, we just put sysvm at 243 * address 0. So vram start at address 0 and gart is right after vram. 244 */ 245 void amdgpu_gmc_sysvm_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc) 246 { 247 u64 hive_vram_start = 0; 248 u64 hive_vram_end = mc->xgmi.node_segment_size * mc->xgmi.num_physical_nodes - 1; 249 mc->vram_start = mc->xgmi.node_segment_size * mc->xgmi.physical_node_id; 250 mc->vram_end = mc->vram_start + mc->xgmi.node_segment_size - 1; 251 mc->gart_start = hive_vram_end + 1; 252 mc->gart_end = mc->gart_start + mc->gart_size - 1; 253 mc->fb_start = hive_vram_start; 254 mc->fb_end = hive_vram_end; 255 dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", 256 mc->mc_vram_size >> 20, mc->vram_start, 257 mc->vram_end, mc->real_vram_size >> 20); 258 dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n", 259 mc->gart_size >> 20, mc->gart_start, mc->gart_end); 260 } 261 262 /** 263 * amdgpu_gmc_gart_location - try to find GART location 264 * 265 * @adev: amdgpu device structure holding all necessary information 266 * @mc: memory controller structure holding memory information 267 * 268 * Function will place try to place GART before or after VRAM. 269 * If GART size is bigger than space left then we ajust GART size. 270 * Thus function will never fails. 271 */ 272 void amdgpu_gmc_gart_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc, 273 enum amdgpu_gart_placement gart_placement) 274 { 275 const uint64_t four_gb = 0x100000000ULL; 276 u64 size_af, size_bf; 277 /*To avoid the hole, limit the max mc address to AMDGPU_GMC_HOLE_START*/ 278 u64 max_mc_address = min(adev->gmc.mc_mask, AMDGPU_GMC_HOLE_START - 1); 279 280 /* VCE doesn't like it when BOs cross a 4GB segment, so align 281 * the GART base on a 4GB boundary as well. 282 */ 283 size_bf = mc->fb_start; 284 size_af = max_mc_address + 1 - ALIGN(mc->fb_end + 1, four_gb); 285 286 if (mc->gart_size > max(size_bf, size_af)) { 287 dev_warn(adev->dev, "limiting GART\n"); 288 mc->gart_size = max(size_bf, size_af); 289 } 290 291 switch (gart_placement) { 292 case AMDGPU_GART_PLACEMENT_HIGH: 293 mc->gart_start = max_mc_address - mc->gart_size + 1; 294 break; 295 case AMDGPU_GART_PLACEMENT_LOW: 296 mc->gart_start = 0; 297 break; 298 case AMDGPU_GART_PLACEMENT_BEST_FIT: 299 default: 300 if ((size_bf >= mc->gart_size && size_bf < size_af) || 301 (size_af < mc->gart_size)) 302 mc->gart_start = 0; 303 else 304 mc->gart_start = max_mc_address - mc->gart_size + 1; 305 break; 306 } 307 308 mc->gart_start &= ~(four_gb - 1); 309 mc->gart_end = mc->gart_start + mc->gart_size - 1; 310 dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n", 311 mc->gart_size >> 20, mc->gart_start, mc->gart_end); 312 } 313 314 /** 315 * amdgpu_gmc_agp_location - try to find AGP location 316 * @adev: amdgpu device structure holding all necessary information 317 * @mc: memory controller structure holding memory information 318 * 319 * Function will place try to find a place for the AGP BAR in the MC address 320 * space. 321 * 322 * AGP BAR will be assigned the largest available hole in the address space. 323 * Should be called after VRAM and GART locations are setup. 324 */ 325 void amdgpu_gmc_agp_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc) 326 { 327 const uint64_t sixteen_gb = 1ULL << 34; 328 const uint64_t sixteen_gb_mask = ~(sixteen_gb - 1); 329 u64 size_af, size_bf; 330 331 if (mc->fb_start > mc->gart_start) { 332 size_bf = (mc->fb_start & sixteen_gb_mask) - 333 ALIGN(mc->gart_end + 1, sixteen_gb); 334 size_af = mc->mc_mask + 1 - ALIGN(mc->fb_end + 1, sixteen_gb); 335 } else { 336 size_bf = mc->fb_start & sixteen_gb_mask; 337 size_af = (mc->gart_start & sixteen_gb_mask) - 338 ALIGN(mc->fb_end + 1, sixteen_gb); 339 } 340 341 if (size_bf > size_af) { 342 mc->agp_start = (mc->fb_start - size_bf) & sixteen_gb_mask; 343 mc->agp_size = size_bf; 344 } else { 345 mc->agp_start = ALIGN(mc->fb_end + 1, sixteen_gb); 346 mc->agp_size = size_af; 347 } 348 349 mc->agp_end = mc->agp_start + mc->agp_size - 1; 350 dev_info(adev->dev, "AGP: %lluM 0x%016llX - 0x%016llX\n", 351 mc->agp_size >> 20, mc->agp_start, mc->agp_end); 352 } 353 354 /** 355 * amdgpu_gmc_set_agp_default - Set the default AGP aperture value. 356 * @adev: amdgpu device structure holding all necessary information 357 * @mc: memory controller structure holding memory information 358 * 359 * To disable the AGP aperture, you need to set the start to a larger 360 * value than the end. This function sets the default value which 361 * can then be overridden using amdgpu_gmc_agp_location() if you want 362 * to enable the AGP aperture on a specific chip. 363 * 364 */ 365 void amdgpu_gmc_set_agp_default(struct amdgpu_device *adev, 366 struct amdgpu_gmc *mc) 367 { 368 mc->agp_start = 0xffffffffffff; 369 mc->agp_end = 0; 370 mc->agp_size = 0; 371 } 372 373 /** 374 * amdgpu_gmc_fault_key - get hask key from vm fault address and pasid 375 * 376 * @addr: 48 bit physical address, page aligned (36 significant bits) 377 * @pasid: 16 bit process address space identifier 378 */ 379 static inline uint64_t amdgpu_gmc_fault_key(uint64_t addr, uint16_t pasid) 380 { 381 return addr << 4 | pasid; 382 } 383 384 /** 385 * amdgpu_gmc_filter_faults - filter VM faults 386 * 387 * @adev: amdgpu device structure 388 * @ih: interrupt ring that the fault received from 389 * @addr: address of the VM fault 390 * @pasid: PASID of the process causing the fault 391 * @timestamp: timestamp of the fault 392 * 393 * Returns: 394 * True if the fault was filtered and should not be processed further. 395 * False if the fault is a new one and needs to be handled. 396 */ 397 bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, 398 struct amdgpu_ih_ring *ih, uint64_t addr, 399 uint16_t pasid, uint64_t timestamp) 400 { 401 struct amdgpu_gmc *gmc = &adev->gmc; 402 uint64_t stamp, key = amdgpu_gmc_fault_key(addr, pasid); 403 struct amdgpu_gmc_fault *fault; 404 uint32_t hash; 405 406 /* Stale retry fault if timestamp goes backward */ 407 if (amdgpu_ih_ts_after(timestamp, ih->processed_timestamp)) 408 return true; 409 410 /* If we don't have space left in the ring buffer return immediately */ 411 stamp = max(timestamp, AMDGPU_GMC_FAULT_TIMEOUT + 1) - 412 AMDGPU_GMC_FAULT_TIMEOUT; 413 if (gmc->fault_ring[gmc->last_fault].timestamp >= stamp) 414 return true; 415 416 /* Try to find the fault in the hash */ 417 hash = hash_64(key, AMDGPU_GMC_FAULT_HASH_ORDER); 418 fault = &gmc->fault_ring[gmc->fault_hash[hash].idx]; 419 while (fault->timestamp >= stamp) { 420 uint64_t tmp; 421 422 if (atomic64_read(&fault->key) == key) { 423 /* 424 * if we get a fault which is already present in 425 * the fault_ring and the timestamp of 426 * the fault is after the expired timestamp, 427 * then this is a new fault that needs to be added 428 * into the fault ring. 429 */ 430 if (fault->timestamp_expiry != 0 && 431 amdgpu_ih_ts_after(fault->timestamp_expiry, 432 timestamp)) 433 break; 434 else 435 return true; 436 } 437 438 tmp = fault->timestamp; 439 fault = &gmc->fault_ring[fault->next]; 440 441 /* Check if the entry was reused */ 442 if (fault->timestamp >= tmp) 443 break; 444 } 445 446 /* Add the fault to the ring */ 447 fault = &gmc->fault_ring[gmc->last_fault]; 448 atomic64_set(&fault->key, key); 449 fault->timestamp = timestamp; 450 451 /* And update the hash */ 452 fault->next = gmc->fault_hash[hash].idx; 453 gmc->fault_hash[hash].idx = gmc->last_fault++; 454 return false; 455 } 456 457 /** 458 * amdgpu_gmc_filter_faults_remove - remove address from VM faults filter 459 * 460 * @adev: amdgpu device structure 461 * @addr: address of the VM fault 462 * @pasid: PASID of the process causing the fault 463 * 464 * Remove the address from fault filter, then future vm fault on this address 465 * will pass to retry fault handler to recover. 466 */ 467 void amdgpu_gmc_filter_faults_remove(struct amdgpu_device *adev, uint64_t addr, 468 uint16_t pasid) 469 { 470 struct amdgpu_gmc *gmc = &adev->gmc; 471 uint64_t key = amdgpu_gmc_fault_key(addr, pasid); 472 struct amdgpu_ih_ring *ih; 473 struct amdgpu_gmc_fault *fault; 474 uint32_t last_wptr; 475 uint64_t last_ts; 476 uint32_t hash; 477 uint64_t tmp; 478 479 if (adev->irq.retry_cam_enabled) 480 return; 481 482 ih = &adev->irq.ih1; 483 /* Get the WPTR of the last entry in IH ring */ 484 last_wptr = amdgpu_ih_get_wptr(adev, ih); 485 /* Order wptr with ring data. */ 486 rmb(); 487 /* Get the timetamp of the last entry in IH ring */ 488 last_ts = amdgpu_ih_decode_iv_ts(adev, ih, last_wptr, -1); 489 490 hash = hash_64(key, AMDGPU_GMC_FAULT_HASH_ORDER); 491 fault = &gmc->fault_ring[gmc->fault_hash[hash].idx]; 492 do { 493 if (atomic64_read(&fault->key) == key) { 494 /* 495 * Update the timestamp when this fault 496 * expired. 497 */ 498 fault->timestamp_expiry = last_ts; 499 break; 500 } 501 502 tmp = fault->timestamp; 503 fault = &gmc->fault_ring[fault->next]; 504 } while (fault->timestamp < tmp); 505 } 506 507 int amdgpu_gmc_ras_sw_init(struct amdgpu_device *adev) 508 { 509 int r; 510 511 /* umc ras block */ 512 r = amdgpu_umc_ras_sw_init(adev); 513 if (r) 514 return r; 515 516 /* mmhub ras block */ 517 r = amdgpu_mmhub_ras_sw_init(adev); 518 if (r) 519 return r; 520 521 /* hdp ras block */ 522 r = amdgpu_hdp_ras_sw_init(adev); 523 if (r) 524 return r; 525 526 /* mca.x ras block */ 527 r = amdgpu_mca_mp0_ras_sw_init(adev); 528 if (r) 529 return r; 530 531 r = amdgpu_mca_mp1_ras_sw_init(adev); 532 if (r) 533 return r; 534 535 r = amdgpu_mca_mpio_ras_sw_init(adev); 536 if (r) 537 return r; 538 539 /* xgmi ras block */ 540 r = amdgpu_xgmi_ras_sw_init(adev); 541 if (r) 542 return r; 543 544 return 0; 545 } 546 547 int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev) 548 { 549 return 0; 550 } 551 552 void amdgpu_gmc_ras_fini(struct amdgpu_device *adev) 553 { 554 555 } 556 557 /* 558 * The latest engine allocation on gfx9/10 is: 559 * Engine 2, 3: firmware 560 * Engine 0, 1, 4~16: amdgpu ring, 561 * subject to change when ring number changes 562 * Engine 17: Gart flushes 563 */ 564 #define AMDGPU_VMHUB_INV_ENG_BITMAP 0x1FFF3 565 566 int amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_device *adev) 567 { 568 struct amdgpu_ring *ring; 569 unsigned vm_inv_engs[AMDGPU_MAX_VMHUBS] = {0}; 570 unsigned i; 571 unsigned vmhub, inv_eng; 572 573 /* init the vm inv eng for all vmhubs */ 574 for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 575 vm_inv_engs[i] = AMDGPU_VMHUB_INV_ENG_BITMAP; 576 /* reserve engine 5 for firmware */ 577 if (adev->enable_mes) 578 vm_inv_engs[i] &= ~(1 << 5); 579 /* reserve mmhub engine 3 for firmware */ 580 if (adev->enable_umsch_mm) 581 vm_inv_engs[i] &= ~(1 << 3); 582 } 583 584 for (i = 0; i < adev->num_rings; ++i) { 585 ring = adev->rings[i]; 586 vmhub = ring->vm_hub; 587 588 if (ring == &adev->mes.ring || 589 ring == &adev->umsch_mm.ring) 590 continue; 591 592 inv_eng = ffs(vm_inv_engs[vmhub]); 593 if (!inv_eng) { 594 dev_err(adev->dev, "no VM inv eng for ring %s\n", 595 ring->name); 596 return -EINVAL; 597 } 598 599 ring->vm_inv_eng = inv_eng - 1; 600 vm_inv_engs[vmhub] &= ~(1 << ring->vm_inv_eng); 601 602 dev_info(adev->dev, "ring %s uses VM inv eng %u on hub %u\n", 603 ring->name, ring->vm_inv_eng, ring->vm_hub); 604 } 605 606 return 0; 607 } 608 609 void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 610 uint32_t vmhub, uint32_t flush_type) 611 { 612 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 613 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 614 struct dma_fence *fence; 615 struct amdgpu_job *job; 616 int r; 617 618 if (!hub->sdma_invalidation_workaround || vmid || 619 !adev->mman.buffer_funcs_enabled || 620 !adev->ib_pool_ready || amdgpu_in_reset(adev) || 621 !ring->sched.ready) { 622 623 /* 624 * A GPU reset should flush all TLBs anyway, so no need to do 625 * this while one is ongoing. 626 */ 627 if (!down_read_trylock(&adev->reset_domain->sem)) 628 return; 629 630 if (adev->gmc.flush_tlb_needs_extra_type_2) 631 adev->gmc.gmc_funcs->flush_gpu_tlb(adev, vmid, 632 vmhub, 2); 633 634 if (adev->gmc.flush_tlb_needs_extra_type_0 && flush_type == 2) 635 adev->gmc.gmc_funcs->flush_gpu_tlb(adev, vmid, 636 vmhub, 0); 637 638 adev->gmc.gmc_funcs->flush_gpu_tlb(adev, vmid, vmhub, 639 flush_type); 640 up_read(&adev->reset_domain->sem); 641 return; 642 } 643 644 /* The SDMA on Navi 1x has a bug which can theoretically result in memory 645 * corruption if an invalidation happens at the same time as an VA 646 * translation. Avoid this by doing the invalidation from the SDMA 647 * itself at least for GART. 648 */ 649 mutex_lock(&adev->mman.gtt_window_lock); 650 r = amdgpu_job_alloc_with_ib(ring->adev, &adev->mman.high_pr, 651 AMDGPU_FENCE_OWNER_UNDEFINED, 652 16 * 4, AMDGPU_IB_POOL_IMMEDIATE, 653 &job); 654 if (r) 655 goto error_alloc; 656 657 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo); 658 job->vm_needs_flush = true; 659 job->ibs->ptr[job->ibs->length_dw++] = ring->funcs->nop; 660 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 661 fence = amdgpu_job_submit(job); 662 mutex_unlock(&adev->mman.gtt_window_lock); 663 664 dma_fence_wait(fence, false); 665 dma_fence_put(fence); 666 667 return; 668 669 error_alloc: 670 mutex_unlock(&adev->mman.gtt_window_lock); 671 dev_err(adev->dev, "Error flushing GPU TLB using the SDMA (%d)!\n", r); 672 } 673 674 int amdgpu_gmc_flush_gpu_tlb_pasid(struct amdgpu_device *adev, uint16_t pasid, 675 uint32_t flush_type, bool all_hub, 676 uint32_t inst) 677 { 678 u32 usec_timeout = amdgpu_sriov_vf(adev) ? SRIOV_USEC_TIMEOUT : 679 adev->usec_timeout; 680 struct amdgpu_ring *ring = &adev->gfx.kiq[inst].ring; 681 struct amdgpu_kiq *kiq = &adev->gfx.kiq[inst]; 682 unsigned int ndw; 683 signed long r; 684 uint32_t seq; 685 686 if (!adev->gmc.flush_pasid_uses_kiq || !ring->sched.ready || 687 !down_read_trylock(&adev->reset_domain->sem)) { 688 689 if (adev->gmc.flush_tlb_needs_extra_type_2) 690 adev->gmc.gmc_funcs->flush_gpu_tlb_pasid(adev, pasid, 691 2, all_hub, 692 inst); 693 694 if (adev->gmc.flush_tlb_needs_extra_type_0 && flush_type == 2) 695 adev->gmc.gmc_funcs->flush_gpu_tlb_pasid(adev, pasid, 696 0, all_hub, 697 inst); 698 699 adev->gmc.gmc_funcs->flush_gpu_tlb_pasid(adev, pasid, 700 flush_type, all_hub, 701 inst); 702 return 0; 703 } 704 705 /* 2 dwords flush + 8 dwords fence */ 706 ndw = kiq->pmf->invalidate_tlbs_size + 8; 707 708 if (adev->gmc.flush_tlb_needs_extra_type_2) 709 ndw += kiq->pmf->invalidate_tlbs_size; 710 711 if (adev->gmc.flush_tlb_needs_extra_type_0) 712 ndw += kiq->pmf->invalidate_tlbs_size; 713 714 spin_lock(&adev->gfx.kiq[inst].ring_lock); 715 amdgpu_ring_alloc(ring, ndw); 716 if (adev->gmc.flush_tlb_needs_extra_type_2) 717 kiq->pmf->kiq_invalidate_tlbs(ring, pasid, 2, all_hub); 718 719 if (flush_type == 2 && adev->gmc.flush_tlb_needs_extra_type_0) 720 kiq->pmf->kiq_invalidate_tlbs(ring, pasid, 0, all_hub); 721 722 kiq->pmf->kiq_invalidate_tlbs(ring, pasid, flush_type, all_hub); 723 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT); 724 if (r) { 725 amdgpu_ring_undo(ring); 726 spin_unlock(&adev->gfx.kiq[inst].ring_lock); 727 goto error_unlock_reset; 728 } 729 730 amdgpu_ring_commit(ring); 731 spin_unlock(&adev->gfx.kiq[inst].ring_lock); 732 r = amdgpu_fence_wait_polling(ring, seq, usec_timeout); 733 if (r < 1) { 734 dev_err(adev->dev, "wait for kiq fence error: %ld.\n", r); 735 r = -ETIME; 736 goto error_unlock_reset; 737 } 738 r = 0; 739 740 error_unlock_reset: 741 up_read(&adev->reset_domain->sem); 742 return r; 743 } 744 745 /** 746 * amdgpu_gmc_tmz_set -- check and set if a device supports TMZ 747 * @adev: amdgpu_device pointer 748 * 749 * Check and set if an the device @adev supports Trusted Memory 750 * Zones (TMZ). 751 */ 752 void amdgpu_gmc_tmz_set(struct amdgpu_device *adev) 753 { 754 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 755 /* RAVEN */ 756 case IP_VERSION(9, 2, 2): 757 case IP_VERSION(9, 1, 0): 758 /* RENOIR looks like RAVEN */ 759 case IP_VERSION(9, 3, 0): 760 /* GC 10.3.7 */ 761 case IP_VERSION(10, 3, 7): 762 /* GC 11.0.1 */ 763 case IP_VERSION(11, 0, 1): 764 if (amdgpu_tmz == 0) { 765 adev->gmc.tmz_enabled = false; 766 dev_info(adev->dev, 767 "Trusted Memory Zone (TMZ) feature disabled (cmd line)\n"); 768 } else { 769 adev->gmc.tmz_enabled = true; 770 dev_info(adev->dev, 771 "Trusted Memory Zone (TMZ) feature enabled\n"); 772 } 773 break; 774 case IP_VERSION(10, 1, 10): 775 case IP_VERSION(10, 1, 1): 776 case IP_VERSION(10, 1, 2): 777 case IP_VERSION(10, 1, 3): 778 case IP_VERSION(10, 3, 0): 779 case IP_VERSION(10, 3, 2): 780 case IP_VERSION(10, 3, 4): 781 case IP_VERSION(10, 3, 5): 782 case IP_VERSION(10, 3, 6): 783 /* VANGOGH */ 784 case IP_VERSION(10, 3, 1): 785 /* YELLOW_CARP*/ 786 case IP_VERSION(10, 3, 3): 787 case IP_VERSION(11, 0, 4): 788 /* Don't enable it by default yet. 789 */ 790 if (amdgpu_tmz < 1) { 791 adev->gmc.tmz_enabled = false; 792 dev_info(adev->dev, 793 "Trusted Memory Zone (TMZ) feature disabled as experimental (default)\n"); 794 } else { 795 adev->gmc.tmz_enabled = true; 796 dev_info(adev->dev, 797 "Trusted Memory Zone (TMZ) feature enabled as experimental (cmd line)\n"); 798 } 799 break; 800 default: 801 adev->gmc.tmz_enabled = false; 802 dev_info(adev->dev, 803 "Trusted Memory Zone (TMZ) feature not supported\n"); 804 break; 805 } 806 } 807 808 /** 809 * amdgpu_gmc_noretry_set -- set per asic noretry defaults 810 * @adev: amdgpu_device pointer 811 * 812 * Set a per asic default for the no-retry parameter. 813 * 814 */ 815 void amdgpu_gmc_noretry_set(struct amdgpu_device *adev) 816 { 817 struct amdgpu_gmc *gmc = &adev->gmc; 818 uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0); 819 bool noretry_default = (gc_ver == IP_VERSION(9, 0, 1) || 820 gc_ver == IP_VERSION(9, 3, 0) || 821 gc_ver == IP_VERSION(9, 4, 0) || 822 gc_ver == IP_VERSION(9, 4, 1) || 823 gc_ver == IP_VERSION(9, 4, 2) || 824 gc_ver == IP_VERSION(9, 4, 3) || 825 gc_ver >= IP_VERSION(10, 3, 0)); 826 827 gmc->noretry = (amdgpu_noretry == -1) ? noretry_default : amdgpu_noretry; 828 } 829 830 void amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device *adev, int hub_type, 831 bool enable) 832 { 833 struct amdgpu_vmhub *hub; 834 u32 tmp, reg, i; 835 836 hub = &adev->vmhub[hub_type]; 837 for (i = 0; i < 16; i++) { 838 reg = hub->vm_context0_cntl + hub->ctx_distance * i; 839 840 tmp = (hub_type == AMDGPU_GFXHUB(0)) ? 841 RREG32_SOC15_IP(GC, reg) : 842 RREG32_SOC15_IP(MMHUB, reg); 843 844 if (enable) 845 tmp |= hub->vm_cntx_cntl_vm_fault; 846 else 847 tmp &= ~hub->vm_cntx_cntl_vm_fault; 848 849 (hub_type == AMDGPU_GFXHUB(0)) ? 850 WREG32_SOC15_IP(GC, reg, tmp) : 851 WREG32_SOC15_IP(MMHUB, reg, tmp); 852 } 853 } 854 855 void amdgpu_gmc_get_vbios_allocations(struct amdgpu_device *adev) 856 { 857 unsigned size; 858 859 /* 860 * Some ASICs need to reserve a region of video memory to avoid access 861 * from driver 862 */ 863 adev->mman.stolen_reserved_offset = 0; 864 adev->mman.stolen_reserved_size = 0; 865 866 /* 867 * TODO: 868 * Currently there is a bug where some memory client outside 869 * of the driver writes to first 8M of VRAM on S3 resume, 870 * this overrides GART which by default gets placed in first 8M and 871 * causes VM_FAULTS once GTT is accessed. 872 * Keep the stolen memory reservation until the while this is not solved. 873 */ 874 switch (adev->asic_type) { 875 case CHIP_VEGA10: 876 adev->mman.keep_stolen_vga_memory = true; 877 /* 878 * VEGA10 SRIOV VF with MS_HYPERV host needs some firmware reserved area. 879 */ 880 #ifdef CONFIG_X86 881 if (amdgpu_sriov_vf(adev) && hypervisor_is_type(X86_HYPER_MS_HYPERV)) { 882 adev->mman.stolen_reserved_offset = 0x500000; 883 adev->mman.stolen_reserved_size = 0x200000; 884 } 885 #endif 886 break; 887 case CHIP_RAVEN: 888 case CHIP_RENOIR: 889 adev->mman.keep_stolen_vga_memory = true; 890 break; 891 default: 892 adev->mman.keep_stolen_vga_memory = false; 893 break; 894 } 895 896 if (amdgpu_sriov_vf(adev) || 897 !amdgpu_device_has_display_hardware(adev)) { 898 size = 0; 899 } else { 900 size = amdgpu_gmc_get_vbios_fb_size(adev); 901 902 if (adev->mman.keep_stolen_vga_memory) 903 size = max(size, (unsigned)AMDGPU_VBIOS_VGA_ALLOCATION); 904 } 905 906 /* set to 0 if the pre-OS buffer uses up most of vram */ 907 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024)) 908 size = 0; 909 910 if (size > AMDGPU_VBIOS_VGA_ALLOCATION) { 911 adev->mman.stolen_vga_size = AMDGPU_VBIOS_VGA_ALLOCATION; 912 adev->mman.stolen_extended_size = size - adev->mman.stolen_vga_size; 913 } else { 914 adev->mman.stolen_vga_size = size; 915 adev->mman.stolen_extended_size = 0; 916 } 917 } 918 919 /** 920 * amdgpu_gmc_init_pdb0 - initialize PDB0 921 * 922 * @adev: amdgpu_device pointer 923 * 924 * This function is only used when GART page table is used 925 * for FB address translatioin. In such a case, we construct 926 * a 2-level system VM page table: PDB0->PTB, to cover both 927 * VRAM of the hive and system memory. 928 * 929 * PDB0 is static, initialized once on driver initialization. 930 * The first n entries of PDB0 are used as PTE by setting 931 * P bit to 1, pointing to VRAM. The n+1'th entry points 932 * to a big PTB covering system memory. 933 * 934 */ 935 void amdgpu_gmc_init_pdb0(struct amdgpu_device *adev) 936 { 937 int i; 938 uint64_t flags = adev->gart.gart_pte_flags; //TODO it is UC. explore NC/RW? 939 /* Each PDE0 (used as PTE) covers (2^vmid0_page_table_block_size)*2M 940 */ 941 u64 vram_size = adev->gmc.xgmi.node_segment_size * adev->gmc.xgmi.num_physical_nodes; 942 u64 pde0_page_size = (1ULL<<adev->gmc.vmid0_page_table_block_size)<<21; 943 u64 vram_addr = adev->vm_manager.vram_base_offset - 944 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 945 u64 vram_end = vram_addr + vram_size; 946 u64 gart_ptb_gpu_pa = amdgpu_gmc_vram_pa(adev, adev->gart.bo); 947 int idx; 948 949 if (!drm_dev_enter(adev_to_drm(adev), &idx)) 950 return; 951 952 flags |= AMDGPU_PTE_VALID | AMDGPU_PTE_READABLE; 953 flags |= AMDGPU_PTE_WRITEABLE; 954 flags |= AMDGPU_PTE_SNOOPED; 955 flags |= AMDGPU_PTE_FRAG((adev->gmc.vmid0_page_table_block_size + 9*1)); 956 flags |= AMDGPU_PDE_PTE; 957 958 /* The first n PDE0 entries are used as PTE, 959 * pointing to vram 960 */ 961 for (i = 0; vram_addr < vram_end; i++, vram_addr += pde0_page_size) 962 amdgpu_gmc_set_pte_pde(adev, adev->gmc.ptr_pdb0, i, vram_addr, flags); 963 964 /* The n+1'th PDE0 entry points to a huge 965 * PTB who has more than 512 entries each 966 * pointing to a 4K system page 967 */ 968 flags = AMDGPU_PTE_VALID; 969 flags |= AMDGPU_PDE_BFS(0) | AMDGPU_PTE_SNOOPED; 970 /* Requires gart_ptb_gpu_pa to be 4K aligned */ 971 amdgpu_gmc_set_pte_pde(adev, adev->gmc.ptr_pdb0, i, gart_ptb_gpu_pa, flags); 972 drm_dev_exit(idx); 973 } 974 975 /** 976 * amdgpu_gmc_vram_mc2pa - calculate vram buffer's physical address from MC 977 * address 978 * 979 * @adev: amdgpu_device pointer 980 * @mc_addr: MC address of buffer 981 */ 982 uint64_t amdgpu_gmc_vram_mc2pa(struct amdgpu_device *adev, uint64_t mc_addr) 983 { 984 return mc_addr - adev->gmc.vram_start + adev->vm_manager.vram_base_offset; 985 } 986 987 /** 988 * amdgpu_gmc_vram_pa - calculate vram buffer object's physical address from 989 * GPU's view 990 * 991 * @adev: amdgpu_device pointer 992 * @bo: amdgpu buffer object 993 */ 994 uint64_t amdgpu_gmc_vram_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo) 995 { 996 return amdgpu_gmc_vram_mc2pa(adev, amdgpu_bo_gpu_offset(bo)); 997 } 998 999 /** 1000 * amdgpu_gmc_vram_cpu_pa - calculate vram buffer object's physical address 1001 * from CPU's view 1002 * 1003 * @adev: amdgpu_device pointer 1004 * @bo: amdgpu buffer object 1005 */ 1006 uint64_t amdgpu_gmc_vram_cpu_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo) 1007 { 1008 return amdgpu_bo_gpu_offset(bo) - adev->gmc.vram_start + adev->gmc.aper_base; 1009 } 1010 1011 int amdgpu_gmc_vram_checking(struct amdgpu_device *adev) 1012 { 1013 struct amdgpu_bo *vram_bo = NULL; 1014 uint64_t vram_gpu = 0; 1015 void *vram_ptr = NULL; 1016 1017 int ret, size = 0x100000; 1018 uint8_t cptr[10]; 1019 1020 ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE, 1021 AMDGPU_GEM_DOMAIN_VRAM, 1022 &vram_bo, 1023 &vram_gpu, 1024 &vram_ptr); 1025 if (ret) 1026 return ret; 1027 1028 memset(vram_ptr, 0x86, size); 1029 memset(cptr, 0x86, 10); 1030 1031 /** 1032 * Check the start, the mid, and the end of the memory if the content of 1033 * each byte is the pattern "0x86". If yes, we suppose the vram bo is 1034 * workable. 1035 * 1036 * Note: If check the each byte of whole 1M bo, it will cost too many 1037 * seconds, so here, we just pick up three parts for emulation. 1038 */ 1039 ret = memcmp(vram_ptr, cptr, 10); 1040 if (ret) 1041 return ret; 1042 1043 ret = memcmp(vram_ptr + (size / 2), cptr, 10); 1044 if (ret) 1045 return ret; 1046 1047 ret = memcmp(vram_ptr + size - 10, cptr, 10); 1048 if (ret) 1049 return ret; 1050 1051 amdgpu_bo_free_kernel(&vram_bo, &vram_gpu, 1052 &vram_ptr); 1053 1054 return 0; 1055 } 1056 1057 static ssize_t current_memory_partition_show( 1058 struct device *dev, struct device_attribute *addr, char *buf) 1059 { 1060 struct drm_device *ddev = dev_get_drvdata(dev); 1061 struct amdgpu_device *adev = drm_to_adev(ddev); 1062 enum amdgpu_memory_partition mode; 1063 1064 mode = adev->gmc.gmc_funcs->query_mem_partition_mode(adev); 1065 switch (mode) { 1066 case AMDGPU_NPS1_PARTITION_MODE: 1067 return sysfs_emit(buf, "NPS1\n"); 1068 case AMDGPU_NPS2_PARTITION_MODE: 1069 return sysfs_emit(buf, "NPS2\n"); 1070 case AMDGPU_NPS3_PARTITION_MODE: 1071 return sysfs_emit(buf, "NPS3\n"); 1072 case AMDGPU_NPS4_PARTITION_MODE: 1073 return sysfs_emit(buf, "NPS4\n"); 1074 case AMDGPU_NPS6_PARTITION_MODE: 1075 return sysfs_emit(buf, "NPS6\n"); 1076 case AMDGPU_NPS8_PARTITION_MODE: 1077 return sysfs_emit(buf, "NPS8\n"); 1078 default: 1079 return sysfs_emit(buf, "UNKNOWN\n"); 1080 } 1081 1082 return sysfs_emit(buf, "UNKNOWN\n"); 1083 } 1084 1085 static DEVICE_ATTR_RO(current_memory_partition); 1086 1087 int amdgpu_gmc_sysfs_init(struct amdgpu_device *adev) 1088 { 1089 if (!adev->gmc.gmc_funcs->query_mem_partition_mode) 1090 return 0; 1091 1092 return device_create_file(adev->dev, 1093 &dev_attr_current_memory_partition); 1094 } 1095 1096 void amdgpu_gmc_sysfs_fini(struct amdgpu_device *adev) 1097 { 1098 device_remove_file(adev->dev, &dev_attr_current_memory_partition); 1099 } 1100