1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 27 #include <linux/io-64-nonatomic-lo-hi.h> 28 #ifdef CONFIG_X86 29 #include <asm/hypervisor.h> 30 #endif 31 32 #include "amdgpu.h" 33 #include "amdgpu_gmc.h" 34 #include "amdgpu_ras.h" 35 #include "amdgpu_reset.h" 36 #include "amdgpu_xgmi.h" 37 #include "amdgpu_atomfirmware.h" 38 39 #include <drm/drm_drv.h> 40 #include <drm/ttm/ttm_tt.h> 41 42 static const u64 four_gb = 0x100000000ULL; 43 44 bool amdgpu_gmc_is_pdb0_enabled(struct amdgpu_device *adev) 45 { 46 return adev->gmc.xgmi.connected_to_cpu || amdgpu_virt_xgmi_migrate_enabled(adev); 47 } 48 49 /** 50 * amdgpu_gmc_pdb0_alloc - allocate vram for pdb0 51 * 52 * @adev: amdgpu_device pointer 53 * 54 * Allocate video memory for pdb0 and map it for CPU access 55 * Returns 0 for success, error for failure. 56 */ 57 int amdgpu_gmc_pdb0_alloc(struct amdgpu_device *adev) 58 { 59 int r; 60 struct amdgpu_bo_param bp; 61 u64 vram_size = adev->gmc.xgmi.node_segment_size * adev->gmc.xgmi.num_physical_nodes; 62 uint32_t pde0_page_shift = adev->gmc.vmid0_page_table_block_size + 21; 63 uint32_t npdes = (vram_size + (1ULL << pde0_page_shift) - 1) >> pde0_page_shift; 64 65 memset(&bp, 0, sizeof(bp)); 66 bp.size = PAGE_ALIGN((npdes + 1) * 8); 67 bp.byte_align = PAGE_SIZE; 68 bp.domain = AMDGPU_GEM_DOMAIN_VRAM; 69 bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 70 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 71 bp.type = ttm_bo_type_kernel; 72 bp.resv = NULL; 73 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 74 75 r = amdgpu_bo_create(adev, &bp, &adev->gmc.pdb0_bo); 76 if (r) 77 return r; 78 79 r = amdgpu_bo_reserve(adev->gmc.pdb0_bo, false); 80 if (unlikely(r != 0)) 81 goto bo_reserve_failure; 82 83 r = amdgpu_bo_pin(adev->gmc.pdb0_bo, AMDGPU_GEM_DOMAIN_VRAM); 84 if (r) 85 goto bo_pin_failure; 86 r = amdgpu_bo_kmap(adev->gmc.pdb0_bo, &adev->gmc.ptr_pdb0); 87 if (r) 88 goto bo_kmap_failure; 89 90 amdgpu_bo_unreserve(adev->gmc.pdb0_bo); 91 return 0; 92 93 bo_kmap_failure: 94 amdgpu_bo_unpin(adev->gmc.pdb0_bo); 95 bo_pin_failure: 96 amdgpu_bo_unreserve(adev->gmc.pdb0_bo); 97 bo_reserve_failure: 98 amdgpu_bo_unref(&adev->gmc.pdb0_bo); 99 return r; 100 } 101 102 /** 103 * amdgpu_gmc_get_pde_for_bo - get the PDE for a BO 104 * 105 * @bo: the BO to get the PDE for 106 * @level: the level in the PD hirarchy 107 * @addr: resulting addr 108 * @flags: resulting flags 109 * 110 * Get the address and flags to be used for a PDE (Page Directory Entry). 111 */ 112 void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level, 113 uint64_t *addr, uint64_t *flags) 114 { 115 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 116 117 switch (bo->tbo.resource->mem_type) { 118 case TTM_PL_TT: 119 *addr = bo->tbo.ttm->dma_address[0]; 120 break; 121 case TTM_PL_VRAM: 122 *addr = amdgpu_bo_gpu_offset(bo); 123 break; 124 default: 125 *addr = 0; 126 break; 127 } 128 *flags = amdgpu_ttm_tt_pde_flags(bo->tbo.ttm, bo->tbo.resource); 129 amdgpu_gmc_get_vm_pde(adev, level, addr, flags); 130 } 131 132 /* 133 * amdgpu_gmc_pd_addr - return the address of the root directory 134 */ 135 uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo) 136 { 137 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 138 uint64_t pd_addr; 139 140 /* TODO: move that into ASIC specific code */ 141 if (adev->asic_type >= CHIP_VEGA10) { 142 uint64_t flags = AMDGPU_PTE_VALID; 143 144 amdgpu_gmc_get_pde_for_bo(bo, -1, &pd_addr, &flags); 145 pd_addr |= flags; 146 } else { 147 pd_addr = amdgpu_bo_gpu_offset(bo); 148 } 149 return pd_addr; 150 } 151 152 /** 153 * amdgpu_gmc_set_pte_pde - update the page tables using CPU 154 * 155 * @adev: amdgpu_device pointer 156 * @cpu_pt_addr: cpu address of the page table 157 * @gpu_page_idx: entry in the page table to update 158 * @addr: dst addr to write into pte/pde 159 * @flags: access flags 160 * 161 * Update the page tables using CPU. 162 */ 163 int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr, 164 uint32_t gpu_page_idx, uint64_t addr, 165 uint64_t flags) 166 { 167 void __iomem *ptr = (void *)cpu_pt_addr; 168 uint64_t value; 169 170 /* 171 * The following is for PTE only. GART does not have PDEs. 172 */ 173 value = addr & 0x0000FFFFFFFFF000ULL; 174 value |= flags; 175 writeq(value, ptr + (gpu_page_idx * 8)); 176 177 return 0; 178 } 179 180 /** 181 * amdgpu_gmc_agp_addr - return the address in the AGP address space 182 * 183 * @bo: TTM BO which needs the address, must be in GTT domain 184 * 185 * Tries to figure out how to access the BO through the AGP aperture. Returns 186 * AMDGPU_BO_INVALID_OFFSET if that is not possible. 187 */ 188 uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo) 189 { 190 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 191 192 if (!bo->ttm) 193 return AMDGPU_BO_INVALID_OFFSET; 194 195 if (bo->ttm->num_pages != 1 || bo->ttm->caching == ttm_cached) 196 return AMDGPU_BO_INVALID_OFFSET; 197 198 if (bo->ttm->dma_address[0] + PAGE_SIZE >= adev->gmc.agp_size) 199 return AMDGPU_BO_INVALID_OFFSET; 200 201 return adev->gmc.agp_start + bo->ttm->dma_address[0]; 202 } 203 204 /** 205 * amdgpu_gmc_vram_location - try to find VRAM location 206 * 207 * @adev: amdgpu device structure holding all necessary information 208 * @mc: memory controller structure holding memory information 209 * @base: base address at which to put VRAM 210 * 211 * Function will try to place VRAM at base address provided 212 * as parameter. 213 */ 214 void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc, 215 u64 base) 216 { 217 uint64_t vis_limit = (uint64_t)amdgpu_vis_vram_limit << 20; 218 uint64_t limit = (uint64_t)amdgpu_vram_limit << 20; 219 220 mc->vram_start = base; 221 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 222 if (limit < mc->real_vram_size) 223 mc->real_vram_size = limit; 224 225 if (vis_limit && vis_limit < mc->visible_vram_size) 226 mc->visible_vram_size = vis_limit; 227 228 if (mc->real_vram_size < mc->visible_vram_size) 229 mc->visible_vram_size = mc->real_vram_size; 230 231 if (mc->xgmi.num_physical_nodes == 0) { 232 mc->fb_start = mc->vram_start; 233 mc->fb_end = mc->vram_end; 234 } 235 dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", 236 mc->mc_vram_size >> 20, mc->vram_start, 237 mc->vram_end, mc->real_vram_size >> 20); 238 } 239 240 /** amdgpu_gmc_sysvm_location - place vram and gart in sysvm aperture 241 * 242 * @adev: amdgpu device structure holding all necessary information 243 * @mc: memory controller structure holding memory information 244 * 245 * This function is only used if use GART for FB translation. In such 246 * case, we use sysvm aperture (vmid0 page tables) for both vram 247 * and gart (aka system memory) access. 248 * 249 * GPUVM (and our organization of vmid0 page tables) require sysvm 250 * aperture to be placed at a location aligned with 8 times of native 251 * page size. For example, if vm_context0_cntl.page_table_block_size 252 * is 12, then native page size is 8G (2M*2^12), sysvm should start 253 * with a 64G aligned address. For simplicity, we just put sysvm at 254 * address 0. So vram start at address 0 and gart is right after vram. 255 */ 256 void amdgpu_gmc_sysvm_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc) 257 { 258 u64 hive_vram_start = 0; 259 u64 hive_vram_end = mc->xgmi.node_segment_size * mc->xgmi.num_physical_nodes - 1; 260 mc->vram_start = mc->xgmi.node_segment_size * mc->xgmi.physical_node_id; 261 mc->vram_end = mc->vram_start + mc->xgmi.node_segment_size - 1; 262 /* node_segment_size may not 4GB aligned on SRIOV, align up is needed. */ 263 mc->gart_start = ALIGN(hive_vram_end + 1, four_gb); 264 mc->gart_end = mc->gart_start + mc->gart_size - 1; 265 if (amdgpu_virt_xgmi_migrate_enabled(adev)) { 266 /* set mc->vram_start to 0 to switch the returned GPU address of 267 * amdgpu_bo_create_reserved() from FB aperture to GART aperture. 268 */ 269 mc->vram_start = 0; 270 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 271 mc->visible_vram_size = min(mc->visible_vram_size, mc->real_vram_size); 272 } else { 273 mc->fb_start = hive_vram_start; 274 mc->fb_end = hive_vram_end; 275 } 276 dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", 277 mc->mc_vram_size >> 20, mc->vram_start, 278 mc->vram_end, mc->real_vram_size >> 20); 279 dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n", 280 mc->gart_size >> 20, mc->gart_start, mc->gart_end); 281 } 282 283 /** 284 * amdgpu_gmc_gart_location - try to find GART location 285 * 286 * @adev: amdgpu device structure holding all necessary information 287 * @mc: memory controller structure holding memory information 288 * @gart_placement: GART placement policy with respect to VRAM 289 * 290 * Function will try to place GART before or after VRAM. 291 * If GART size is bigger than space left then we ajust GART size. 292 * Thus function will never fails. 293 */ 294 void amdgpu_gmc_gart_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc, 295 enum amdgpu_gart_placement gart_placement) 296 { 297 u64 size_af, size_bf; 298 /*To avoid the hole, limit the max mc address to AMDGPU_GMC_HOLE_START*/ 299 u64 max_mc_address = min(adev->gmc.mc_mask, AMDGPU_GMC_HOLE_START - 1); 300 301 /* VCE doesn't like it when BOs cross a 4GB segment, so align 302 * the GART base on a 4GB boundary as well. 303 */ 304 size_bf = mc->fb_start; 305 size_af = max_mc_address + 1 - ALIGN(mc->fb_end + 1, four_gb); 306 307 if (mc->gart_size > max(size_bf, size_af)) { 308 dev_warn(adev->dev, "limiting GART\n"); 309 mc->gart_size = max(size_bf, size_af); 310 } 311 312 switch (gart_placement) { 313 case AMDGPU_GART_PLACEMENT_HIGH: 314 mc->gart_start = max_mc_address - mc->gart_size + 1; 315 break; 316 case AMDGPU_GART_PLACEMENT_LOW: 317 mc->gart_start = 0; 318 break; 319 case AMDGPU_GART_PLACEMENT_BEST_FIT: 320 default: 321 if ((size_bf >= mc->gart_size && size_bf < size_af) || 322 (size_af < mc->gart_size)) 323 mc->gart_start = 0; 324 else 325 mc->gart_start = max_mc_address - mc->gart_size + 1; 326 break; 327 } 328 329 mc->gart_start &= ~(four_gb - 1); 330 mc->gart_end = mc->gart_start + mc->gart_size - 1; 331 dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n", 332 mc->gart_size >> 20, mc->gart_start, mc->gart_end); 333 } 334 335 /** 336 * amdgpu_gmc_agp_location - try to find AGP location 337 * @adev: amdgpu device structure holding all necessary information 338 * @mc: memory controller structure holding memory information 339 * 340 * Function will place try to find a place for the AGP BAR in the MC address 341 * space. 342 * 343 * AGP BAR will be assigned the largest available hole in the address space. 344 * Should be called after VRAM and GART locations are setup. 345 */ 346 void amdgpu_gmc_agp_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc) 347 { 348 const uint64_t sixteen_gb = 1ULL << 34; 349 const uint64_t sixteen_gb_mask = ~(sixteen_gb - 1); 350 u64 size_af, size_bf; 351 352 if (mc->fb_start > mc->gart_start) { 353 size_bf = (mc->fb_start & sixteen_gb_mask) - 354 ALIGN(mc->gart_end + 1, sixteen_gb); 355 size_af = mc->mc_mask + 1 - ALIGN(mc->fb_end + 1, sixteen_gb); 356 } else { 357 size_bf = mc->fb_start & sixteen_gb_mask; 358 size_af = (mc->gart_start & sixteen_gb_mask) - 359 ALIGN(mc->fb_end + 1, sixteen_gb); 360 } 361 362 if (size_bf > size_af) { 363 mc->agp_start = (mc->fb_start - size_bf) & sixteen_gb_mask; 364 mc->agp_size = size_bf; 365 } else { 366 mc->agp_start = ALIGN(mc->fb_end + 1, sixteen_gb); 367 mc->agp_size = size_af; 368 } 369 370 mc->agp_end = mc->agp_start + mc->agp_size - 1; 371 dev_info(adev->dev, "AGP: %lluM 0x%016llX - 0x%016llX\n", 372 mc->agp_size >> 20, mc->agp_start, mc->agp_end); 373 } 374 375 /** 376 * amdgpu_gmc_set_agp_default - Set the default AGP aperture value. 377 * @adev: amdgpu device structure holding all necessary information 378 * @mc: memory controller structure holding memory information 379 * 380 * To disable the AGP aperture, you need to set the start to a larger 381 * value than the end. This function sets the default value which 382 * can then be overridden using amdgpu_gmc_agp_location() if you want 383 * to enable the AGP aperture on a specific chip. 384 * 385 */ 386 void amdgpu_gmc_set_agp_default(struct amdgpu_device *adev, 387 struct amdgpu_gmc *mc) 388 { 389 mc->agp_start = 0xffffffffffff; 390 mc->agp_end = 0; 391 mc->agp_size = 0; 392 } 393 394 /** 395 * amdgpu_gmc_fault_key - get hask key from vm fault address and pasid 396 * 397 * @addr: 48 bit physical address, page aligned (36 significant bits) 398 * @pasid: 16 bit process address space identifier 399 */ 400 static inline uint64_t amdgpu_gmc_fault_key(uint64_t addr, uint16_t pasid) 401 { 402 return addr << 4 | pasid; 403 } 404 405 /** 406 * amdgpu_gmc_filter_faults - filter VM faults 407 * 408 * @adev: amdgpu device structure 409 * @ih: interrupt ring that the fault received from 410 * @addr: address of the VM fault 411 * @pasid: PASID of the process causing the fault 412 * @timestamp: timestamp of the fault 413 * 414 * Returns: 415 * True if the fault was filtered and should not be processed further. 416 * False if the fault is a new one and needs to be handled. 417 */ 418 bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, 419 struct amdgpu_ih_ring *ih, uint64_t addr, 420 uint16_t pasid, uint64_t timestamp) 421 { 422 struct amdgpu_gmc *gmc = &adev->gmc; 423 uint64_t stamp, key = amdgpu_gmc_fault_key(addr, pasid); 424 struct amdgpu_gmc_fault *fault; 425 uint32_t hash; 426 427 /* Stale retry fault if timestamp goes backward */ 428 if (amdgpu_ih_ts_after(timestamp, ih->processed_timestamp)) 429 return true; 430 431 /* If we don't have space left in the ring buffer return immediately */ 432 stamp = max(timestamp, AMDGPU_GMC_FAULT_TIMEOUT + 1) - 433 AMDGPU_GMC_FAULT_TIMEOUT; 434 if (gmc->fault_ring[gmc->last_fault].timestamp >= stamp) 435 return true; 436 437 /* Try to find the fault in the hash */ 438 hash = hash_64(key, AMDGPU_GMC_FAULT_HASH_ORDER); 439 fault = &gmc->fault_ring[gmc->fault_hash[hash].idx]; 440 while (fault->timestamp >= stamp) { 441 uint64_t tmp; 442 443 if (atomic64_read(&fault->key) == key) { 444 /* 445 * if we get a fault which is already present in 446 * the fault_ring and the timestamp of 447 * the fault is after the expired timestamp, 448 * then this is a new fault that needs to be added 449 * into the fault ring. 450 */ 451 if (fault->timestamp_expiry != 0 && 452 amdgpu_ih_ts_after(fault->timestamp_expiry, 453 timestamp)) 454 break; 455 else 456 return true; 457 } 458 459 tmp = fault->timestamp; 460 fault = &gmc->fault_ring[fault->next]; 461 462 /* Check if the entry was reused */ 463 if (fault->timestamp >= tmp) 464 break; 465 } 466 467 /* Add the fault to the ring */ 468 fault = &gmc->fault_ring[gmc->last_fault]; 469 atomic64_set(&fault->key, key); 470 fault->timestamp = timestamp; 471 472 /* And update the hash */ 473 fault->next = gmc->fault_hash[hash].idx; 474 gmc->fault_hash[hash].idx = gmc->last_fault++; 475 return false; 476 } 477 478 /** 479 * amdgpu_gmc_filter_faults_remove - remove address from VM faults filter 480 * 481 * @adev: amdgpu device structure 482 * @addr: address of the VM fault 483 * @pasid: PASID of the process causing the fault 484 * 485 * Remove the address from fault filter, then future vm fault on this address 486 * will pass to retry fault handler to recover. 487 */ 488 void amdgpu_gmc_filter_faults_remove(struct amdgpu_device *adev, uint64_t addr, 489 uint16_t pasid) 490 { 491 struct amdgpu_gmc *gmc = &adev->gmc; 492 uint64_t key = amdgpu_gmc_fault_key(addr, pasid); 493 struct amdgpu_ih_ring *ih; 494 struct amdgpu_gmc_fault *fault; 495 uint32_t last_wptr; 496 uint64_t last_ts; 497 uint32_t hash; 498 uint64_t tmp; 499 500 if (adev->irq.retry_cam_enabled) 501 return; 502 else if (adev->irq.ih1.ring_size) 503 ih = &adev->irq.ih1; 504 else if (adev->irq.ih_soft.enabled) 505 ih = &adev->irq.ih_soft; 506 else 507 return; 508 509 /* Get the WPTR of the last entry in IH ring */ 510 last_wptr = amdgpu_ih_get_wptr(adev, ih); 511 /* Order wptr with ring data. */ 512 rmb(); 513 /* Get the timetamp of the last entry in IH ring */ 514 last_ts = amdgpu_ih_decode_iv_ts(adev, ih, last_wptr, -1); 515 516 hash = hash_64(key, AMDGPU_GMC_FAULT_HASH_ORDER); 517 fault = &gmc->fault_ring[gmc->fault_hash[hash].idx]; 518 do { 519 if (atomic64_read(&fault->key) == key) { 520 /* 521 * Update the timestamp when this fault 522 * expired. 523 */ 524 fault->timestamp_expiry = last_ts; 525 break; 526 } 527 528 tmp = fault->timestamp; 529 fault = &gmc->fault_ring[fault->next]; 530 } while (fault->timestamp < tmp); 531 } 532 533 int amdgpu_gmc_handle_retry_fault(struct amdgpu_device *adev, 534 struct amdgpu_iv_entry *entry, 535 u64 addr, 536 u32 cam_index, 537 u32 node_id, 538 bool write_fault) 539 { 540 int ret; 541 542 if (adev->irq.retry_cam_enabled) { 543 /* Delegate it to a different ring if the hardware hasn't 544 * already done it. 545 */ 546 if (entry->ih == &adev->irq.ih) { 547 amdgpu_irq_delegate(adev, entry, 8); 548 return 1; 549 } 550 551 ret = amdgpu_vm_handle_fault(adev, entry->pasid, entry->vmid, node_id, 552 addr, entry->timestamp, write_fault); 553 WDOORBELL32(adev->irq.retry_cam_doorbell_index, cam_index); 554 if (ret) 555 return 1; 556 } else { 557 /* Process it only if it's the first fault for this address */ 558 if (entry->ih != &adev->irq.ih_soft && 559 amdgpu_gmc_filter_faults(adev, entry->ih, addr, entry->pasid, 560 entry->timestamp)) 561 return 1; 562 563 /* Delegate it to a different ring if the hardware hasn't 564 * already done it. 565 */ 566 if (entry->ih == &adev->irq.ih) { 567 amdgpu_irq_delegate(adev, entry, 8); 568 return 1; 569 } 570 571 /* Try to handle the recoverable page faults by filling page 572 * tables 573 */ 574 if (amdgpu_vm_handle_fault(adev, entry->pasid, entry->vmid, node_id, 575 addr, entry->timestamp, write_fault)) 576 return 1; 577 } 578 return 0; 579 } 580 581 int amdgpu_gmc_ras_sw_init(struct amdgpu_device *adev) 582 { 583 int r; 584 585 /* umc ras block */ 586 r = amdgpu_umc_ras_sw_init(adev); 587 if (r) 588 return r; 589 590 /* mmhub ras block */ 591 r = amdgpu_mmhub_ras_sw_init(adev); 592 if (r) 593 return r; 594 595 /* hdp ras block */ 596 r = amdgpu_hdp_ras_sw_init(adev); 597 if (r) 598 return r; 599 600 /* mca.x ras block */ 601 r = amdgpu_mca_mp0_ras_sw_init(adev); 602 if (r) 603 return r; 604 605 r = amdgpu_mca_mp1_ras_sw_init(adev); 606 if (r) 607 return r; 608 609 r = amdgpu_mca_mpio_ras_sw_init(adev); 610 if (r) 611 return r; 612 613 /* xgmi ras block */ 614 r = amdgpu_xgmi_ras_sw_init(adev); 615 if (r) 616 return r; 617 618 return 0; 619 } 620 621 int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev) 622 { 623 return 0; 624 } 625 626 void amdgpu_gmc_ras_fini(struct amdgpu_device *adev) 627 { 628 629 } 630 631 /* 632 * The latest engine allocation on gfx9/10 is: 633 * Engine 2, 3: firmware 634 * Engine 0, 1, 4~16: amdgpu ring, 635 * subject to change when ring number changes 636 * Engine 17: Gart flushes 637 */ 638 #define AMDGPU_VMHUB_INV_ENG_BITMAP 0x1FFF3 639 640 int amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_device *adev) 641 { 642 struct amdgpu_ring *ring; 643 unsigned vm_inv_engs[AMDGPU_MAX_VMHUBS] = {0}; 644 unsigned i; 645 unsigned vmhub, inv_eng; 646 struct amdgpu_ring *shared_ring; 647 648 /* init the vm inv eng for all vmhubs */ 649 for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 650 vm_inv_engs[i] = AMDGPU_VMHUB_INV_ENG_BITMAP; 651 /* reserve engine 5 for firmware */ 652 if (adev->enable_mes) 653 vm_inv_engs[i] &= ~(1 << 5); 654 /* reserve engine 6 for uni mes */ 655 if (adev->enable_uni_mes) 656 vm_inv_engs[i] &= ~(1 << 6); 657 /* reserve mmhub engine 3 for firmware */ 658 if (adev->enable_umsch_mm) 659 vm_inv_engs[i] &= ~(1 << 3); 660 } 661 662 for (i = 0; i < adev->num_rings; ++i) { 663 ring = adev->rings[i]; 664 vmhub = ring->vm_hub; 665 666 if (ring == &adev->mes.ring[0] || 667 ring == &adev->mes.ring[1] || 668 ring == &adev->umsch_mm.ring || 669 ring == &adev->cper.ring_buf) 670 continue; 671 672 /* Skip if the ring is a shared ring */ 673 if (amdgpu_sdma_is_shared_inv_eng(adev, ring)) 674 continue; 675 676 inv_eng = ffs(vm_inv_engs[vmhub]); 677 if (!inv_eng) { 678 dev_err(adev->dev, "no VM inv eng for ring %s\n", 679 ring->name); 680 return -EINVAL; 681 } 682 683 ring->vm_inv_eng = inv_eng - 1; 684 vm_inv_engs[vmhub] &= ~(1 << ring->vm_inv_eng); 685 686 dev_info(adev->dev, "ring %s uses VM inv eng %u on hub %u\n", 687 ring->name, ring->vm_inv_eng, ring->vm_hub); 688 /* SDMA has a special packet which allows it to use the same 689 * invalidation engine for all the rings in one instance. 690 * Therefore, we do not allocate a separate VM invalidation engine 691 * for SDMA page rings. Instead, they share the VM invalidation 692 * engine with the SDMA gfx ring. This change ensures efficient 693 * resource management and avoids the issue of insufficient VM 694 * invalidation engines. 695 */ 696 shared_ring = amdgpu_sdma_get_shared_ring(adev, ring); 697 if (shared_ring) { 698 shared_ring->vm_inv_eng = ring->vm_inv_eng; 699 dev_info(adev->dev, "ring %s shares VM invalidation engine %u with ring %s on hub %u\n", 700 ring->name, ring->vm_inv_eng, shared_ring->name, ring->vm_hub); 701 continue; 702 } 703 } 704 705 return 0; 706 } 707 708 void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 709 uint32_t vmhub, uint32_t flush_type) 710 { 711 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 712 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 713 struct dma_fence *fence; 714 struct amdgpu_job *job; 715 int r; 716 717 if (!hub->sdma_invalidation_workaround || vmid || 718 !adev->mman.buffer_funcs_enabled || !adev->ib_pool_ready || 719 !ring->sched.ready) { 720 /* 721 * A GPU reset should flush all TLBs anyway, so no need to do 722 * this while one is ongoing. 723 */ 724 if (!down_read_trylock(&adev->reset_domain->sem)) 725 return; 726 727 if (adev->gmc.flush_tlb_needs_extra_type_2) 728 adev->gmc.gmc_funcs->flush_gpu_tlb(adev, vmid, 729 vmhub, 2); 730 731 if (adev->gmc.flush_tlb_needs_extra_type_0 && flush_type == 2) 732 adev->gmc.gmc_funcs->flush_gpu_tlb(adev, vmid, 733 vmhub, 0); 734 735 adev->gmc.gmc_funcs->flush_gpu_tlb(adev, vmid, vmhub, 736 flush_type); 737 up_read(&adev->reset_domain->sem); 738 return; 739 } 740 741 /* The SDMA on Navi 1x has a bug which can theoretically result in memory 742 * corruption if an invalidation happens at the same time as an VA 743 * translation. Avoid this by doing the invalidation from the SDMA 744 * itself at least for GART. 745 */ 746 mutex_lock(&adev->mman.default_entity.lock); 747 r = amdgpu_job_alloc_with_ib(ring->adev, &adev->mman.default_entity.base, 748 AMDGPU_FENCE_OWNER_UNDEFINED, 749 16 * 4, AMDGPU_IB_POOL_IMMEDIATE, 750 &job, AMDGPU_KERNEL_JOB_ID_FLUSH_GPU_TLB); 751 if (r) 752 goto error_alloc; 753 754 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo); 755 job->vm_needs_flush = true; 756 job->ibs->ptr[job->ibs->length_dw++] = ring->funcs->nop; 757 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 758 fence = amdgpu_job_submit(job); 759 mutex_unlock(&adev->mman.default_entity.lock); 760 761 dma_fence_wait(fence, false); 762 dma_fence_put(fence); 763 764 return; 765 766 error_alloc: 767 mutex_unlock(&adev->mman.default_entity.lock); 768 dev_err(adev->dev, "Error flushing GPU TLB using the SDMA (%d)!\n", r); 769 } 770 771 int amdgpu_gmc_flush_gpu_tlb_pasid(struct amdgpu_device *adev, uint16_t pasid, 772 uint32_t flush_type, bool all_hub, 773 uint32_t inst) 774 { 775 struct amdgpu_ring *ring = &adev->gfx.kiq[inst].ring; 776 struct amdgpu_kiq *kiq = &adev->gfx.kiq[inst]; 777 unsigned int ndw; 778 int r, cnt = 0; 779 uint32_t seq; 780 781 /* 782 * A GPU reset should flush all TLBs anyway, so no need to do 783 * this while one is ongoing. 784 */ 785 if (!down_read_trylock(&adev->reset_domain->sem)) 786 return 0; 787 788 if (!adev->gmc.flush_pasid_uses_kiq || !ring->sched.ready) { 789 790 if (!adev->gmc.gmc_funcs->flush_gpu_tlb_pasid) { 791 r = 0; 792 goto error_unlock_reset; 793 } 794 795 if (adev->gmc.flush_tlb_needs_extra_type_2) 796 adev->gmc.gmc_funcs->flush_gpu_tlb_pasid(adev, pasid, 797 2, all_hub, 798 inst); 799 800 if (adev->gmc.flush_tlb_needs_extra_type_0 && flush_type == 2) 801 adev->gmc.gmc_funcs->flush_gpu_tlb_pasid(adev, pasid, 802 0, all_hub, 803 inst); 804 805 adev->gmc.gmc_funcs->flush_gpu_tlb_pasid(adev, pasid, 806 flush_type, all_hub, 807 inst); 808 r = 0; 809 } else { 810 /* 2 dwords flush + 8 dwords fence */ 811 ndw = kiq->pmf->invalidate_tlbs_size + 8; 812 813 if (adev->gmc.flush_tlb_needs_extra_type_2) 814 ndw += kiq->pmf->invalidate_tlbs_size; 815 816 if (adev->gmc.flush_tlb_needs_extra_type_0) 817 ndw += kiq->pmf->invalidate_tlbs_size; 818 819 spin_lock(&adev->gfx.kiq[inst].ring_lock); 820 r = amdgpu_ring_alloc(ring, ndw); 821 if (r) { 822 spin_unlock(&adev->gfx.kiq[inst].ring_lock); 823 goto error_unlock_reset; 824 } 825 if (adev->gmc.flush_tlb_needs_extra_type_2) 826 kiq->pmf->kiq_invalidate_tlbs(ring, pasid, 2, all_hub); 827 828 if (flush_type == 2 && adev->gmc.flush_tlb_needs_extra_type_0) 829 kiq->pmf->kiq_invalidate_tlbs(ring, pasid, 0, all_hub); 830 831 kiq->pmf->kiq_invalidate_tlbs(ring, pasid, flush_type, all_hub); 832 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT); 833 if (r) { 834 amdgpu_ring_undo(ring); 835 spin_unlock(&adev->gfx.kiq[inst].ring_lock); 836 goto error_unlock_reset; 837 } 838 839 amdgpu_ring_commit(ring); 840 spin_unlock(&adev->gfx.kiq[inst].ring_lock); 841 842 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); 843 844 might_sleep(); 845 while (r < 1 && cnt++ < MAX_KIQ_REG_TRY && 846 !amdgpu_reset_pending(adev->reset_domain)) { 847 msleep(MAX_KIQ_REG_BAILOUT_INTERVAL); 848 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); 849 } 850 851 if (cnt > MAX_KIQ_REG_TRY) { 852 dev_err(adev->dev, "timeout waiting for kiq fence\n"); 853 r = -ETIME; 854 } else 855 r = 0; 856 } 857 858 error_unlock_reset: 859 up_read(&adev->reset_domain->sem); 860 return r; 861 } 862 863 void amdgpu_gmc_fw_reg_write_reg_wait(struct amdgpu_device *adev, 864 uint32_t reg0, uint32_t reg1, 865 uint32_t ref, uint32_t mask, 866 uint32_t xcc_inst) 867 { 868 struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_inst]; 869 struct amdgpu_ring *ring = &kiq->ring; 870 signed long r, cnt = 0; 871 unsigned long flags; 872 uint32_t seq; 873 874 if (adev->mes.ring[MES_PIPE_INST(xcc_inst, 0)].sched.ready) { 875 amdgpu_mes_reg_write_reg_wait(adev, reg0, reg1, 876 ref, mask, xcc_inst); 877 return; 878 } 879 880 spin_lock_irqsave(&kiq->ring_lock, flags); 881 amdgpu_ring_alloc(ring, 32); 882 amdgpu_ring_emit_reg_write_reg_wait(ring, reg0, reg1, 883 ref, mask); 884 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT); 885 if (r) 886 goto failed_undo; 887 888 amdgpu_ring_commit(ring); 889 spin_unlock_irqrestore(&kiq->ring_lock, flags); 890 891 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); 892 893 /* don't wait anymore for IRQ context */ 894 if (r < 1 && in_interrupt()) 895 goto failed_kiq; 896 897 might_sleep(); 898 while (r < 1 && cnt++ < MAX_KIQ_REG_TRY && 899 !amdgpu_reset_pending(adev->reset_domain)) { 900 901 msleep(MAX_KIQ_REG_BAILOUT_INTERVAL); 902 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); 903 } 904 905 if (cnt > MAX_KIQ_REG_TRY) 906 goto failed_kiq; 907 908 return; 909 910 failed_undo: 911 amdgpu_ring_undo(ring); 912 spin_unlock_irqrestore(&kiq->ring_lock, flags); 913 failed_kiq: 914 dev_err(adev->dev, "failed to write reg %x wait reg %x\n", reg0, reg1); 915 } 916 917 /** 918 * amdgpu_gmc_tmz_set -- check and set if a device supports TMZ 919 * @adev: amdgpu_device pointer 920 * 921 * Check and set if an the device @adev supports Trusted Memory 922 * Zones (TMZ). 923 */ 924 void amdgpu_gmc_tmz_set(struct amdgpu_device *adev) 925 { 926 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 927 /* RAVEN */ 928 case IP_VERSION(9, 2, 2): 929 case IP_VERSION(9, 1, 0): 930 /* RENOIR looks like RAVEN */ 931 case IP_VERSION(9, 3, 0): 932 /* GC 10.3.7 */ 933 case IP_VERSION(10, 3, 7): 934 /* GC 11.0.1 */ 935 case IP_VERSION(11, 0, 1): 936 if (amdgpu_tmz == 0) { 937 adev->gmc.tmz_enabled = false; 938 dev_info(adev->dev, 939 "Trusted Memory Zone (TMZ) feature disabled (cmd line)\n"); 940 } else { 941 adev->gmc.tmz_enabled = true; 942 dev_info(adev->dev, 943 "Trusted Memory Zone (TMZ) feature enabled\n"); 944 } 945 break; 946 case IP_VERSION(10, 1, 10): 947 case IP_VERSION(10, 1, 1): 948 case IP_VERSION(10, 1, 2): 949 case IP_VERSION(10, 1, 3): 950 case IP_VERSION(10, 3, 0): 951 case IP_VERSION(10, 3, 2): 952 case IP_VERSION(10, 3, 4): 953 case IP_VERSION(10, 3, 5): 954 case IP_VERSION(10, 3, 6): 955 /* VANGOGH */ 956 case IP_VERSION(10, 3, 1): 957 /* YELLOW_CARP*/ 958 case IP_VERSION(10, 3, 3): 959 case IP_VERSION(11, 0, 4): 960 case IP_VERSION(11, 5, 0): 961 case IP_VERSION(11, 5, 1): 962 case IP_VERSION(11, 5, 2): 963 case IP_VERSION(11, 5, 3): 964 case IP_VERSION(11, 5, 4): 965 /* Don't enable it by default yet. 966 */ 967 if (amdgpu_tmz < 1) { 968 adev->gmc.tmz_enabled = false; 969 dev_info(adev->dev, 970 "Trusted Memory Zone (TMZ) feature disabled as experimental (default)\n"); 971 } else { 972 adev->gmc.tmz_enabled = true; 973 dev_info(adev->dev, 974 "Trusted Memory Zone (TMZ) feature enabled as experimental (cmd line)\n"); 975 } 976 break; 977 default: 978 adev->gmc.tmz_enabled = false; 979 dev_info(adev->dev, 980 "Trusted Memory Zone (TMZ) feature not supported\n"); 981 break; 982 } 983 } 984 985 /** 986 * amdgpu_gmc_noretry_set -- set per asic noretry defaults 987 * @adev: amdgpu_device pointer 988 * 989 * Set a per asic default for the no-retry parameter. 990 * 991 */ 992 void amdgpu_gmc_noretry_set(struct amdgpu_device *adev) 993 { 994 struct amdgpu_gmc *gmc = &adev->gmc; 995 uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0); 996 bool noretry_default = (gc_ver == IP_VERSION(9, 0, 1) || 997 gc_ver == IP_VERSION(9, 4, 0) || 998 gc_ver == IP_VERSION(9, 4, 1) || 999 gc_ver == IP_VERSION(9, 4, 2) || 1000 gc_ver == IP_VERSION(9, 4, 3) || 1001 gc_ver == IP_VERSION(9, 4, 4) || 1002 gc_ver == IP_VERSION(9, 5, 0) || 1003 gc_ver >= IP_VERSION(10, 3, 0)); 1004 1005 if (!amdgpu_sriov_xnack_support(adev)) 1006 gmc->noretry = 1; 1007 else 1008 gmc->noretry = (amdgpu_noretry == -1) ? noretry_default : amdgpu_noretry; 1009 } 1010 1011 void amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device *adev, int hub_type, 1012 bool enable) 1013 { 1014 struct amdgpu_vmhub *hub; 1015 u32 tmp, reg, i; 1016 1017 hub = &adev->vmhub[hub_type]; 1018 for (i = 0; i < 16; i++) { 1019 reg = hub->vm_context0_cntl + hub->ctx_distance * i; 1020 1021 tmp = (hub_type == AMDGPU_GFXHUB(0)) ? 1022 RREG32_SOC15_IP(GC, reg) : 1023 RREG32_SOC15_IP(MMHUB, reg); 1024 1025 if (enable) 1026 tmp |= hub->vm_cntx_cntl_vm_fault; 1027 else 1028 tmp &= ~hub->vm_cntx_cntl_vm_fault; 1029 1030 (hub_type == AMDGPU_GFXHUB(0)) ? 1031 WREG32_SOC15_IP(GC, reg, tmp) : 1032 WREG32_SOC15_IP(MMHUB, reg, tmp); 1033 } 1034 } 1035 1036 void amdgpu_gmc_init_vga_resv_regions(struct amdgpu_device *adev) 1037 { 1038 unsigned size; 1039 1040 if (adev->gmc.is_app_apu) 1041 return; 1042 1043 /* 1044 * Some ASICs need to reserve a region of video memory to avoid access 1045 * from driver 1046 */ 1047 /* 1048 * TODO: 1049 * Currently there is a bug where some memory client outside 1050 * of the driver writes to first 8M of VRAM on S3 resume, 1051 * this overrides GART which by default gets placed in first 8M and 1052 * causes VM_FAULTS once GTT is accessed. 1053 * Keep the stolen memory reservation until the while this is not solved. 1054 */ 1055 switch (adev->asic_type) { 1056 case CHIP_VEGA10: 1057 adev->mman.keep_stolen_vga_memory = true; 1058 /* 1059 * VEGA10 SRIOV VF with MS_HYPERV host needs some firmware reserved area. 1060 */ 1061 #ifdef CONFIG_X86 1062 if (amdgpu_sriov_vf(adev) && hypervisor_is_type(X86_HYPER_MS_HYPERV)) { 1063 amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_STOLEN_RESERVED, 1064 0x500000, 0x200000, false); 1065 } 1066 #endif 1067 break; 1068 case CHIP_RAVEN: 1069 case CHIP_RENOIR: 1070 adev->mman.keep_stolen_vga_memory = true; 1071 break; 1072 case CHIP_POLARIS10: 1073 case CHIP_POLARIS11: 1074 case CHIP_POLARIS12: 1075 /* MacBookPros with switchable graphics put VRAM at 0 when 1076 * the iGPU is enabled which results in cursor issues if 1077 * the cursor ends up at 0. Reserve vram at 0 in that case. 1078 */ 1079 if (adev->gmc.vram_start == 0) 1080 adev->mman.keep_stolen_vga_memory = true; 1081 break; 1082 default: 1083 adev->mman.keep_stolen_vga_memory = false; 1084 break; 1085 } 1086 1087 if (amdgpu_sriov_vf(adev) || 1088 !amdgpu_device_has_display_hardware(adev)) { 1089 size = 0; 1090 } else { 1091 size = amdgpu_gmc_get_vbios_fb_size(adev); 1092 1093 if (adev->mman.keep_stolen_vga_memory) 1094 size = max(size, (unsigned)AMDGPU_VBIOS_VGA_ALLOCATION); 1095 } 1096 1097 /* set to 0 if the pre-OS buffer uses up most of vram */ 1098 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024)) 1099 size = 0; 1100 1101 if (size > AMDGPU_VBIOS_VGA_ALLOCATION) { 1102 amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_STOLEN_VGA, 1103 0, AMDGPU_VBIOS_VGA_ALLOCATION, false); 1104 amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_STOLEN_EXTENDED, 1105 AMDGPU_VBIOS_VGA_ALLOCATION, 1106 size - AMDGPU_VBIOS_VGA_ALLOCATION, false); 1107 } else { 1108 amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_STOLEN_VGA, 1109 0, size, false); 1110 } 1111 } 1112 1113 /** 1114 * amdgpu_gmc_init_pdb0 - initialize PDB0 1115 * 1116 * @adev: amdgpu_device pointer 1117 * 1118 * This function is only used when GART page table is used 1119 * for FB address translatioin. In such a case, we construct 1120 * a 2-level system VM page table: PDB0->PTB, to cover both 1121 * VRAM of the hive and system memory. 1122 * 1123 * PDB0 is static, initialized once on driver initialization. 1124 * The first n entries of PDB0 are used as PTE by setting 1125 * P bit to 1, pointing to VRAM. The n+1'th entry points 1126 * to a big PTB covering system memory. 1127 * 1128 */ 1129 void amdgpu_gmc_init_pdb0(struct amdgpu_device *adev) 1130 { 1131 int i; 1132 uint64_t flags = adev->gart.gart_pte_flags; //TODO it is UC. explore NC/RW? 1133 /* Each PDE0 (used as PTE) covers (2^vmid0_page_table_block_size)*2M 1134 */ 1135 u64 vram_size = adev->gmc.xgmi.node_segment_size * adev->gmc.xgmi.num_physical_nodes; 1136 u64 pde0_page_size = (1ULL<<adev->gmc.vmid0_page_table_block_size)<<21; 1137 u64 vram_addr, vram_end; 1138 u64 gart_ptb_gpu_pa = amdgpu_gmc_vram_pa(adev, adev->gart.bo); 1139 int idx; 1140 1141 if (!drm_dev_enter(adev_to_drm(adev), &idx)) 1142 return; 1143 1144 flags |= AMDGPU_PTE_VALID | AMDGPU_PTE_READABLE; 1145 flags |= AMDGPU_PTE_WRITEABLE; 1146 flags |= AMDGPU_PTE_SNOOPED; 1147 flags |= AMDGPU_PTE_FRAG((adev->gmc.vmid0_page_table_block_size + 9*1)); 1148 flags |= AMDGPU_PDE_PTE_FLAG(adev); 1149 1150 vram_addr = adev->vm_manager.vram_base_offset; 1151 if (!amdgpu_virt_xgmi_migrate_enabled(adev)) 1152 vram_addr -= adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 1153 vram_end = vram_addr + vram_size; 1154 1155 /* The first n PDE0 entries are used as PTE, 1156 * pointing to vram 1157 */ 1158 for (i = 0; vram_addr < vram_end; i++, vram_addr += pde0_page_size) 1159 amdgpu_gmc_set_pte_pde(adev, adev->gmc.ptr_pdb0, i, vram_addr, flags); 1160 1161 /* The n+1'th PDE0 entry points to a huge 1162 * PTB who has more than 512 entries each 1163 * pointing to a 4K system page 1164 */ 1165 flags = AMDGPU_PTE_VALID; 1166 flags |= AMDGPU_PTE_SNOOPED | AMDGPU_PDE_BFS_FLAG(adev, 0); 1167 /* Requires gart_ptb_gpu_pa to be 4K aligned */ 1168 amdgpu_gmc_set_pte_pde(adev, adev->gmc.ptr_pdb0, i, gart_ptb_gpu_pa, flags); 1169 drm_dev_exit(idx); 1170 } 1171 1172 /** 1173 * amdgpu_gmc_vram_mc2pa - calculate vram buffer's physical address from MC 1174 * address 1175 * 1176 * @adev: amdgpu_device pointer 1177 * @mc_addr: MC address of buffer 1178 */ 1179 uint64_t amdgpu_gmc_vram_mc2pa(struct amdgpu_device *adev, uint64_t mc_addr) 1180 { 1181 return mc_addr - adev->gmc.vram_start + adev->vm_manager.vram_base_offset; 1182 } 1183 1184 /** 1185 * amdgpu_gmc_vram_pa - calculate vram buffer object's physical address from 1186 * GPU's view 1187 * 1188 * @adev: amdgpu_device pointer 1189 * @bo: amdgpu buffer object 1190 */ 1191 uint64_t amdgpu_gmc_vram_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo) 1192 { 1193 return amdgpu_gmc_vram_mc2pa(adev, amdgpu_bo_gpu_offset(bo)); 1194 } 1195 1196 int amdgpu_gmc_vram_checking(struct amdgpu_device *adev) 1197 { 1198 struct amdgpu_bo *vram_bo = NULL; 1199 uint64_t vram_gpu = 0; 1200 void *vram_ptr = NULL; 1201 1202 int ret, size = 0x100000; 1203 uint8_t cptr[10]; 1204 1205 ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE, 1206 AMDGPU_GEM_DOMAIN_VRAM, 1207 &vram_bo, 1208 &vram_gpu, 1209 &vram_ptr); 1210 if (ret) 1211 return ret; 1212 1213 memset(vram_ptr, 0x86, size); 1214 memset(cptr, 0x86, 10); 1215 1216 /** 1217 * Check the start, the mid, and the end of the memory if the content of 1218 * each byte is the pattern "0x86". If yes, we suppose the vram bo is 1219 * workable. 1220 * 1221 * Note: If check the each byte of whole 1M bo, it will cost too many 1222 * seconds, so here, we just pick up three parts for emulation. 1223 */ 1224 ret = memcmp(vram_ptr, cptr, 10); 1225 if (ret) { 1226 ret = -EIO; 1227 goto release_buffer; 1228 } 1229 1230 ret = memcmp(vram_ptr + (size / 2), cptr, 10); 1231 if (ret) { 1232 ret = -EIO; 1233 goto release_buffer; 1234 } 1235 1236 ret = memcmp(vram_ptr + size - 10, cptr, 10); 1237 if (ret) { 1238 ret = -EIO; 1239 goto release_buffer; 1240 } 1241 1242 release_buffer: 1243 amdgpu_bo_free_kernel(&vram_bo, &vram_gpu, 1244 &vram_ptr); 1245 1246 return ret; 1247 } 1248 1249 static const char *nps_desc[] = { 1250 [AMDGPU_NPS1_PARTITION_MODE] = "NPS1", 1251 [AMDGPU_NPS2_PARTITION_MODE] = "NPS2", 1252 [AMDGPU_NPS3_PARTITION_MODE] = "NPS3", 1253 [AMDGPU_NPS4_PARTITION_MODE] = "NPS4", 1254 [AMDGPU_NPS6_PARTITION_MODE] = "NPS6", 1255 [AMDGPU_NPS8_PARTITION_MODE] = "NPS8", 1256 }; 1257 1258 static ssize_t available_memory_partition_show(struct device *dev, 1259 struct device_attribute *addr, 1260 char *buf) 1261 { 1262 struct drm_device *ddev = dev_get_drvdata(dev); 1263 struct amdgpu_device *adev = drm_to_adev(ddev); 1264 int size = 0, mode; 1265 char *sep = ""; 1266 1267 for_each_inst(mode, adev->gmc.supported_nps_modes) { 1268 size += sysfs_emit_at(buf, size, "%s%s", sep, nps_desc[mode]); 1269 sep = ", "; 1270 } 1271 size += sysfs_emit_at(buf, size, "\n"); 1272 1273 return size; 1274 } 1275 1276 static ssize_t current_memory_partition_store(struct device *dev, 1277 struct device_attribute *attr, 1278 const char *buf, size_t count) 1279 { 1280 struct drm_device *ddev = dev_get_drvdata(dev); 1281 struct amdgpu_device *adev = drm_to_adev(ddev); 1282 enum amdgpu_memory_partition mode; 1283 struct amdgpu_hive_info *hive; 1284 int i; 1285 1286 mode = UNKNOWN_MEMORY_PARTITION_MODE; 1287 for_each_inst(i, adev->gmc.supported_nps_modes) { 1288 if (!strncasecmp(nps_desc[i], buf, strlen(nps_desc[i]))) { 1289 mode = i; 1290 break; 1291 } 1292 } 1293 1294 if (mode == UNKNOWN_MEMORY_PARTITION_MODE) 1295 return -EINVAL; 1296 1297 if (mode == adev->gmc.gmc_funcs->query_mem_partition_mode(adev)) { 1298 dev_info( 1299 adev->dev, 1300 "requested NPS mode is same as current NPS mode, skipping\n"); 1301 return count; 1302 } 1303 1304 /* If device is part of hive, all devices in the hive should request the 1305 * same mode. Hence store the requested mode in hive. 1306 */ 1307 hive = amdgpu_get_xgmi_hive(adev); 1308 if (hive) { 1309 atomic_set(&hive->requested_nps_mode, mode); 1310 amdgpu_put_xgmi_hive(hive); 1311 } else { 1312 adev->gmc.requested_nps_mode = mode; 1313 } 1314 1315 dev_info( 1316 adev->dev, 1317 "NPS mode change requested, please remove and reload the driver\n"); 1318 1319 return count; 1320 } 1321 1322 static ssize_t current_memory_partition_show( 1323 struct device *dev, struct device_attribute *addr, char *buf) 1324 { 1325 struct drm_device *ddev = dev_get_drvdata(dev); 1326 struct amdgpu_device *adev = drm_to_adev(ddev); 1327 enum amdgpu_memory_partition mode; 1328 1329 /* Only minimal precaution taken to reject requests while in reset */ 1330 if (amdgpu_in_reset(adev)) 1331 return -EPERM; 1332 1333 mode = adev->gmc.gmc_funcs->query_mem_partition_mode(adev); 1334 if ((mode >= ARRAY_SIZE(nps_desc)) || 1335 (BIT(mode) & AMDGPU_ALL_NPS_MASK) != BIT(mode)) 1336 return sysfs_emit(buf, "UNKNOWN\n"); 1337 1338 return sysfs_emit(buf, "%s\n", nps_desc[mode]); 1339 } 1340 1341 static DEVICE_ATTR_RW(current_memory_partition); 1342 static DEVICE_ATTR_RO(available_memory_partition); 1343 1344 int amdgpu_gmc_sysfs_init(struct amdgpu_device *adev) 1345 { 1346 bool nps_switch_support; 1347 int r = 0; 1348 1349 if (!adev->gmc.gmc_funcs->query_mem_partition_mode) 1350 return 0; 1351 1352 nps_switch_support = (hweight32(adev->gmc.supported_nps_modes & 1353 AMDGPU_ALL_NPS_MASK) > 1); 1354 if (!nps_switch_support) 1355 dev_attr_current_memory_partition.attr.mode &= 1356 ~(S_IWUSR | S_IWGRP | S_IWOTH); 1357 else 1358 r = device_create_file(adev->dev, 1359 &dev_attr_available_memory_partition); 1360 1361 if (r) 1362 return r; 1363 1364 return device_create_file(adev->dev, 1365 &dev_attr_current_memory_partition); 1366 } 1367 1368 void amdgpu_gmc_sysfs_fini(struct amdgpu_device *adev) 1369 { 1370 if (!adev->gmc.gmc_funcs->query_mem_partition_mode) 1371 return; 1372 1373 device_remove_file(adev->dev, &dev_attr_current_memory_partition); 1374 device_remove_file(adev->dev, &dev_attr_available_memory_partition); 1375 } 1376 1377 int amdgpu_gmc_get_nps_memranges(struct amdgpu_device *adev, 1378 struct amdgpu_mem_partition_info *mem_ranges, 1379 uint8_t *exp_ranges) 1380 { 1381 struct amdgpu_gmc_memrange ranges[AMDGPU_MAX_MEM_RANGES]; 1382 int range_cnt, ret, i, j; 1383 uint32_t nps_type; 1384 bool refresh; 1385 1386 if (!mem_ranges || !exp_ranges) 1387 return -EINVAL; 1388 range_cnt = AMDGPU_MAX_MEM_RANGES; 1389 refresh = (adev->init_lvl->level != AMDGPU_INIT_LEVEL_MINIMAL_XGMI) && 1390 (adev->gmc.reset_flags & AMDGPU_GMC_INIT_RESET_NPS); 1391 ret = amdgpu_discovery_get_nps_info(adev, &nps_type, ranges, &range_cnt, 1392 refresh); 1393 1394 if (ret) 1395 return ret; 1396 1397 /* TODO: For now, expect ranges and partition count to be the same. 1398 * Adjust if there are holes expected in any NPS domain. 1399 */ 1400 if (*exp_ranges && (range_cnt != *exp_ranges)) { 1401 dev_warn( 1402 adev->dev, 1403 "NPS config mismatch - expected ranges: %d discovery - nps mode: %d, nps ranges: %d", 1404 *exp_ranges, nps_type, range_cnt); 1405 ret = -EINVAL; 1406 goto err; 1407 } 1408 1409 for (i = 0; i < range_cnt; ++i) { 1410 if (ranges[i].base_address >= ranges[i].limit_address) { 1411 dev_warn( 1412 adev->dev, 1413 "Invalid NPS range - nps mode: %d, range[%d]: base: %llx limit: %llx", 1414 nps_type, i, ranges[i].base_address, 1415 ranges[i].limit_address); 1416 ret = -EINVAL; 1417 goto err; 1418 } 1419 1420 /* Check for overlaps, not expecting any now */ 1421 for (j = i - 1; j >= 0; j--) { 1422 if (max(ranges[j].base_address, 1423 ranges[i].base_address) <= 1424 min(ranges[j].limit_address, 1425 ranges[i].limit_address)) { 1426 dev_warn( 1427 adev->dev, 1428 "overlapping ranges detected [ %llx - %llx ] | [%llx - %llx]", 1429 ranges[j].base_address, 1430 ranges[j].limit_address, 1431 ranges[i].base_address, 1432 ranges[i].limit_address); 1433 ret = -EINVAL; 1434 goto err; 1435 } 1436 } 1437 1438 mem_ranges[i].range.fpfn = 1439 (ranges[i].base_address - 1440 adev->vm_manager.vram_base_offset) >> 1441 AMDGPU_GPU_PAGE_SHIFT; 1442 mem_ranges[i].range.lpfn = 1443 (ranges[i].limit_address - 1444 adev->vm_manager.vram_base_offset) >> 1445 AMDGPU_GPU_PAGE_SHIFT; 1446 mem_ranges[i].size = 1447 ranges[i].limit_address - ranges[i].base_address + 1; 1448 } 1449 1450 if (!*exp_ranges) 1451 *exp_ranges = range_cnt; 1452 err: 1453 return ret; 1454 } 1455 1456 int amdgpu_gmc_request_memory_partition(struct amdgpu_device *adev, 1457 int nps_mode) 1458 { 1459 /* Not supported on VF devices and APUs */ 1460 if (amdgpu_sriov_vf(adev) || (adev->flags & AMD_IS_APU)) 1461 return -EOPNOTSUPP; 1462 1463 if (!adev->psp.funcs) { 1464 dev_err(adev->dev, 1465 "PSP interface not available for nps mode change request"); 1466 return -EINVAL; 1467 } 1468 1469 return psp_memory_partition(&adev->psp, nps_mode); 1470 } 1471 1472 static inline bool amdgpu_gmc_need_nps_switch_req(struct amdgpu_device *adev, 1473 int req_nps_mode, 1474 int cur_nps_mode) 1475 { 1476 return (((BIT(req_nps_mode) & adev->gmc.supported_nps_modes) == 1477 BIT(req_nps_mode)) && 1478 req_nps_mode != cur_nps_mode); 1479 } 1480 1481 void amdgpu_gmc_prepare_nps_mode_change(struct amdgpu_device *adev) 1482 { 1483 int req_nps_mode, cur_nps_mode, r; 1484 struct amdgpu_hive_info *hive; 1485 1486 if (amdgpu_sriov_vf(adev) || !adev->gmc.supported_nps_modes || 1487 !adev->gmc.gmc_funcs->request_mem_partition_mode) 1488 return; 1489 1490 cur_nps_mode = adev->gmc.gmc_funcs->query_mem_partition_mode(adev); 1491 hive = amdgpu_get_xgmi_hive(adev); 1492 if (hive) { 1493 req_nps_mode = atomic_read(&hive->requested_nps_mode); 1494 if (!amdgpu_gmc_need_nps_switch_req(adev, req_nps_mode, 1495 cur_nps_mode)) { 1496 amdgpu_put_xgmi_hive(hive); 1497 return; 1498 } 1499 r = amdgpu_xgmi_request_nps_change(adev, hive, req_nps_mode); 1500 amdgpu_put_xgmi_hive(hive); 1501 goto out; 1502 } 1503 1504 req_nps_mode = adev->gmc.requested_nps_mode; 1505 if (!amdgpu_gmc_need_nps_switch_req(adev, req_nps_mode, cur_nps_mode)) 1506 return; 1507 1508 /* even if this fails, we should let driver unload w/o blocking */ 1509 r = adev->gmc.gmc_funcs->request_mem_partition_mode(adev, req_nps_mode); 1510 out: 1511 if (r) 1512 dev_err(adev->dev, "NPS mode change request failed\n"); 1513 else 1514 dev_info( 1515 adev->dev, 1516 "NPS mode change request done, reload driver to complete the change\n"); 1517 } 1518 1519 bool amdgpu_gmc_need_reset_on_init(struct amdgpu_device *adev) 1520 { 1521 if (adev->gmc.gmc_funcs->need_reset_on_init) 1522 return adev->gmc.gmc_funcs->need_reset_on_init(adev); 1523 1524 return false; 1525 } 1526 1527 enum amdgpu_memory_partition 1528 amdgpu_gmc_get_vf_memory_partition(struct amdgpu_device *adev) 1529 { 1530 switch (adev->gmc.num_mem_partitions) { 1531 case 0: 1532 return UNKNOWN_MEMORY_PARTITION_MODE; 1533 case 1: 1534 return AMDGPU_NPS1_PARTITION_MODE; 1535 case 2: 1536 return AMDGPU_NPS2_PARTITION_MODE; 1537 case 4: 1538 return AMDGPU_NPS4_PARTITION_MODE; 1539 case 8: 1540 return AMDGPU_NPS8_PARTITION_MODE; 1541 default: 1542 return AMDGPU_NPS1_PARTITION_MODE; 1543 } 1544 } 1545 1546 enum amdgpu_memory_partition 1547 amdgpu_gmc_get_memory_partition(struct amdgpu_device *adev, u32 *supp_modes) 1548 { 1549 enum amdgpu_memory_partition mode = UNKNOWN_MEMORY_PARTITION_MODE; 1550 1551 if (adev->nbio.funcs && 1552 adev->nbio.funcs->get_memory_partition_mode) 1553 mode = adev->nbio.funcs->get_memory_partition_mode(adev, 1554 supp_modes); 1555 else 1556 dev_warn(adev->dev, "memory partition mode query is not supported\n"); 1557 1558 return mode; 1559 } 1560 1561 enum amdgpu_memory_partition 1562 amdgpu_gmc_query_memory_partition(struct amdgpu_device *adev) 1563 { 1564 if (amdgpu_sriov_vf(adev)) 1565 return amdgpu_gmc_get_vf_memory_partition(adev); 1566 else 1567 return amdgpu_gmc_get_memory_partition(adev, NULL); 1568 } 1569 1570 static bool amdgpu_gmc_validate_partition_info(struct amdgpu_device *adev) 1571 { 1572 enum amdgpu_memory_partition mode; 1573 u32 supp_modes; 1574 bool valid; 1575 1576 mode = amdgpu_gmc_get_memory_partition(adev, &supp_modes); 1577 1578 /* Mode detected by hardware not present in supported modes */ 1579 if ((mode != UNKNOWN_MEMORY_PARTITION_MODE) && 1580 !(BIT(mode - 1) & supp_modes)) 1581 return false; 1582 1583 switch (mode) { 1584 case UNKNOWN_MEMORY_PARTITION_MODE: 1585 case AMDGPU_NPS1_PARTITION_MODE: 1586 valid = (adev->gmc.num_mem_partitions == 1); 1587 break; 1588 case AMDGPU_NPS2_PARTITION_MODE: 1589 valid = (adev->gmc.num_mem_partitions == 2); 1590 break; 1591 case AMDGPU_NPS4_PARTITION_MODE: 1592 valid = (adev->gmc.num_mem_partitions == 3 || 1593 adev->gmc.num_mem_partitions == 4); 1594 break; 1595 case AMDGPU_NPS8_PARTITION_MODE: 1596 valid = (adev->gmc.num_mem_partitions == 8); 1597 break; 1598 default: 1599 valid = false; 1600 } 1601 1602 return valid; 1603 } 1604 1605 static bool amdgpu_gmc_is_node_present(int *node_ids, int num_ids, int nid) 1606 { 1607 int i; 1608 1609 /* Check if node with id 'nid' is present in 'node_ids' array */ 1610 for (i = 0; i < num_ids; ++i) 1611 if (node_ids[i] == nid) 1612 return true; 1613 1614 return false; 1615 } 1616 1617 static void 1618 amdgpu_gmc_init_acpi_mem_ranges(struct amdgpu_device *adev, 1619 struct amdgpu_mem_partition_info *mem_ranges) 1620 { 1621 struct amdgpu_numa_info numa_info; 1622 int node_ids[AMDGPU_MAX_MEM_RANGES]; 1623 int num_ranges = 0, ret; 1624 int num_xcc, xcc_id; 1625 uint32_t xcc_mask; 1626 1627 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1628 xcc_mask = (1U << num_xcc) - 1; 1629 1630 for_each_inst(xcc_id, xcc_mask) { 1631 ret = amdgpu_acpi_get_mem_info(adev, xcc_id, &numa_info); 1632 if (ret) 1633 continue; 1634 1635 if (numa_info.nid == NUMA_NO_NODE) { 1636 mem_ranges[0].size = numa_info.size; 1637 mem_ranges[0].numa.node = numa_info.nid; 1638 num_ranges = 1; 1639 break; 1640 } 1641 1642 if (amdgpu_gmc_is_node_present(node_ids, num_ranges, 1643 numa_info.nid)) 1644 continue; 1645 1646 node_ids[num_ranges] = numa_info.nid; 1647 mem_ranges[num_ranges].numa.node = numa_info.nid; 1648 mem_ranges[num_ranges].size = numa_info.size; 1649 ++num_ranges; 1650 } 1651 1652 adev->gmc.num_mem_partitions = num_ranges; 1653 } 1654 1655 void amdgpu_gmc_init_sw_mem_ranges(struct amdgpu_device *adev, 1656 struct amdgpu_mem_partition_info *mem_ranges) 1657 { 1658 enum amdgpu_memory_partition mode; 1659 u32 start_addr = 0, size; 1660 int i, r, l; 1661 1662 mode = amdgpu_gmc_query_memory_partition(adev); 1663 1664 switch (mode) { 1665 case UNKNOWN_MEMORY_PARTITION_MODE: 1666 adev->gmc.num_mem_partitions = 0; 1667 break; 1668 case AMDGPU_NPS1_PARTITION_MODE: 1669 adev->gmc.num_mem_partitions = 1; 1670 break; 1671 case AMDGPU_NPS2_PARTITION_MODE: 1672 adev->gmc.num_mem_partitions = 2; 1673 break; 1674 case AMDGPU_NPS4_PARTITION_MODE: 1675 if (adev->flags & AMD_IS_APU) 1676 adev->gmc.num_mem_partitions = 3; 1677 else 1678 adev->gmc.num_mem_partitions = 4; 1679 break; 1680 case AMDGPU_NPS8_PARTITION_MODE: 1681 adev->gmc.num_mem_partitions = 8; 1682 break; 1683 default: 1684 adev->gmc.num_mem_partitions = 1; 1685 break; 1686 } 1687 1688 /* Use NPS range info, if populated */ 1689 r = amdgpu_gmc_get_nps_memranges(adev, mem_ranges, 1690 &adev->gmc.num_mem_partitions); 1691 if (!r) { 1692 l = 0; 1693 for (i = 1; i < adev->gmc.num_mem_partitions; ++i) { 1694 if (mem_ranges[i].range.lpfn > 1695 mem_ranges[i - 1].range.lpfn) 1696 l = i; 1697 } 1698 1699 } else { 1700 if (!adev->gmc.num_mem_partitions) { 1701 dev_warn(adev->dev, 1702 "Not able to detect NPS mode, fall back to NPS1\n"); 1703 adev->gmc.num_mem_partitions = 1; 1704 } 1705 /* Fallback to sw based calculation */ 1706 size = (adev->gmc.real_vram_size + SZ_16M) >> AMDGPU_GPU_PAGE_SHIFT; 1707 size /= adev->gmc.num_mem_partitions; 1708 1709 for (i = 0; i < adev->gmc.num_mem_partitions; ++i) { 1710 mem_ranges[i].range.fpfn = start_addr; 1711 mem_ranges[i].size = 1712 ((u64)size << AMDGPU_GPU_PAGE_SHIFT); 1713 mem_ranges[i].range.lpfn = start_addr + size - 1; 1714 start_addr += size; 1715 } 1716 1717 l = adev->gmc.num_mem_partitions - 1; 1718 } 1719 1720 /* Adjust the last one */ 1721 mem_ranges[l].range.lpfn = 1722 (adev->gmc.real_vram_size >> AMDGPU_GPU_PAGE_SHIFT) - 1; 1723 mem_ranges[l].size = 1724 adev->gmc.real_vram_size - 1725 ((u64)mem_ranges[l].range.fpfn << AMDGPU_GPU_PAGE_SHIFT); 1726 } 1727 1728 int amdgpu_gmc_init_mem_ranges(struct amdgpu_device *adev) 1729 { 1730 bool valid; 1731 1732 adev->gmc.mem_partitions = kzalloc_objs(struct amdgpu_mem_partition_info, 1733 AMDGPU_MAX_MEM_RANGES); 1734 if (!adev->gmc.mem_partitions) 1735 return -ENOMEM; 1736 1737 if (adev->gmc.is_app_apu) 1738 amdgpu_gmc_init_acpi_mem_ranges(adev, adev->gmc.mem_partitions); 1739 else 1740 amdgpu_gmc_init_sw_mem_ranges(adev, adev->gmc.mem_partitions); 1741 1742 if (amdgpu_sriov_vf(adev)) 1743 valid = true; 1744 else 1745 valid = amdgpu_gmc_validate_partition_info(adev); 1746 if (!valid) { 1747 /* TODO: handle invalid case */ 1748 dev_warn(adev->dev, 1749 "Mem ranges not matching with hardware config\n"); 1750 } 1751 1752 return 0; 1753 } 1754 1755 int amdgpu_gmc_get_vram_info(struct amdgpu_device *adev, 1756 int *vram_width, int *vram_type, int *vram_vendor) 1757 { 1758 int ret = 0; 1759 1760 if (adev->flags & AMD_IS_APU) 1761 return amdgpu_atomfirmware_get_integrated_system_info(adev, 1762 vram_width, vram_type, vram_vendor); 1763 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1764 case IP_VERSION(12, 0, 0): 1765 case IP_VERSION(12, 0, 1): 1766 return amdgpu_atomfirmware_get_umc_info(adev, 1767 vram_width, vram_type, vram_vendor); 1768 case IP_VERSION(9, 5, 0): 1769 case IP_VERSION(9, 4, 4): 1770 case IP_VERSION(9, 4, 3): 1771 ret = amdgpu_atomfirmware_get_umc_info(adev, 1772 vram_width, vram_type, vram_vendor); 1773 if (vram_width && !ret) 1774 *vram_width *= hweight32(adev->aid_mask); 1775 return ret; 1776 default: 1777 return amdgpu_atomfirmware_get_vram_info(adev, 1778 vram_width, vram_type, vram_vendor); 1779 } 1780 return 0; 1781 } 1782