1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 27 #include <linux/io-64-nonatomic-lo-hi.h> 28 #ifdef CONFIG_X86 29 #include <asm/hypervisor.h> 30 #endif 31 32 #include "amdgpu.h" 33 #include "amdgpu_gmc.h" 34 #include "amdgpu_ras.h" 35 #include "amdgpu_reset.h" 36 #include "amdgpu_xgmi.h" 37 38 #include <drm/drm_drv.h> 39 #include <drm/ttm/ttm_tt.h> 40 41 /** 42 * amdgpu_gmc_pdb0_alloc - allocate vram for pdb0 43 * 44 * @adev: amdgpu_device pointer 45 * 46 * Allocate video memory for pdb0 and map it for CPU access 47 * Returns 0 for success, error for failure. 48 */ 49 int amdgpu_gmc_pdb0_alloc(struct amdgpu_device *adev) 50 { 51 int r; 52 struct amdgpu_bo_param bp; 53 u64 vram_size = adev->gmc.xgmi.node_segment_size * adev->gmc.xgmi.num_physical_nodes; 54 uint32_t pde0_page_shift = adev->gmc.vmid0_page_table_block_size + 21; 55 uint32_t npdes = (vram_size + (1ULL << pde0_page_shift) - 1) >> pde0_page_shift; 56 57 memset(&bp, 0, sizeof(bp)); 58 bp.size = PAGE_ALIGN((npdes + 1) * 8); 59 bp.byte_align = PAGE_SIZE; 60 bp.domain = AMDGPU_GEM_DOMAIN_VRAM; 61 bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 62 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 63 bp.type = ttm_bo_type_kernel; 64 bp.resv = NULL; 65 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 66 67 r = amdgpu_bo_create(adev, &bp, &adev->gmc.pdb0_bo); 68 if (r) 69 return r; 70 71 r = amdgpu_bo_reserve(adev->gmc.pdb0_bo, false); 72 if (unlikely(r != 0)) 73 goto bo_reserve_failure; 74 75 r = amdgpu_bo_pin(adev->gmc.pdb0_bo, AMDGPU_GEM_DOMAIN_VRAM); 76 if (r) 77 goto bo_pin_failure; 78 r = amdgpu_bo_kmap(adev->gmc.pdb0_bo, &adev->gmc.ptr_pdb0); 79 if (r) 80 goto bo_kmap_failure; 81 82 amdgpu_bo_unreserve(adev->gmc.pdb0_bo); 83 return 0; 84 85 bo_kmap_failure: 86 amdgpu_bo_unpin(adev->gmc.pdb0_bo); 87 bo_pin_failure: 88 amdgpu_bo_unreserve(adev->gmc.pdb0_bo); 89 bo_reserve_failure: 90 amdgpu_bo_unref(&adev->gmc.pdb0_bo); 91 return r; 92 } 93 94 /** 95 * amdgpu_gmc_get_pde_for_bo - get the PDE for a BO 96 * 97 * @bo: the BO to get the PDE for 98 * @level: the level in the PD hirarchy 99 * @addr: resulting addr 100 * @flags: resulting flags 101 * 102 * Get the address and flags to be used for a PDE (Page Directory Entry). 103 */ 104 void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level, 105 uint64_t *addr, uint64_t *flags) 106 { 107 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 108 109 switch (bo->tbo.resource->mem_type) { 110 case TTM_PL_TT: 111 *addr = bo->tbo.ttm->dma_address[0]; 112 break; 113 case TTM_PL_VRAM: 114 *addr = amdgpu_bo_gpu_offset(bo); 115 break; 116 default: 117 *addr = 0; 118 break; 119 } 120 *flags = amdgpu_ttm_tt_pde_flags(bo->tbo.ttm, bo->tbo.resource); 121 amdgpu_gmc_get_vm_pde(adev, level, addr, flags); 122 } 123 124 /* 125 * amdgpu_gmc_pd_addr - return the address of the root directory 126 */ 127 uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo) 128 { 129 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 130 uint64_t pd_addr; 131 132 /* TODO: move that into ASIC specific code */ 133 if (adev->asic_type >= CHIP_VEGA10) { 134 uint64_t flags = AMDGPU_PTE_VALID; 135 136 amdgpu_gmc_get_pde_for_bo(bo, -1, &pd_addr, &flags); 137 pd_addr |= flags; 138 } else { 139 pd_addr = amdgpu_bo_gpu_offset(bo); 140 } 141 return pd_addr; 142 } 143 144 /** 145 * amdgpu_gmc_set_pte_pde - update the page tables using CPU 146 * 147 * @adev: amdgpu_device pointer 148 * @cpu_pt_addr: cpu address of the page table 149 * @gpu_page_idx: entry in the page table to update 150 * @addr: dst addr to write into pte/pde 151 * @flags: access flags 152 * 153 * Update the page tables using CPU. 154 */ 155 int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr, 156 uint32_t gpu_page_idx, uint64_t addr, 157 uint64_t flags) 158 { 159 void __iomem *ptr = (void *)cpu_pt_addr; 160 uint64_t value; 161 162 /* 163 * The following is for PTE only. GART does not have PDEs. 164 */ 165 value = addr & 0x0000FFFFFFFFF000ULL; 166 value |= flags; 167 writeq(value, ptr + (gpu_page_idx * 8)); 168 169 return 0; 170 } 171 172 /** 173 * amdgpu_gmc_agp_addr - return the address in the AGP address space 174 * 175 * @bo: TTM BO which needs the address, must be in GTT domain 176 * 177 * Tries to figure out how to access the BO through the AGP aperture. Returns 178 * AMDGPU_BO_INVALID_OFFSET if that is not possible. 179 */ 180 uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo) 181 { 182 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 183 184 if (!bo->ttm) 185 return AMDGPU_BO_INVALID_OFFSET; 186 187 if (bo->ttm->num_pages != 1 || bo->ttm->caching == ttm_cached) 188 return AMDGPU_BO_INVALID_OFFSET; 189 190 if (bo->ttm->dma_address[0] + PAGE_SIZE >= adev->gmc.agp_size) 191 return AMDGPU_BO_INVALID_OFFSET; 192 193 return adev->gmc.agp_start + bo->ttm->dma_address[0]; 194 } 195 196 /** 197 * amdgpu_gmc_vram_location - try to find VRAM location 198 * 199 * @adev: amdgpu device structure holding all necessary information 200 * @mc: memory controller structure holding memory information 201 * @base: base address at which to put VRAM 202 * 203 * Function will try to place VRAM at base address provided 204 * as parameter. 205 */ 206 void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc, 207 u64 base) 208 { 209 uint64_t vis_limit = (uint64_t)amdgpu_vis_vram_limit << 20; 210 uint64_t limit = (uint64_t)amdgpu_vram_limit << 20; 211 212 mc->vram_start = base; 213 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 214 if (limit < mc->real_vram_size) 215 mc->real_vram_size = limit; 216 217 if (vis_limit && vis_limit < mc->visible_vram_size) 218 mc->visible_vram_size = vis_limit; 219 220 if (mc->real_vram_size < mc->visible_vram_size) 221 mc->visible_vram_size = mc->real_vram_size; 222 223 if (mc->xgmi.num_physical_nodes == 0) { 224 mc->fb_start = mc->vram_start; 225 mc->fb_end = mc->vram_end; 226 } 227 dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", 228 mc->mc_vram_size >> 20, mc->vram_start, 229 mc->vram_end, mc->real_vram_size >> 20); 230 } 231 232 /** amdgpu_gmc_sysvm_location - place vram and gart in sysvm aperture 233 * 234 * @adev: amdgpu device structure holding all necessary information 235 * @mc: memory controller structure holding memory information 236 * 237 * This function is only used if use GART for FB translation. In such 238 * case, we use sysvm aperture (vmid0 page tables) for both vram 239 * and gart (aka system memory) access. 240 * 241 * GPUVM (and our organization of vmid0 page tables) require sysvm 242 * aperture to be placed at a location aligned with 8 times of native 243 * page size. For example, if vm_context0_cntl.page_table_block_size 244 * is 12, then native page size is 8G (2M*2^12), sysvm should start 245 * with a 64G aligned address. For simplicity, we just put sysvm at 246 * address 0. So vram start at address 0 and gart is right after vram. 247 */ 248 void amdgpu_gmc_sysvm_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc) 249 { 250 u64 hive_vram_start = 0; 251 u64 hive_vram_end = mc->xgmi.node_segment_size * mc->xgmi.num_physical_nodes - 1; 252 mc->vram_start = mc->xgmi.node_segment_size * mc->xgmi.physical_node_id; 253 mc->vram_end = mc->vram_start + mc->xgmi.node_segment_size - 1; 254 mc->gart_start = hive_vram_end + 1; 255 mc->gart_end = mc->gart_start + mc->gart_size - 1; 256 mc->fb_start = hive_vram_start; 257 mc->fb_end = hive_vram_end; 258 dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", 259 mc->mc_vram_size >> 20, mc->vram_start, 260 mc->vram_end, mc->real_vram_size >> 20); 261 dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n", 262 mc->gart_size >> 20, mc->gart_start, mc->gart_end); 263 } 264 265 /** 266 * amdgpu_gmc_gart_location - try to find GART location 267 * 268 * @adev: amdgpu device structure holding all necessary information 269 * @mc: memory controller structure holding memory information 270 * @gart_placement: GART placement policy with respect to VRAM 271 * 272 * Function will place try to place GART before or after VRAM. 273 * If GART size is bigger than space left then we ajust GART size. 274 * Thus function will never fails. 275 */ 276 void amdgpu_gmc_gart_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc, 277 enum amdgpu_gart_placement gart_placement) 278 { 279 const uint64_t four_gb = 0x100000000ULL; 280 u64 size_af, size_bf; 281 /*To avoid the hole, limit the max mc address to AMDGPU_GMC_HOLE_START*/ 282 u64 max_mc_address = min(adev->gmc.mc_mask, AMDGPU_GMC_HOLE_START - 1); 283 284 /* VCE doesn't like it when BOs cross a 4GB segment, so align 285 * the GART base on a 4GB boundary as well. 286 */ 287 size_bf = mc->fb_start; 288 size_af = max_mc_address + 1 - ALIGN(mc->fb_end + 1, four_gb); 289 290 if (mc->gart_size > max(size_bf, size_af)) { 291 dev_warn(adev->dev, "limiting GART\n"); 292 mc->gart_size = max(size_bf, size_af); 293 } 294 295 switch (gart_placement) { 296 case AMDGPU_GART_PLACEMENT_HIGH: 297 mc->gart_start = max_mc_address - mc->gart_size + 1; 298 break; 299 case AMDGPU_GART_PLACEMENT_LOW: 300 mc->gart_start = 0; 301 break; 302 case AMDGPU_GART_PLACEMENT_BEST_FIT: 303 default: 304 if ((size_bf >= mc->gart_size && size_bf < size_af) || 305 (size_af < mc->gart_size)) 306 mc->gart_start = 0; 307 else 308 mc->gart_start = max_mc_address - mc->gart_size + 1; 309 break; 310 } 311 312 mc->gart_start &= ~(four_gb - 1); 313 mc->gart_end = mc->gart_start + mc->gart_size - 1; 314 dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n", 315 mc->gart_size >> 20, mc->gart_start, mc->gart_end); 316 } 317 318 /** 319 * amdgpu_gmc_agp_location - try to find AGP location 320 * @adev: amdgpu device structure holding all necessary information 321 * @mc: memory controller structure holding memory information 322 * 323 * Function will place try to find a place for the AGP BAR in the MC address 324 * space. 325 * 326 * AGP BAR will be assigned the largest available hole in the address space. 327 * Should be called after VRAM and GART locations are setup. 328 */ 329 void amdgpu_gmc_agp_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc) 330 { 331 const uint64_t sixteen_gb = 1ULL << 34; 332 const uint64_t sixteen_gb_mask = ~(sixteen_gb - 1); 333 u64 size_af, size_bf; 334 335 if (mc->fb_start > mc->gart_start) { 336 size_bf = (mc->fb_start & sixteen_gb_mask) - 337 ALIGN(mc->gart_end + 1, sixteen_gb); 338 size_af = mc->mc_mask + 1 - ALIGN(mc->fb_end + 1, sixteen_gb); 339 } else { 340 size_bf = mc->fb_start & sixteen_gb_mask; 341 size_af = (mc->gart_start & sixteen_gb_mask) - 342 ALIGN(mc->fb_end + 1, sixteen_gb); 343 } 344 345 if (size_bf > size_af) { 346 mc->agp_start = (mc->fb_start - size_bf) & sixteen_gb_mask; 347 mc->agp_size = size_bf; 348 } else { 349 mc->agp_start = ALIGN(mc->fb_end + 1, sixteen_gb); 350 mc->agp_size = size_af; 351 } 352 353 mc->agp_end = mc->agp_start + mc->agp_size - 1; 354 dev_info(adev->dev, "AGP: %lluM 0x%016llX - 0x%016llX\n", 355 mc->agp_size >> 20, mc->agp_start, mc->agp_end); 356 } 357 358 /** 359 * amdgpu_gmc_set_agp_default - Set the default AGP aperture value. 360 * @adev: amdgpu device structure holding all necessary information 361 * @mc: memory controller structure holding memory information 362 * 363 * To disable the AGP aperture, you need to set the start to a larger 364 * value than the end. This function sets the default value which 365 * can then be overridden using amdgpu_gmc_agp_location() if you want 366 * to enable the AGP aperture on a specific chip. 367 * 368 */ 369 void amdgpu_gmc_set_agp_default(struct amdgpu_device *adev, 370 struct amdgpu_gmc *mc) 371 { 372 mc->agp_start = 0xffffffffffff; 373 mc->agp_end = 0; 374 mc->agp_size = 0; 375 } 376 377 /** 378 * amdgpu_gmc_fault_key - get hask key from vm fault address and pasid 379 * 380 * @addr: 48 bit physical address, page aligned (36 significant bits) 381 * @pasid: 16 bit process address space identifier 382 */ 383 static inline uint64_t amdgpu_gmc_fault_key(uint64_t addr, uint16_t pasid) 384 { 385 return addr << 4 | pasid; 386 } 387 388 /** 389 * amdgpu_gmc_filter_faults - filter VM faults 390 * 391 * @adev: amdgpu device structure 392 * @ih: interrupt ring that the fault received from 393 * @addr: address of the VM fault 394 * @pasid: PASID of the process causing the fault 395 * @timestamp: timestamp of the fault 396 * 397 * Returns: 398 * True if the fault was filtered and should not be processed further. 399 * False if the fault is a new one and needs to be handled. 400 */ 401 bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, 402 struct amdgpu_ih_ring *ih, uint64_t addr, 403 uint16_t pasid, uint64_t timestamp) 404 { 405 struct amdgpu_gmc *gmc = &adev->gmc; 406 uint64_t stamp, key = amdgpu_gmc_fault_key(addr, pasid); 407 struct amdgpu_gmc_fault *fault; 408 uint32_t hash; 409 410 /* Stale retry fault if timestamp goes backward */ 411 if (amdgpu_ih_ts_after(timestamp, ih->processed_timestamp)) 412 return true; 413 414 /* If we don't have space left in the ring buffer return immediately */ 415 stamp = max(timestamp, AMDGPU_GMC_FAULT_TIMEOUT + 1) - 416 AMDGPU_GMC_FAULT_TIMEOUT; 417 if (gmc->fault_ring[gmc->last_fault].timestamp >= stamp) 418 return true; 419 420 /* Try to find the fault in the hash */ 421 hash = hash_64(key, AMDGPU_GMC_FAULT_HASH_ORDER); 422 fault = &gmc->fault_ring[gmc->fault_hash[hash].idx]; 423 while (fault->timestamp >= stamp) { 424 uint64_t tmp; 425 426 if (atomic64_read(&fault->key) == key) { 427 /* 428 * if we get a fault which is already present in 429 * the fault_ring and the timestamp of 430 * the fault is after the expired timestamp, 431 * then this is a new fault that needs to be added 432 * into the fault ring. 433 */ 434 if (fault->timestamp_expiry != 0 && 435 amdgpu_ih_ts_after(fault->timestamp_expiry, 436 timestamp)) 437 break; 438 else 439 return true; 440 } 441 442 tmp = fault->timestamp; 443 fault = &gmc->fault_ring[fault->next]; 444 445 /* Check if the entry was reused */ 446 if (fault->timestamp >= tmp) 447 break; 448 } 449 450 /* Add the fault to the ring */ 451 fault = &gmc->fault_ring[gmc->last_fault]; 452 atomic64_set(&fault->key, key); 453 fault->timestamp = timestamp; 454 455 /* And update the hash */ 456 fault->next = gmc->fault_hash[hash].idx; 457 gmc->fault_hash[hash].idx = gmc->last_fault++; 458 return false; 459 } 460 461 /** 462 * amdgpu_gmc_filter_faults_remove - remove address from VM faults filter 463 * 464 * @adev: amdgpu device structure 465 * @addr: address of the VM fault 466 * @pasid: PASID of the process causing the fault 467 * 468 * Remove the address from fault filter, then future vm fault on this address 469 * will pass to retry fault handler to recover. 470 */ 471 void amdgpu_gmc_filter_faults_remove(struct amdgpu_device *adev, uint64_t addr, 472 uint16_t pasid) 473 { 474 struct amdgpu_gmc *gmc = &adev->gmc; 475 uint64_t key = amdgpu_gmc_fault_key(addr, pasid); 476 struct amdgpu_ih_ring *ih; 477 struct amdgpu_gmc_fault *fault; 478 uint32_t last_wptr; 479 uint64_t last_ts; 480 uint32_t hash; 481 uint64_t tmp; 482 483 if (adev->irq.retry_cam_enabled) 484 return; 485 486 ih = &adev->irq.ih1; 487 /* Get the WPTR of the last entry in IH ring */ 488 last_wptr = amdgpu_ih_get_wptr(adev, ih); 489 /* Order wptr with ring data. */ 490 rmb(); 491 /* Get the timetamp of the last entry in IH ring */ 492 last_ts = amdgpu_ih_decode_iv_ts(adev, ih, last_wptr, -1); 493 494 hash = hash_64(key, AMDGPU_GMC_FAULT_HASH_ORDER); 495 fault = &gmc->fault_ring[gmc->fault_hash[hash].idx]; 496 do { 497 if (atomic64_read(&fault->key) == key) { 498 /* 499 * Update the timestamp when this fault 500 * expired. 501 */ 502 fault->timestamp_expiry = last_ts; 503 break; 504 } 505 506 tmp = fault->timestamp; 507 fault = &gmc->fault_ring[fault->next]; 508 } while (fault->timestamp < tmp); 509 } 510 511 int amdgpu_gmc_ras_sw_init(struct amdgpu_device *adev) 512 { 513 int r; 514 515 /* umc ras block */ 516 r = amdgpu_umc_ras_sw_init(adev); 517 if (r) 518 return r; 519 520 /* mmhub ras block */ 521 r = amdgpu_mmhub_ras_sw_init(adev); 522 if (r) 523 return r; 524 525 /* hdp ras block */ 526 r = amdgpu_hdp_ras_sw_init(adev); 527 if (r) 528 return r; 529 530 /* mca.x ras block */ 531 r = amdgpu_mca_mp0_ras_sw_init(adev); 532 if (r) 533 return r; 534 535 r = amdgpu_mca_mp1_ras_sw_init(adev); 536 if (r) 537 return r; 538 539 r = amdgpu_mca_mpio_ras_sw_init(adev); 540 if (r) 541 return r; 542 543 /* xgmi ras block */ 544 r = amdgpu_xgmi_ras_sw_init(adev); 545 if (r) 546 return r; 547 548 return 0; 549 } 550 551 int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev) 552 { 553 return 0; 554 } 555 556 void amdgpu_gmc_ras_fini(struct amdgpu_device *adev) 557 { 558 559 } 560 561 /* 562 * The latest engine allocation on gfx9/10 is: 563 * Engine 2, 3: firmware 564 * Engine 0, 1, 4~16: amdgpu ring, 565 * subject to change when ring number changes 566 * Engine 17: Gart flushes 567 */ 568 #define AMDGPU_VMHUB_INV_ENG_BITMAP 0x1FFF3 569 570 int amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_device *adev) 571 { 572 struct amdgpu_ring *ring; 573 unsigned vm_inv_engs[AMDGPU_MAX_VMHUBS] = {0}; 574 unsigned i; 575 unsigned vmhub, inv_eng; 576 577 /* init the vm inv eng for all vmhubs */ 578 for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 579 vm_inv_engs[i] = AMDGPU_VMHUB_INV_ENG_BITMAP; 580 /* reserve engine 5 for firmware */ 581 if (adev->enable_mes) 582 vm_inv_engs[i] &= ~(1 << 5); 583 /* reserve mmhub engine 3 for firmware */ 584 if (adev->enable_umsch_mm) 585 vm_inv_engs[i] &= ~(1 << 3); 586 } 587 588 for (i = 0; i < adev->num_rings; ++i) { 589 ring = adev->rings[i]; 590 vmhub = ring->vm_hub; 591 592 if (ring == &adev->mes.ring || 593 ring == &adev->umsch_mm.ring) 594 continue; 595 596 inv_eng = ffs(vm_inv_engs[vmhub]); 597 if (!inv_eng) { 598 dev_err(adev->dev, "no VM inv eng for ring %s\n", 599 ring->name); 600 return -EINVAL; 601 } 602 603 ring->vm_inv_eng = inv_eng - 1; 604 vm_inv_engs[vmhub] &= ~(1 << ring->vm_inv_eng); 605 606 dev_info(adev->dev, "ring %s uses VM inv eng %u on hub %u\n", 607 ring->name, ring->vm_inv_eng, ring->vm_hub); 608 } 609 610 return 0; 611 } 612 613 void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 614 uint32_t vmhub, uint32_t flush_type) 615 { 616 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 617 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 618 struct dma_fence *fence; 619 struct amdgpu_job *job; 620 int r; 621 622 if (!hub->sdma_invalidation_workaround || vmid || 623 !adev->mman.buffer_funcs_enabled || !adev->ib_pool_ready || 624 !ring->sched.ready) { 625 /* 626 * A GPU reset should flush all TLBs anyway, so no need to do 627 * this while one is ongoing. 628 */ 629 if (!down_read_trylock(&adev->reset_domain->sem)) 630 return; 631 632 if (adev->gmc.flush_tlb_needs_extra_type_2) 633 adev->gmc.gmc_funcs->flush_gpu_tlb(adev, vmid, 634 vmhub, 2); 635 636 if (adev->gmc.flush_tlb_needs_extra_type_0 && flush_type == 2) 637 adev->gmc.gmc_funcs->flush_gpu_tlb(adev, vmid, 638 vmhub, 0); 639 640 adev->gmc.gmc_funcs->flush_gpu_tlb(adev, vmid, vmhub, 641 flush_type); 642 up_read(&adev->reset_domain->sem); 643 return; 644 } 645 646 /* The SDMA on Navi 1x has a bug which can theoretically result in memory 647 * corruption if an invalidation happens at the same time as an VA 648 * translation. Avoid this by doing the invalidation from the SDMA 649 * itself at least for GART. 650 */ 651 mutex_lock(&adev->mman.gtt_window_lock); 652 r = amdgpu_job_alloc_with_ib(ring->adev, &adev->mman.high_pr, 653 AMDGPU_FENCE_OWNER_UNDEFINED, 654 16 * 4, AMDGPU_IB_POOL_IMMEDIATE, 655 &job); 656 if (r) 657 goto error_alloc; 658 659 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo); 660 job->vm_needs_flush = true; 661 job->ibs->ptr[job->ibs->length_dw++] = ring->funcs->nop; 662 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 663 fence = amdgpu_job_submit(job); 664 mutex_unlock(&adev->mman.gtt_window_lock); 665 666 dma_fence_wait(fence, false); 667 dma_fence_put(fence); 668 669 return; 670 671 error_alloc: 672 mutex_unlock(&adev->mman.gtt_window_lock); 673 dev_err(adev->dev, "Error flushing GPU TLB using the SDMA (%d)!\n", r); 674 } 675 676 int amdgpu_gmc_flush_gpu_tlb_pasid(struct amdgpu_device *adev, uint16_t pasid, 677 uint32_t flush_type, bool all_hub, 678 uint32_t inst) 679 { 680 u32 usec_timeout = amdgpu_sriov_vf(adev) ? SRIOV_USEC_TIMEOUT : 681 adev->usec_timeout; 682 struct amdgpu_ring *ring = &adev->gfx.kiq[inst].ring; 683 struct amdgpu_kiq *kiq = &adev->gfx.kiq[inst]; 684 unsigned int ndw; 685 int r; 686 uint32_t seq; 687 688 /* 689 * A GPU reset should flush all TLBs anyway, so no need to do 690 * this while one is ongoing. 691 */ 692 if (!down_read_trylock(&adev->reset_domain->sem)) 693 return 0; 694 695 if (!adev->gmc.flush_pasid_uses_kiq || !ring->sched.ready) { 696 if (adev->gmc.flush_tlb_needs_extra_type_2) 697 adev->gmc.gmc_funcs->flush_gpu_tlb_pasid(adev, pasid, 698 2, all_hub, 699 inst); 700 701 if (adev->gmc.flush_tlb_needs_extra_type_0 && flush_type == 2) 702 adev->gmc.gmc_funcs->flush_gpu_tlb_pasid(adev, pasid, 703 0, all_hub, 704 inst); 705 706 adev->gmc.gmc_funcs->flush_gpu_tlb_pasid(adev, pasid, 707 flush_type, all_hub, 708 inst); 709 r = 0; 710 } else { 711 /* 2 dwords flush + 8 dwords fence */ 712 ndw = kiq->pmf->invalidate_tlbs_size + 8; 713 714 if (adev->gmc.flush_tlb_needs_extra_type_2) 715 ndw += kiq->pmf->invalidate_tlbs_size; 716 717 if (adev->gmc.flush_tlb_needs_extra_type_0) 718 ndw += kiq->pmf->invalidate_tlbs_size; 719 720 spin_lock(&adev->gfx.kiq[inst].ring_lock); 721 r = amdgpu_ring_alloc(ring, ndw); 722 if (r) { 723 spin_unlock(&adev->gfx.kiq[inst].ring_lock); 724 goto error_unlock_reset; 725 } 726 if (adev->gmc.flush_tlb_needs_extra_type_2) 727 kiq->pmf->kiq_invalidate_tlbs(ring, pasid, 2, all_hub); 728 729 if (flush_type == 2 && adev->gmc.flush_tlb_needs_extra_type_0) 730 kiq->pmf->kiq_invalidate_tlbs(ring, pasid, 0, all_hub); 731 732 kiq->pmf->kiq_invalidate_tlbs(ring, pasid, flush_type, all_hub); 733 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT); 734 if (r) { 735 amdgpu_ring_undo(ring); 736 spin_unlock(&adev->gfx.kiq[inst].ring_lock); 737 goto error_unlock_reset; 738 } 739 740 amdgpu_ring_commit(ring); 741 spin_unlock(&adev->gfx.kiq[inst].ring_lock); 742 if (amdgpu_fence_wait_polling(ring, seq, usec_timeout) < 1) { 743 dev_err(adev->dev, "timeout waiting for kiq fence\n"); 744 r = -ETIME; 745 } 746 } 747 748 error_unlock_reset: 749 up_read(&adev->reset_domain->sem); 750 return r; 751 } 752 753 void amdgpu_gmc_fw_reg_write_reg_wait(struct amdgpu_device *adev, 754 uint32_t reg0, uint32_t reg1, 755 uint32_t ref, uint32_t mask, 756 uint32_t xcc_inst) 757 { 758 struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_inst]; 759 struct amdgpu_ring *ring = &kiq->ring; 760 signed long r, cnt = 0; 761 unsigned long flags; 762 uint32_t seq; 763 764 if (adev->mes.ring.sched.ready) { 765 amdgpu_mes_reg_write_reg_wait(adev, reg0, reg1, 766 ref, mask); 767 return; 768 } 769 770 spin_lock_irqsave(&kiq->ring_lock, flags); 771 amdgpu_ring_alloc(ring, 32); 772 amdgpu_ring_emit_reg_write_reg_wait(ring, reg0, reg1, 773 ref, mask); 774 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT); 775 if (r) 776 goto failed_undo; 777 778 amdgpu_ring_commit(ring); 779 spin_unlock_irqrestore(&kiq->ring_lock, flags); 780 781 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); 782 783 /* don't wait anymore for IRQ context */ 784 if (r < 1 && in_interrupt()) 785 goto failed_kiq; 786 787 might_sleep(); 788 while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) { 789 790 msleep(MAX_KIQ_REG_BAILOUT_INTERVAL); 791 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); 792 } 793 794 if (cnt > MAX_KIQ_REG_TRY) 795 goto failed_kiq; 796 797 return; 798 799 failed_undo: 800 amdgpu_ring_undo(ring); 801 spin_unlock_irqrestore(&kiq->ring_lock, flags); 802 failed_kiq: 803 dev_err(adev->dev, "failed to write reg %x wait reg %x\n", reg0, reg1); 804 } 805 806 /** 807 * amdgpu_gmc_tmz_set -- check and set if a device supports TMZ 808 * @adev: amdgpu_device pointer 809 * 810 * Check and set if an the device @adev supports Trusted Memory 811 * Zones (TMZ). 812 */ 813 void amdgpu_gmc_tmz_set(struct amdgpu_device *adev) 814 { 815 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 816 /* RAVEN */ 817 case IP_VERSION(9, 2, 2): 818 case IP_VERSION(9, 1, 0): 819 /* RENOIR looks like RAVEN */ 820 case IP_VERSION(9, 3, 0): 821 /* GC 10.3.7 */ 822 case IP_VERSION(10, 3, 7): 823 /* GC 11.0.1 */ 824 case IP_VERSION(11, 0, 1): 825 if (amdgpu_tmz == 0) { 826 adev->gmc.tmz_enabled = false; 827 dev_info(adev->dev, 828 "Trusted Memory Zone (TMZ) feature disabled (cmd line)\n"); 829 } else { 830 adev->gmc.tmz_enabled = true; 831 dev_info(adev->dev, 832 "Trusted Memory Zone (TMZ) feature enabled\n"); 833 } 834 break; 835 case IP_VERSION(10, 1, 10): 836 case IP_VERSION(10, 1, 1): 837 case IP_VERSION(10, 1, 2): 838 case IP_VERSION(10, 1, 3): 839 case IP_VERSION(10, 3, 0): 840 case IP_VERSION(10, 3, 2): 841 case IP_VERSION(10, 3, 4): 842 case IP_VERSION(10, 3, 5): 843 case IP_VERSION(10, 3, 6): 844 /* VANGOGH */ 845 case IP_VERSION(10, 3, 1): 846 /* YELLOW_CARP*/ 847 case IP_VERSION(10, 3, 3): 848 case IP_VERSION(11, 0, 4): 849 case IP_VERSION(11, 5, 0): 850 case IP_VERSION(11, 5, 1): 851 /* Don't enable it by default yet. 852 */ 853 if (amdgpu_tmz < 1) { 854 adev->gmc.tmz_enabled = false; 855 dev_info(adev->dev, 856 "Trusted Memory Zone (TMZ) feature disabled as experimental (default)\n"); 857 } else { 858 adev->gmc.tmz_enabled = true; 859 dev_info(adev->dev, 860 "Trusted Memory Zone (TMZ) feature enabled as experimental (cmd line)\n"); 861 } 862 break; 863 default: 864 adev->gmc.tmz_enabled = false; 865 dev_info(adev->dev, 866 "Trusted Memory Zone (TMZ) feature not supported\n"); 867 break; 868 } 869 } 870 871 /** 872 * amdgpu_gmc_noretry_set -- set per asic noretry defaults 873 * @adev: amdgpu_device pointer 874 * 875 * Set a per asic default for the no-retry parameter. 876 * 877 */ 878 void amdgpu_gmc_noretry_set(struct amdgpu_device *adev) 879 { 880 struct amdgpu_gmc *gmc = &adev->gmc; 881 uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0); 882 bool noretry_default = (gc_ver == IP_VERSION(9, 0, 1) || 883 gc_ver == IP_VERSION(9, 4, 0) || 884 gc_ver == IP_VERSION(9, 4, 1) || 885 gc_ver == IP_VERSION(9, 4, 2) || 886 gc_ver == IP_VERSION(9, 4, 3) || 887 gc_ver == IP_VERSION(9, 4, 4) || 888 gc_ver >= IP_VERSION(10, 3, 0)); 889 890 if (!amdgpu_sriov_xnack_support(adev)) 891 gmc->noretry = 1; 892 else 893 gmc->noretry = (amdgpu_noretry == -1) ? noretry_default : amdgpu_noretry; 894 } 895 896 void amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device *adev, int hub_type, 897 bool enable) 898 { 899 struct amdgpu_vmhub *hub; 900 u32 tmp, reg, i; 901 902 hub = &adev->vmhub[hub_type]; 903 for (i = 0; i < 16; i++) { 904 reg = hub->vm_context0_cntl + hub->ctx_distance * i; 905 906 tmp = (hub_type == AMDGPU_GFXHUB(0)) ? 907 RREG32_SOC15_IP(GC, reg) : 908 RREG32_SOC15_IP(MMHUB, reg); 909 910 if (enable) 911 tmp |= hub->vm_cntx_cntl_vm_fault; 912 else 913 tmp &= ~hub->vm_cntx_cntl_vm_fault; 914 915 (hub_type == AMDGPU_GFXHUB(0)) ? 916 WREG32_SOC15_IP(GC, reg, tmp) : 917 WREG32_SOC15_IP(MMHUB, reg, tmp); 918 } 919 } 920 921 void amdgpu_gmc_get_vbios_allocations(struct amdgpu_device *adev) 922 { 923 unsigned size; 924 925 /* 926 * Some ASICs need to reserve a region of video memory to avoid access 927 * from driver 928 */ 929 adev->mman.stolen_reserved_offset = 0; 930 adev->mman.stolen_reserved_size = 0; 931 932 /* 933 * TODO: 934 * Currently there is a bug where some memory client outside 935 * of the driver writes to first 8M of VRAM on S3 resume, 936 * this overrides GART which by default gets placed in first 8M and 937 * causes VM_FAULTS once GTT is accessed. 938 * Keep the stolen memory reservation until the while this is not solved. 939 */ 940 switch (adev->asic_type) { 941 case CHIP_VEGA10: 942 adev->mman.keep_stolen_vga_memory = true; 943 /* 944 * VEGA10 SRIOV VF with MS_HYPERV host needs some firmware reserved area. 945 */ 946 #ifdef CONFIG_X86 947 if (amdgpu_sriov_vf(adev) && hypervisor_is_type(X86_HYPER_MS_HYPERV)) { 948 adev->mman.stolen_reserved_offset = 0x500000; 949 adev->mman.stolen_reserved_size = 0x200000; 950 } 951 #endif 952 break; 953 case CHIP_RAVEN: 954 case CHIP_RENOIR: 955 adev->mman.keep_stolen_vga_memory = true; 956 break; 957 default: 958 adev->mman.keep_stolen_vga_memory = false; 959 break; 960 } 961 962 if (amdgpu_sriov_vf(adev) || 963 !amdgpu_device_has_display_hardware(adev)) { 964 size = 0; 965 } else { 966 size = amdgpu_gmc_get_vbios_fb_size(adev); 967 968 if (adev->mman.keep_stolen_vga_memory) 969 size = max(size, (unsigned)AMDGPU_VBIOS_VGA_ALLOCATION); 970 } 971 972 /* set to 0 if the pre-OS buffer uses up most of vram */ 973 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024)) 974 size = 0; 975 976 if (size > AMDGPU_VBIOS_VGA_ALLOCATION) { 977 adev->mman.stolen_vga_size = AMDGPU_VBIOS_VGA_ALLOCATION; 978 adev->mman.stolen_extended_size = size - adev->mman.stolen_vga_size; 979 } else { 980 adev->mman.stolen_vga_size = size; 981 adev->mman.stolen_extended_size = 0; 982 } 983 } 984 985 /** 986 * amdgpu_gmc_init_pdb0 - initialize PDB0 987 * 988 * @adev: amdgpu_device pointer 989 * 990 * This function is only used when GART page table is used 991 * for FB address translatioin. In such a case, we construct 992 * a 2-level system VM page table: PDB0->PTB, to cover both 993 * VRAM of the hive and system memory. 994 * 995 * PDB0 is static, initialized once on driver initialization. 996 * The first n entries of PDB0 are used as PTE by setting 997 * P bit to 1, pointing to VRAM. The n+1'th entry points 998 * to a big PTB covering system memory. 999 * 1000 */ 1001 void amdgpu_gmc_init_pdb0(struct amdgpu_device *adev) 1002 { 1003 int i; 1004 uint64_t flags = adev->gart.gart_pte_flags; //TODO it is UC. explore NC/RW? 1005 /* Each PDE0 (used as PTE) covers (2^vmid0_page_table_block_size)*2M 1006 */ 1007 u64 vram_size = adev->gmc.xgmi.node_segment_size * adev->gmc.xgmi.num_physical_nodes; 1008 u64 pde0_page_size = (1ULL<<adev->gmc.vmid0_page_table_block_size)<<21; 1009 u64 vram_addr = adev->vm_manager.vram_base_offset - 1010 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 1011 u64 vram_end = vram_addr + vram_size; 1012 u64 gart_ptb_gpu_pa = amdgpu_gmc_vram_pa(adev, adev->gart.bo); 1013 int idx; 1014 1015 if (!drm_dev_enter(adev_to_drm(adev), &idx)) 1016 return; 1017 1018 flags |= AMDGPU_PTE_VALID | AMDGPU_PTE_READABLE; 1019 flags |= AMDGPU_PTE_WRITEABLE; 1020 flags |= AMDGPU_PTE_SNOOPED; 1021 flags |= AMDGPU_PTE_FRAG((adev->gmc.vmid0_page_table_block_size + 9*1)); 1022 flags |= AMDGPU_PDE_PTE_FLAG(adev); 1023 1024 /* The first n PDE0 entries are used as PTE, 1025 * pointing to vram 1026 */ 1027 for (i = 0; vram_addr < vram_end; i++, vram_addr += pde0_page_size) 1028 amdgpu_gmc_set_pte_pde(adev, adev->gmc.ptr_pdb0, i, vram_addr, flags); 1029 1030 /* The n+1'th PDE0 entry points to a huge 1031 * PTB who has more than 512 entries each 1032 * pointing to a 4K system page 1033 */ 1034 flags = AMDGPU_PTE_VALID; 1035 flags |= AMDGPU_PTE_SNOOPED | AMDGPU_PDE_BFS_FLAG(adev, 0); 1036 /* Requires gart_ptb_gpu_pa to be 4K aligned */ 1037 amdgpu_gmc_set_pte_pde(adev, adev->gmc.ptr_pdb0, i, gart_ptb_gpu_pa, flags); 1038 drm_dev_exit(idx); 1039 } 1040 1041 /** 1042 * amdgpu_gmc_vram_mc2pa - calculate vram buffer's physical address from MC 1043 * address 1044 * 1045 * @adev: amdgpu_device pointer 1046 * @mc_addr: MC address of buffer 1047 */ 1048 uint64_t amdgpu_gmc_vram_mc2pa(struct amdgpu_device *adev, uint64_t mc_addr) 1049 { 1050 return mc_addr - adev->gmc.vram_start + adev->vm_manager.vram_base_offset; 1051 } 1052 1053 /** 1054 * amdgpu_gmc_vram_pa - calculate vram buffer object's physical address from 1055 * GPU's view 1056 * 1057 * @adev: amdgpu_device pointer 1058 * @bo: amdgpu buffer object 1059 */ 1060 uint64_t amdgpu_gmc_vram_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo) 1061 { 1062 return amdgpu_gmc_vram_mc2pa(adev, amdgpu_bo_gpu_offset(bo)); 1063 } 1064 1065 /** 1066 * amdgpu_gmc_vram_cpu_pa - calculate vram buffer object's physical address 1067 * from CPU's view 1068 * 1069 * @adev: amdgpu_device pointer 1070 * @bo: amdgpu buffer object 1071 */ 1072 uint64_t amdgpu_gmc_vram_cpu_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo) 1073 { 1074 return amdgpu_bo_gpu_offset(bo) - adev->gmc.vram_start + adev->gmc.aper_base; 1075 } 1076 1077 int amdgpu_gmc_vram_checking(struct amdgpu_device *adev) 1078 { 1079 struct amdgpu_bo *vram_bo = NULL; 1080 uint64_t vram_gpu = 0; 1081 void *vram_ptr = NULL; 1082 1083 int ret, size = 0x100000; 1084 uint8_t cptr[10]; 1085 1086 ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE, 1087 AMDGPU_GEM_DOMAIN_VRAM, 1088 &vram_bo, 1089 &vram_gpu, 1090 &vram_ptr); 1091 if (ret) 1092 return ret; 1093 1094 memset(vram_ptr, 0x86, size); 1095 memset(cptr, 0x86, 10); 1096 1097 /** 1098 * Check the start, the mid, and the end of the memory if the content of 1099 * each byte is the pattern "0x86". If yes, we suppose the vram bo is 1100 * workable. 1101 * 1102 * Note: If check the each byte of whole 1M bo, it will cost too many 1103 * seconds, so here, we just pick up three parts for emulation. 1104 */ 1105 ret = memcmp(vram_ptr, cptr, 10); 1106 if (ret) { 1107 ret = -EIO; 1108 goto release_buffer; 1109 } 1110 1111 ret = memcmp(vram_ptr + (size / 2), cptr, 10); 1112 if (ret) { 1113 ret = -EIO; 1114 goto release_buffer; 1115 } 1116 1117 ret = memcmp(vram_ptr + size - 10, cptr, 10); 1118 if (ret) { 1119 ret = -EIO; 1120 goto release_buffer; 1121 } 1122 1123 release_buffer: 1124 amdgpu_bo_free_kernel(&vram_bo, &vram_gpu, 1125 &vram_ptr); 1126 1127 return ret; 1128 } 1129 1130 static ssize_t current_memory_partition_show( 1131 struct device *dev, struct device_attribute *addr, char *buf) 1132 { 1133 struct drm_device *ddev = dev_get_drvdata(dev); 1134 struct amdgpu_device *adev = drm_to_adev(ddev); 1135 enum amdgpu_memory_partition mode; 1136 1137 mode = adev->gmc.gmc_funcs->query_mem_partition_mode(adev); 1138 switch (mode) { 1139 case AMDGPU_NPS1_PARTITION_MODE: 1140 return sysfs_emit(buf, "NPS1\n"); 1141 case AMDGPU_NPS2_PARTITION_MODE: 1142 return sysfs_emit(buf, "NPS2\n"); 1143 case AMDGPU_NPS3_PARTITION_MODE: 1144 return sysfs_emit(buf, "NPS3\n"); 1145 case AMDGPU_NPS4_PARTITION_MODE: 1146 return sysfs_emit(buf, "NPS4\n"); 1147 case AMDGPU_NPS6_PARTITION_MODE: 1148 return sysfs_emit(buf, "NPS6\n"); 1149 case AMDGPU_NPS8_PARTITION_MODE: 1150 return sysfs_emit(buf, "NPS8\n"); 1151 default: 1152 return sysfs_emit(buf, "UNKNOWN\n"); 1153 } 1154 } 1155 1156 static DEVICE_ATTR_RO(current_memory_partition); 1157 1158 int amdgpu_gmc_sysfs_init(struct amdgpu_device *adev) 1159 { 1160 if (!adev->gmc.gmc_funcs->query_mem_partition_mode) 1161 return 0; 1162 1163 return device_create_file(adev->dev, 1164 &dev_attr_current_memory_partition); 1165 } 1166 1167 void amdgpu_gmc_sysfs_fini(struct amdgpu_device *adev) 1168 { 1169 device_remove_file(adev->dev, &dev_attr_current_memory_partition); 1170 } 1171 1172 int amdgpu_gmc_get_nps_memranges(struct amdgpu_device *adev, 1173 struct amdgpu_mem_partition_info *mem_ranges, 1174 int exp_ranges) 1175 { 1176 struct amdgpu_gmc_memrange *ranges; 1177 int range_cnt, ret, i, j; 1178 uint32_t nps_type; 1179 1180 if (!mem_ranges) 1181 return -EINVAL; 1182 1183 ret = amdgpu_discovery_get_nps_info(adev, &nps_type, &ranges, 1184 &range_cnt); 1185 1186 if (ret) 1187 return ret; 1188 1189 /* TODO: For now, expect ranges and partition count to be the same. 1190 * Adjust if there are holes expected in any NPS domain. 1191 */ 1192 if (range_cnt != exp_ranges) { 1193 dev_warn( 1194 adev->dev, 1195 "NPS config mismatch - expected ranges: %d discovery - nps mode: %d, nps ranges: %d", 1196 exp_ranges, nps_type, range_cnt); 1197 ret = -EINVAL; 1198 goto err; 1199 } 1200 1201 for (i = 0; i < exp_ranges; ++i) { 1202 if (ranges[i].base_address >= ranges[i].limit_address) { 1203 dev_warn( 1204 adev->dev, 1205 "Invalid NPS range - nps mode: %d, range[%d]: base: %llx limit: %llx", 1206 nps_type, i, ranges[i].base_address, 1207 ranges[i].limit_address); 1208 ret = -EINVAL; 1209 goto err; 1210 } 1211 1212 /* Check for overlaps, not expecting any now */ 1213 for (j = i - 1; j >= 0; j--) { 1214 if (max(ranges[j].base_address, 1215 ranges[i].base_address) <= 1216 min(ranges[j].limit_address, 1217 ranges[i].limit_address)) { 1218 dev_warn( 1219 adev->dev, 1220 "overlapping ranges detected [ %llx - %llx ] | [%llx - %llx]", 1221 ranges[j].base_address, 1222 ranges[j].limit_address, 1223 ranges[i].base_address, 1224 ranges[i].limit_address); 1225 ret = -EINVAL; 1226 goto err; 1227 } 1228 } 1229 1230 mem_ranges[i].range.fpfn = 1231 (ranges[i].base_address - 1232 adev->vm_manager.vram_base_offset) >> 1233 AMDGPU_GPU_PAGE_SHIFT; 1234 mem_ranges[i].range.lpfn = 1235 (ranges[i].limit_address - 1236 adev->vm_manager.vram_base_offset) >> 1237 AMDGPU_GPU_PAGE_SHIFT; 1238 mem_ranges[i].size = 1239 ranges[i].limit_address - ranges[i].base_address + 1; 1240 } 1241 1242 err: 1243 kfree(ranges); 1244 1245 return ret; 1246 } 1247