1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 27 #include <linux/io-64-nonatomic-lo-hi.h> 28 #ifdef CONFIG_X86 29 #include <asm/hypervisor.h> 30 #endif 31 32 #include "amdgpu.h" 33 #include "amdgpu_gmc.h" 34 #include "amdgpu_ras.h" 35 #include "amdgpu_xgmi.h" 36 37 #include <drm/drm_drv.h> 38 #include <drm/ttm/ttm_tt.h> 39 40 /** 41 * amdgpu_gmc_pdb0_alloc - allocate vram for pdb0 42 * 43 * @adev: amdgpu_device pointer 44 * 45 * Allocate video memory for pdb0 and map it for CPU access 46 * Returns 0 for success, error for failure. 47 */ 48 int amdgpu_gmc_pdb0_alloc(struct amdgpu_device *adev) 49 { 50 int r; 51 struct amdgpu_bo_param bp; 52 u64 vram_size = adev->gmc.xgmi.node_segment_size * adev->gmc.xgmi.num_physical_nodes; 53 uint32_t pde0_page_shift = adev->gmc.vmid0_page_table_block_size + 21; 54 uint32_t npdes = (vram_size + (1ULL << pde0_page_shift) -1) >> pde0_page_shift; 55 56 memset(&bp, 0, sizeof(bp)); 57 bp.size = PAGE_ALIGN((npdes + 1) * 8); 58 bp.byte_align = PAGE_SIZE; 59 bp.domain = AMDGPU_GEM_DOMAIN_VRAM; 60 bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 61 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 62 bp.type = ttm_bo_type_kernel; 63 bp.resv = NULL; 64 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 65 66 r = amdgpu_bo_create(adev, &bp, &adev->gmc.pdb0_bo); 67 if (r) 68 return r; 69 70 r = amdgpu_bo_reserve(adev->gmc.pdb0_bo, false); 71 if (unlikely(r != 0)) 72 goto bo_reserve_failure; 73 74 r = amdgpu_bo_pin(adev->gmc.pdb0_bo, AMDGPU_GEM_DOMAIN_VRAM); 75 if (r) 76 goto bo_pin_failure; 77 r = amdgpu_bo_kmap(adev->gmc.pdb0_bo, &adev->gmc.ptr_pdb0); 78 if (r) 79 goto bo_kmap_failure; 80 81 amdgpu_bo_unreserve(adev->gmc.pdb0_bo); 82 return 0; 83 84 bo_kmap_failure: 85 amdgpu_bo_unpin(adev->gmc.pdb0_bo); 86 bo_pin_failure: 87 amdgpu_bo_unreserve(adev->gmc.pdb0_bo); 88 bo_reserve_failure: 89 amdgpu_bo_unref(&adev->gmc.pdb0_bo); 90 return r; 91 } 92 93 /** 94 * amdgpu_gmc_get_pde_for_bo - get the PDE for a BO 95 * 96 * @bo: the BO to get the PDE for 97 * @level: the level in the PD hirarchy 98 * @addr: resulting addr 99 * @flags: resulting flags 100 * 101 * Get the address and flags to be used for a PDE (Page Directory Entry). 102 */ 103 void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level, 104 uint64_t *addr, uint64_t *flags) 105 { 106 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 107 108 switch (bo->tbo.resource->mem_type) { 109 case TTM_PL_TT: 110 *addr = bo->tbo.ttm->dma_address[0]; 111 break; 112 case TTM_PL_VRAM: 113 *addr = amdgpu_bo_gpu_offset(bo); 114 break; 115 default: 116 *addr = 0; 117 break; 118 } 119 *flags = amdgpu_ttm_tt_pde_flags(bo->tbo.ttm, bo->tbo.resource); 120 amdgpu_gmc_get_vm_pde(adev, level, addr, flags); 121 } 122 123 /* 124 * amdgpu_gmc_pd_addr - return the address of the root directory 125 */ 126 uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo) 127 { 128 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 129 uint64_t pd_addr; 130 131 /* TODO: move that into ASIC specific code */ 132 if (adev->asic_type >= CHIP_VEGA10) { 133 uint64_t flags = AMDGPU_PTE_VALID; 134 135 amdgpu_gmc_get_pde_for_bo(bo, -1, &pd_addr, &flags); 136 pd_addr |= flags; 137 } else { 138 pd_addr = amdgpu_bo_gpu_offset(bo); 139 } 140 return pd_addr; 141 } 142 143 /** 144 * amdgpu_gmc_set_pte_pde - update the page tables using CPU 145 * 146 * @adev: amdgpu_device pointer 147 * @cpu_pt_addr: cpu address of the page table 148 * @gpu_page_idx: entry in the page table to update 149 * @addr: dst addr to write into pte/pde 150 * @flags: access flags 151 * 152 * Update the page tables using CPU. 153 */ 154 int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr, 155 uint32_t gpu_page_idx, uint64_t addr, 156 uint64_t flags) 157 { 158 void __iomem *ptr = (void *)cpu_pt_addr; 159 uint64_t value; 160 161 /* 162 * The following is for PTE only. GART does not have PDEs. 163 */ 164 value = addr & 0x0000FFFFFFFFF000ULL; 165 value |= flags; 166 writeq(value, ptr + (gpu_page_idx * 8)); 167 168 return 0; 169 } 170 171 /** 172 * amdgpu_gmc_agp_addr - return the address in the AGP address space 173 * 174 * @bo: TTM BO which needs the address, must be in GTT domain 175 * 176 * Tries to figure out how to access the BO through the AGP aperture. Returns 177 * AMDGPU_BO_INVALID_OFFSET if that is not possible. 178 */ 179 uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo) 180 { 181 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 182 183 if (bo->ttm->num_pages != 1 || bo->ttm->caching == ttm_cached) 184 return AMDGPU_BO_INVALID_OFFSET; 185 186 if (bo->ttm->dma_address[0] + PAGE_SIZE >= adev->gmc.agp_size) 187 return AMDGPU_BO_INVALID_OFFSET; 188 189 return adev->gmc.agp_start + bo->ttm->dma_address[0]; 190 } 191 192 /** 193 * amdgpu_gmc_vram_location - try to find VRAM location 194 * 195 * @adev: amdgpu device structure holding all necessary information 196 * @mc: memory controller structure holding memory information 197 * @base: base address at which to put VRAM 198 * 199 * Function will try to place VRAM at base address provided 200 * as parameter. 201 */ 202 void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc, 203 u64 base) 204 { 205 uint64_t limit = (uint64_t)amdgpu_vram_limit << 20; 206 207 mc->vram_start = base; 208 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 209 if (limit && limit < mc->real_vram_size) 210 mc->real_vram_size = limit; 211 212 if (mc->xgmi.num_physical_nodes == 0) { 213 mc->fb_start = mc->vram_start; 214 mc->fb_end = mc->vram_end; 215 } 216 dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", 217 mc->mc_vram_size >> 20, mc->vram_start, 218 mc->vram_end, mc->real_vram_size >> 20); 219 } 220 221 /** amdgpu_gmc_sysvm_location - place vram and gart in sysvm aperture 222 * 223 * @adev: amdgpu device structure holding all necessary information 224 * @mc: memory controller structure holding memory information 225 * 226 * This function is only used if use GART for FB translation. In such 227 * case, we use sysvm aperture (vmid0 page tables) for both vram 228 * and gart (aka system memory) access. 229 * 230 * GPUVM (and our organization of vmid0 page tables) require sysvm 231 * aperture to be placed at a location aligned with 8 times of native 232 * page size. For example, if vm_context0_cntl.page_table_block_size 233 * is 12, then native page size is 8G (2M*2^12), sysvm should start 234 * with a 64G aligned address. For simplicity, we just put sysvm at 235 * address 0. So vram start at address 0 and gart is right after vram. 236 */ 237 void amdgpu_gmc_sysvm_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc) 238 { 239 u64 hive_vram_start = 0; 240 u64 hive_vram_end = mc->xgmi.node_segment_size * mc->xgmi.num_physical_nodes - 1; 241 mc->vram_start = mc->xgmi.node_segment_size * mc->xgmi.physical_node_id; 242 mc->vram_end = mc->vram_start + mc->xgmi.node_segment_size - 1; 243 mc->gart_start = hive_vram_end + 1; 244 mc->gart_end = mc->gart_start + mc->gart_size - 1; 245 mc->fb_start = hive_vram_start; 246 mc->fb_end = hive_vram_end; 247 dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", 248 mc->mc_vram_size >> 20, mc->vram_start, 249 mc->vram_end, mc->real_vram_size >> 20); 250 dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n", 251 mc->gart_size >> 20, mc->gart_start, mc->gart_end); 252 } 253 254 /** 255 * amdgpu_gmc_gart_location - try to find GART location 256 * 257 * @adev: amdgpu device structure holding all necessary information 258 * @mc: memory controller structure holding memory information 259 * 260 * Function will place try to place GART before or after VRAM. 261 * If GART size is bigger than space left then we ajust GART size. 262 * Thus function will never fails. 263 */ 264 void amdgpu_gmc_gart_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc) 265 { 266 const uint64_t four_gb = 0x100000000ULL; 267 u64 size_af, size_bf; 268 /*To avoid the hole, limit the max mc address to AMDGPU_GMC_HOLE_START*/ 269 u64 max_mc_address = min(adev->gmc.mc_mask, AMDGPU_GMC_HOLE_START - 1); 270 271 /* VCE doesn't like it when BOs cross a 4GB segment, so align 272 * the GART base on a 4GB boundary as well. 273 */ 274 size_bf = mc->fb_start; 275 size_af = max_mc_address + 1 - ALIGN(mc->fb_end + 1, four_gb); 276 277 if (mc->gart_size > max(size_bf, size_af)) { 278 dev_warn(adev->dev, "limiting GART\n"); 279 mc->gart_size = max(size_bf, size_af); 280 } 281 282 if ((size_bf >= mc->gart_size && size_bf < size_af) || 283 (size_af < mc->gart_size)) 284 mc->gart_start = 0; 285 else 286 mc->gart_start = max_mc_address - mc->gart_size + 1; 287 288 mc->gart_start &= ~(four_gb - 1); 289 mc->gart_end = mc->gart_start + mc->gart_size - 1; 290 dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n", 291 mc->gart_size >> 20, mc->gart_start, mc->gart_end); 292 } 293 294 /** 295 * amdgpu_gmc_agp_location - try to find AGP location 296 * @adev: amdgpu device structure holding all necessary information 297 * @mc: memory controller structure holding memory information 298 * 299 * Function will place try to find a place for the AGP BAR in the MC address 300 * space. 301 * 302 * AGP BAR will be assigned the largest available hole in the address space. 303 * Should be called after VRAM and GART locations are setup. 304 */ 305 void amdgpu_gmc_agp_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc) 306 { 307 const uint64_t sixteen_gb = 1ULL << 34; 308 const uint64_t sixteen_gb_mask = ~(sixteen_gb - 1); 309 u64 size_af, size_bf; 310 311 if (amdgpu_sriov_vf(adev)) { 312 mc->agp_start = 0xffffffffffff; 313 mc->agp_end = 0x0; 314 mc->agp_size = 0; 315 316 return; 317 } 318 319 if (mc->fb_start > mc->gart_start) { 320 size_bf = (mc->fb_start & sixteen_gb_mask) - 321 ALIGN(mc->gart_end + 1, sixteen_gb); 322 size_af = mc->mc_mask + 1 - ALIGN(mc->fb_end + 1, sixteen_gb); 323 } else { 324 size_bf = mc->fb_start & sixteen_gb_mask; 325 size_af = (mc->gart_start & sixteen_gb_mask) - 326 ALIGN(mc->fb_end + 1, sixteen_gb); 327 } 328 329 if (size_bf > size_af) { 330 mc->agp_start = (mc->fb_start - size_bf) & sixteen_gb_mask; 331 mc->agp_size = size_bf; 332 } else { 333 mc->agp_start = ALIGN(mc->fb_end + 1, sixteen_gb); 334 mc->agp_size = size_af; 335 } 336 337 mc->agp_end = mc->agp_start + mc->agp_size - 1; 338 dev_info(adev->dev, "AGP: %lluM 0x%016llX - 0x%016llX\n", 339 mc->agp_size >> 20, mc->agp_start, mc->agp_end); 340 } 341 342 /** 343 * amdgpu_gmc_fault_key - get hask key from vm fault address and pasid 344 * 345 * @addr: 48 bit physical address, page aligned (36 significant bits) 346 * @pasid: 16 bit process address space identifier 347 */ 348 static inline uint64_t amdgpu_gmc_fault_key(uint64_t addr, uint16_t pasid) 349 { 350 return addr << 4 | pasid; 351 } 352 353 /** 354 * amdgpu_gmc_filter_faults - filter VM faults 355 * 356 * @adev: amdgpu device structure 357 * @ih: interrupt ring that the fault received from 358 * @addr: address of the VM fault 359 * @pasid: PASID of the process causing the fault 360 * @timestamp: timestamp of the fault 361 * 362 * Returns: 363 * True if the fault was filtered and should not be processed further. 364 * False if the fault is a new one and needs to be handled. 365 */ 366 bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, 367 struct amdgpu_ih_ring *ih, uint64_t addr, 368 uint16_t pasid, uint64_t timestamp) 369 { 370 struct amdgpu_gmc *gmc = &adev->gmc; 371 uint64_t stamp, key = amdgpu_gmc_fault_key(addr, pasid); 372 struct amdgpu_gmc_fault *fault; 373 uint32_t hash; 374 375 /* Stale retry fault if timestamp goes backward */ 376 if (amdgpu_ih_ts_after(timestamp, ih->processed_timestamp)) 377 return true; 378 379 /* If we don't have space left in the ring buffer return immediately */ 380 stamp = max(timestamp, AMDGPU_GMC_FAULT_TIMEOUT + 1) - 381 AMDGPU_GMC_FAULT_TIMEOUT; 382 if (gmc->fault_ring[gmc->last_fault].timestamp >= stamp) 383 return true; 384 385 /* Try to find the fault in the hash */ 386 hash = hash_64(key, AMDGPU_GMC_FAULT_HASH_ORDER); 387 fault = &gmc->fault_ring[gmc->fault_hash[hash].idx]; 388 while (fault->timestamp >= stamp) { 389 uint64_t tmp; 390 391 if (atomic64_read(&fault->key) == key) 392 return true; 393 394 tmp = fault->timestamp; 395 fault = &gmc->fault_ring[fault->next]; 396 397 /* Check if the entry was reused */ 398 if (fault->timestamp >= tmp) 399 break; 400 } 401 402 /* Add the fault to the ring */ 403 fault = &gmc->fault_ring[gmc->last_fault]; 404 atomic64_set(&fault->key, key); 405 fault->timestamp = timestamp; 406 407 /* And update the hash */ 408 fault->next = gmc->fault_hash[hash].idx; 409 gmc->fault_hash[hash].idx = gmc->last_fault++; 410 return false; 411 } 412 413 /** 414 * amdgpu_gmc_filter_faults_remove - remove address from VM faults filter 415 * 416 * @adev: amdgpu device structure 417 * @addr: address of the VM fault 418 * @pasid: PASID of the process causing the fault 419 * 420 * Remove the address from fault filter, then future vm fault on this address 421 * will pass to retry fault handler to recover. 422 */ 423 void amdgpu_gmc_filter_faults_remove(struct amdgpu_device *adev, uint64_t addr, 424 uint16_t pasid) 425 { 426 struct amdgpu_gmc *gmc = &adev->gmc; 427 uint64_t key = amdgpu_gmc_fault_key(addr, pasid); 428 struct amdgpu_gmc_fault *fault; 429 uint32_t hash; 430 uint64_t tmp; 431 432 hash = hash_64(key, AMDGPU_GMC_FAULT_HASH_ORDER); 433 fault = &gmc->fault_ring[gmc->fault_hash[hash].idx]; 434 do { 435 if (atomic64_cmpxchg(&fault->key, key, 0) == key) 436 break; 437 438 tmp = fault->timestamp; 439 fault = &gmc->fault_ring[fault->next]; 440 } while (fault->timestamp < tmp); 441 } 442 443 int amdgpu_gmc_ras_early_init(struct amdgpu_device *adev) 444 { 445 if (!adev->gmc.xgmi.connected_to_cpu) { 446 adev->gmc.xgmi.ras = &xgmi_ras; 447 amdgpu_ras_register_ras_block(adev, &adev->gmc.xgmi.ras->ras_block); 448 adev->gmc.xgmi.ras_if = &adev->gmc.xgmi.ras->ras_block.ras_comm; 449 } 450 451 return 0; 452 } 453 454 int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev) 455 { 456 return 0; 457 } 458 459 void amdgpu_gmc_ras_fini(struct amdgpu_device *adev) 460 { 461 462 } 463 464 /* 465 * The latest engine allocation on gfx9/10 is: 466 * Engine 2, 3: firmware 467 * Engine 0, 1, 4~16: amdgpu ring, 468 * subject to change when ring number changes 469 * Engine 17: Gart flushes 470 */ 471 #define GFXHUB_FREE_VM_INV_ENGS_BITMAP 0x1FFF3 472 #define MMHUB_FREE_VM_INV_ENGS_BITMAP 0x1FFF3 473 474 int amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_device *adev) 475 { 476 struct amdgpu_ring *ring; 477 unsigned vm_inv_engs[AMDGPU_MAX_VMHUBS] = 478 {GFXHUB_FREE_VM_INV_ENGS_BITMAP, MMHUB_FREE_VM_INV_ENGS_BITMAP, 479 GFXHUB_FREE_VM_INV_ENGS_BITMAP}; 480 unsigned i; 481 unsigned vmhub, inv_eng; 482 483 for (i = 0; i < adev->num_rings; ++i) { 484 ring = adev->rings[i]; 485 vmhub = ring->funcs->vmhub; 486 487 if (ring == &adev->mes.ring) 488 continue; 489 490 inv_eng = ffs(vm_inv_engs[vmhub]); 491 if (!inv_eng) { 492 dev_err(adev->dev, "no VM inv eng for ring %s\n", 493 ring->name); 494 return -EINVAL; 495 } 496 497 ring->vm_inv_eng = inv_eng - 1; 498 vm_inv_engs[vmhub] &= ~(1 << ring->vm_inv_eng); 499 500 dev_info(adev->dev, "ring %s uses VM inv eng %u on hub %u\n", 501 ring->name, ring->vm_inv_eng, ring->funcs->vmhub); 502 } 503 504 return 0; 505 } 506 507 /** 508 * amdgpu_gmc_tmz_set -- check and set if a device supports TMZ 509 * @adev: amdgpu_device pointer 510 * 511 * Check and set if an the device @adev supports Trusted Memory 512 * Zones (TMZ). 513 */ 514 void amdgpu_gmc_tmz_set(struct amdgpu_device *adev) 515 { 516 switch (adev->ip_versions[GC_HWIP][0]) { 517 /* RAVEN */ 518 case IP_VERSION(9, 2, 2): 519 case IP_VERSION(9, 1, 0): 520 /* RENOIR looks like RAVEN */ 521 case IP_VERSION(9, 3, 0): 522 /* GC 10.3.7 */ 523 case IP_VERSION(10, 3, 7): 524 if (amdgpu_tmz == 0) { 525 adev->gmc.tmz_enabled = false; 526 dev_info(adev->dev, 527 "Trusted Memory Zone (TMZ) feature disabled (cmd line)\n"); 528 } else { 529 adev->gmc.tmz_enabled = true; 530 dev_info(adev->dev, 531 "Trusted Memory Zone (TMZ) feature enabled\n"); 532 } 533 break; 534 case IP_VERSION(10, 1, 10): 535 case IP_VERSION(10, 1, 1): 536 case IP_VERSION(10, 1, 2): 537 case IP_VERSION(10, 1, 3): 538 case IP_VERSION(10, 3, 0): 539 case IP_VERSION(10, 3, 2): 540 case IP_VERSION(10, 3, 4): 541 case IP_VERSION(10, 3, 5): 542 /* VANGOGH */ 543 case IP_VERSION(10, 3, 1): 544 /* YELLOW_CARP*/ 545 case IP_VERSION(10, 3, 3): 546 case IP_VERSION(11, 0, 1): 547 /* Don't enable it by default yet. 548 */ 549 if (amdgpu_tmz < 1) { 550 adev->gmc.tmz_enabled = false; 551 dev_info(adev->dev, 552 "Trusted Memory Zone (TMZ) feature disabled as experimental (default)\n"); 553 } else { 554 adev->gmc.tmz_enabled = true; 555 dev_info(adev->dev, 556 "Trusted Memory Zone (TMZ) feature enabled as experimental (cmd line)\n"); 557 } 558 break; 559 default: 560 adev->gmc.tmz_enabled = false; 561 dev_info(adev->dev, 562 "Trusted Memory Zone (TMZ) feature not supported\n"); 563 break; 564 } 565 } 566 567 /** 568 * amdgpu_gmc_noretry_set -- set per asic noretry defaults 569 * @adev: amdgpu_device pointer 570 * 571 * Set a per asic default for the no-retry parameter. 572 * 573 */ 574 void amdgpu_gmc_noretry_set(struct amdgpu_device *adev) 575 { 576 struct amdgpu_gmc *gmc = &adev->gmc; 577 uint32_t gc_ver = adev->ip_versions[GC_HWIP][0]; 578 bool noretry_default = (gc_ver == IP_VERSION(9, 0, 1) || 579 gc_ver == IP_VERSION(9, 3, 0) || 580 gc_ver == IP_VERSION(9, 4, 0) || 581 gc_ver == IP_VERSION(9, 4, 1) || 582 gc_ver == IP_VERSION(9, 4, 2) || 583 gc_ver >= IP_VERSION(10, 3, 0)); 584 585 gmc->noretry = (amdgpu_noretry == -1) ? noretry_default : amdgpu_noretry; 586 } 587 588 void amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device *adev, int hub_type, 589 bool enable) 590 { 591 struct amdgpu_vmhub *hub; 592 u32 tmp, reg, i; 593 594 hub = &adev->vmhub[hub_type]; 595 for (i = 0; i < 16; i++) { 596 reg = hub->vm_context0_cntl + hub->ctx_distance * i; 597 598 tmp = (hub_type == AMDGPU_GFXHUB_0) ? 599 RREG32_SOC15_IP(GC, reg) : 600 RREG32_SOC15_IP(MMHUB, reg); 601 602 if (enable) 603 tmp |= hub->vm_cntx_cntl_vm_fault; 604 else 605 tmp &= ~hub->vm_cntx_cntl_vm_fault; 606 607 (hub_type == AMDGPU_GFXHUB_0) ? 608 WREG32_SOC15_IP(GC, reg, tmp) : 609 WREG32_SOC15_IP(MMHUB, reg, tmp); 610 } 611 } 612 613 void amdgpu_gmc_get_vbios_allocations(struct amdgpu_device *adev) 614 { 615 unsigned size; 616 617 /* 618 * Some ASICs need to reserve a region of video memory to avoid access 619 * from driver 620 */ 621 adev->mman.stolen_reserved_offset = 0; 622 adev->mman.stolen_reserved_size = 0; 623 624 /* 625 * TODO: 626 * Currently there is a bug where some memory client outside 627 * of the driver writes to first 8M of VRAM on S3 resume, 628 * this overrides GART which by default gets placed in first 8M and 629 * causes VM_FAULTS once GTT is accessed. 630 * Keep the stolen memory reservation until the while this is not solved. 631 */ 632 switch (adev->asic_type) { 633 case CHIP_VEGA10: 634 adev->mman.keep_stolen_vga_memory = true; 635 /* 636 * VEGA10 SRIOV VF with MS_HYPERV host needs some firmware reserved area. 637 */ 638 #ifdef CONFIG_X86 639 if (amdgpu_sriov_vf(adev) && hypervisor_is_type(X86_HYPER_MS_HYPERV)) { 640 adev->mman.stolen_reserved_offset = 0x500000; 641 adev->mman.stolen_reserved_size = 0x200000; 642 } 643 #endif 644 break; 645 case CHIP_RAVEN: 646 case CHIP_RENOIR: 647 adev->mman.keep_stolen_vga_memory = true; 648 break; 649 case CHIP_YELLOW_CARP: 650 if (amdgpu_discovery == 0) { 651 adev->mman.stolen_reserved_offset = 0x1ffb0000; 652 adev->mman.stolen_reserved_size = 64 * PAGE_SIZE; 653 } 654 break; 655 default: 656 adev->mman.keep_stolen_vga_memory = false; 657 break; 658 } 659 660 if (amdgpu_sriov_vf(adev) || 661 !amdgpu_device_has_display_hardware(adev)) { 662 size = 0; 663 } else { 664 size = amdgpu_gmc_get_vbios_fb_size(adev); 665 666 if (adev->mman.keep_stolen_vga_memory) 667 size = max(size, (unsigned)AMDGPU_VBIOS_VGA_ALLOCATION); 668 } 669 670 /* set to 0 if the pre-OS buffer uses up most of vram */ 671 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024)) 672 size = 0; 673 674 if (size > AMDGPU_VBIOS_VGA_ALLOCATION) { 675 adev->mman.stolen_vga_size = AMDGPU_VBIOS_VGA_ALLOCATION; 676 adev->mman.stolen_extended_size = size - adev->mman.stolen_vga_size; 677 } else { 678 adev->mman.stolen_vga_size = size; 679 adev->mman.stolen_extended_size = 0; 680 } 681 } 682 683 /** 684 * amdgpu_gmc_init_pdb0 - initialize PDB0 685 * 686 * @adev: amdgpu_device pointer 687 * 688 * This function is only used when GART page table is used 689 * for FB address translatioin. In such a case, we construct 690 * a 2-level system VM page table: PDB0->PTB, to cover both 691 * VRAM of the hive and system memory. 692 * 693 * PDB0 is static, initialized once on driver initialization. 694 * The first n entries of PDB0 are used as PTE by setting 695 * P bit to 1, pointing to VRAM. The n+1'th entry points 696 * to a big PTB covering system memory. 697 * 698 */ 699 void amdgpu_gmc_init_pdb0(struct amdgpu_device *adev) 700 { 701 int i; 702 uint64_t flags = adev->gart.gart_pte_flags; //TODO it is UC. explore NC/RW? 703 /* Each PDE0 (used as PTE) covers (2^vmid0_page_table_block_size)*2M 704 */ 705 u64 vram_size = adev->gmc.xgmi.node_segment_size * adev->gmc.xgmi.num_physical_nodes; 706 u64 pde0_page_size = (1ULL<<adev->gmc.vmid0_page_table_block_size)<<21; 707 u64 vram_addr = adev->vm_manager.vram_base_offset - 708 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 709 u64 vram_end = vram_addr + vram_size; 710 u64 gart_ptb_gpu_pa = amdgpu_gmc_vram_pa(adev, adev->gart.bo); 711 int idx; 712 713 if (!drm_dev_enter(adev_to_drm(adev), &idx)) 714 return; 715 716 flags |= AMDGPU_PTE_VALID | AMDGPU_PTE_READABLE; 717 flags |= AMDGPU_PTE_WRITEABLE; 718 flags |= AMDGPU_PTE_SNOOPED; 719 flags |= AMDGPU_PTE_FRAG((adev->gmc.vmid0_page_table_block_size + 9*1)); 720 flags |= AMDGPU_PDE_PTE; 721 722 /* The first n PDE0 entries are used as PTE, 723 * pointing to vram 724 */ 725 for (i = 0; vram_addr < vram_end; i++, vram_addr += pde0_page_size) 726 amdgpu_gmc_set_pte_pde(adev, adev->gmc.ptr_pdb0, i, vram_addr, flags); 727 728 /* The n+1'th PDE0 entry points to a huge 729 * PTB who has more than 512 entries each 730 * pointing to a 4K system page 731 */ 732 flags = AMDGPU_PTE_VALID; 733 flags |= AMDGPU_PDE_BFS(0) | AMDGPU_PTE_SNOOPED; 734 /* Requires gart_ptb_gpu_pa to be 4K aligned */ 735 amdgpu_gmc_set_pte_pde(adev, adev->gmc.ptr_pdb0, i, gart_ptb_gpu_pa, flags); 736 drm_dev_exit(idx); 737 } 738 739 /** 740 * amdgpu_gmc_vram_mc2pa - calculate vram buffer's physical address from MC 741 * address 742 * 743 * @adev: amdgpu_device pointer 744 * @mc_addr: MC address of buffer 745 */ 746 uint64_t amdgpu_gmc_vram_mc2pa(struct amdgpu_device *adev, uint64_t mc_addr) 747 { 748 return mc_addr - adev->gmc.vram_start + adev->vm_manager.vram_base_offset; 749 } 750 751 /** 752 * amdgpu_gmc_vram_pa - calculate vram buffer object's physical address from 753 * GPU's view 754 * 755 * @adev: amdgpu_device pointer 756 * @bo: amdgpu buffer object 757 */ 758 uint64_t amdgpu_gmc_vram_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo) 759 { 760 return amdgpu_gmc_vram_mc2pa(adev, amdgpu_bo_gpu_offset(bo)); 761 } 762 763 /** 764 * amdgpu_gmc_vram_cpu_pa - calculate vram buffer object's physical address 765 * from CPU's view 766 * 767 * @adev: amdgpu_device pointer 768 * @bo: amdgpu buffer object 769 */ 770 uint64_t amdgpu_gmc_vram_cpu_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo) 771 { 772 return amdgpu_bo_gpu_offset(bo) - adev->gmc.vram_start + adev->gmc.aper_base; 773 } 774 775 int amdgpu_gmc_vram_checking(struct amdgpu_device *adev) 776 { 777 struct amdgpu_bo *vram_bo = NULL; 778 uint64_t vram_gpu = 0; 779 void *vram_ptr = NULL; 780 781 int ret, size = 0x100000; 782 uint8_t cptr[10]; 783 784 ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE, 785 AMDGPU_GEM_DOMAIN_VRAM, 786 &vram_bo, 787 &vram_gpu, 788 &vram_ptr); 789 if (ret) 790 return ret; 791 792 memset(vram_ptr, 0x86, size); 793 memset(cptr, 0x86, 10); 794 795 /** 796 * Check the start, the mid, and the end of the memory if the content of 797 * each byte is the pattern "0x86". If yes, we suppose the vram bo is 798 * workable. 799 * 800 * Note: If check the each byte of whole 1M bo, it will cost too many 801 * seconds, so here, we just pick up three parts for emulation. 802 */ 803 ret = memcmp(vram_ptr, cptr, 10); 804 if (ret) 805 return ret; 806 807 ret = memcmp(vram_ptr + (size / 2), cptr, 10); 808 if (ret) 809 return ret; 810 811 ret = memcmp(vram_ptr + size - 10, cptr, 10); 812 if (ret) 813 return ret; 814 815 amdgpu_bo_free_kernel(&vram_bo, &vram_gpu, 816 &vram_ptr); 817 818 return 0; 819 } 820