1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_GFX_H__ 25 #define __AMDGPU_GFX_H__ 26 27 /* 28 * GFX stuff 29 */ 30 #include "clearstate_defs.h" 31 #include "amdgpu_ring.h" 32 #include "amdgpu_rlc.h" 33 #include "amdgpu_imu.h" 34 #include "soc15.h" 35 #include "amdgpu_ras.h" 36 #include "amdgpu_ring_mux.h" 37 #include "amdgpu_xcp.h" 38 39 /* GFX current status */ 40 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L 41 #define AMDGPU_GFX_SAFE_MODE 0x00000001L 42 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L 43 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L 44 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L 45 46 #define AMDGPU_MAX_GC_INSTANCES 8 47 #define AMDGPU_MAX_QUEUES 128 48 49 #define AMDGPU_MAX_GFX_QUEUES AMDGPU_MAX_QUEUES 50 #define AMDGPU_MAX_COMPUTE_QUEUES AMDGPU_MAX_QUEUES 51 52 enum amdgpu_gfx_pipe_priority { 53 AMDGPU_GFX_PIPE_PRIO_NORMAL = AMDGPU_RING_PRIO_1, 54 AMDGPU_GFX_PIPE_PRIO_HIGH = AMDGPU_RING_PRIO_2 55 }; 56 57 #define AMDGPU_GFX_QUEUE_PRIORITY_MINIMUM 0 58 #define AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM 15 59 60 /* 1 second timeout */ 61 #define GFX_PROFILE_IDLE_TIMEOUT msecs_to_jiffies(1000) 62 63 enum amdgpu_gfx_partition { 64 AMDGPU_SPX_PARTITION_MODE = 0, 65 AMDGPU_DPX_PARTITION_MODE = 1, 66 AMDGPU_TPX_PARTITION_MODE = 2, 67 AMDGPU_QPX_PARTITION_MODE = 3, 68 AMDGPU_CPX_PARTITION_MODE = 4, 69 AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE = -1, 70 /* Automatically choose the right mode */ 71 AMDGPU_AUTO_COMPUTE_PARTITION_MODE = -2, 72 }; 73 74 enum amdgpu_gfx_partition_mem_alloc_mode { 75 AMDGPU_PARTITION_MEM_CAPPING_EVEN = 0, 76 AMDGPU_PARTITION_MEM_ALLOC_ALL = 1, 77 }; 78 79 #define NUM_XCC(x) hweight16(x) 80 81 enum amdgpu_gfx_ras_mem_id_type { 82 AMDGPU_GFX_CP_MEM = 0, 83 AMDGPU_GFX_GCEA_MEM, 84 AMDGPU_GFX_GC_CANE_MEM, 85 AMDGPU_GFX_GCUTCL2_MEM, 86 AMDGPU_GFX_GDS_MEM, 87 AMDGPU_GFX_LDS_MEM, 88 AMDGPU_GFX_RLC_MEM, 89 AMDGPU_GFX_SP_MEM, 90 AMDGPU_GFX_SPI_MEM, 91 AMDGPU_GFX_SQC_MEM, 92 AMDGPU_GFX_SQ_MEM, 93 AMDGPU_GFX_TA_MEM, 94 AMDGPU_GFX_TCC_MEM, 95 AMDGPU_GFX_TCA_MEM, 96 AMDGPU_GFX_TCI_MEM, 97 AMDGPU_GFX_TCP_MEM, 98 AMDGPU_GFX_TD_MEM, 99 AMDGPU_GFX_TCX_MEM, 100 AMDGPU_GFX_ATC_L2_MEM, 101 AMDGPU_GFX_UTCL2_MEM, 102 AMDGPU_GFX_VML2_MEM, 103 AMDGPU_GFX_VML2_WALKER_MEM, 104 AMDGPU_GFX_MEM_TYPE_NUM 105 }; 106 107 struct amdgpu_mec { 108 struct amdgpu_bo *hpd_eop_obj; 109 u64 hpd_eop_gpu_addr; 110 struct amdgpu_bo *mec_fw_obj; 111 u64 mec_fw_gpu_addr; 112 struct amdgpu_bo *mec_fw_data_obj; 113 u64 mec_fw_data_gpu_addr; 114 115 u32 num_mec; 116 u32 num_pipe_per_mec; 117 u32 num_queue_per_pipe; 118 void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS * AMDGPU_MAX_GC_INSTANCES]; 119 }; 120 121 struct amdgpu_mec_bitmap { 122 /* These are the resources for which amdgpu takes ownership */ 123 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 124 }; 125 126 enum amdgpu_unmap_queues_action { 127 PREEMPT_QUEUES = 0, 128 RESET_QUEUES, 129 DISABLE_PROCESS_QUEUES, 130 PREEMPT_QUEUES_NO_UNMAP, 131 }; 132 133 struct kiq_pm4_funcs { 134 /* Support ASIC-specific kiq pm4 packets*/ 135 void (*kiq_set_resources)(struct amdgpu_ring *kiq_ring, 136 uint64_t queue_mask); 137 void (*kiq_map_queues)(struct amdgpu_ring *kiq_ring, 138 struct amdgpu_ring *ring); 139 void (*kiq_unmap_queues)(struct amdgpu_ring *kiq_ring, 140 struct amdgpu_ring *ring, 141 enum amdgpu_unmap_queues_action action, 142 u64 gpu_addr, u64 seq); 143 void (*kiq_query_status)(struct amdgpu_ring *kiq_ring, 144 struct amdgpu_ring *ring, 145 u64 addr, 146 u64 seq); 147 void (*kiq_invalidate_tlbs)(struct amdgpu_ring *kiq_ring, 148 uint16_t pasid, uint32_t flush_type, 149 bool all_hub); 150 void (*kiq_reset_hw_queue)(struct amdgpu_ring *kiq_ring, 151 uint32_t queue_type, uint32_t me_id, 152 uint32_t pipe_id, uint32_t queue_id, 153 uint32_t xcc_id, uint32_t vmid); 154 /* Packet sizes */ 155 int set_resources_size; 156 int map_queues_size; 157 int unmap_queues_size; 158 int query_status_size; 159 int invalidate_tlbs_size; 160 }; 161 162 struct amdgpu_kiq { 163 u64 eop_gpu_addr; 164 struct amdgpu_bo *eop_obj; 165 spinlock_t ring_lock; 166 struct amdgpu_ring ring; 167 struct amdgpu_irq_src irq; 168 const struct kiq_pm4_funcs *pmf; 169 void *mqd_backup; 170 }; 171 172 /* 173 * GFX configurations 174 */ 175 #define AMDGPU_GFX_MAX_SE 4 176 #define AMDGPU_GFX_MAX_SH_PER_SE 2 177 178 /** 179 * amdgpu_rb_config - Configure a single Render Backend (RB) 180 * 181 * Bad RBs are fused off and there is a harvest register the driver reads to 182 * determine which RB(s) are fused off so that the driver can configure the 183 * hardware state so that nothing gets sent to them. There are also user 184 * harvest registers that the driver can program to disable additional RBs, 185 * etc., for testing purposes. 186 */ 187 struct amdgpu_rb_config { 188 /** 189 * @rb_backend_disable: 190 * 191 * The value captured from register RB_BACKEND_DISABLE indicates if the 192 * RB backend is disabled or not. 193 */ 194 uint32_t rb_backend_disable; 195 196 /** 197 * @user_rb_backend_disable: 198 * 199 * The value captured from register USER_RB_BACKEND_DISABLE indicates 200 * if the User RB backend is disabled or not. 201 */ 202 uint32_t user_rb_backend_disable; 203 204 /** 205 * @raster_config: 206 * 207 * To set up all of the states, it is necessary to have two registers 208 * to keep all of the states. This field holds the first register. 209 */ 210 uint32_t raster_config; 211 212 /** 213 * @raster_config_1: 214 * 215 * To set up all of the states, it is necessary to have two registers 216 * to keep all of the states. This field holds the second register. 217 */ 218 uint32_t raster_config_1; 219 }; 220 221 struct gb_addr_config { 222 uint16_t pipe_interleave_size; 223 uint8_t num_pipes; 224 uint8_t max_compress_frags; 225 uint8_t num_banks; 226 uint8_t num_se; 227 uint8_t num_rb_per_se; 228 uint8_t num_pkrs; 229 }; 230 231 struct amdgpu_gfx_config { 232 unsigned max_shader_engines; 233 unsigned max_tile_pipes; 234 unsigned max_cu_per_sh; 235 unsigned max_sh_per_se; 236 unsigned max_backends_per_se; 237 unsigned max_texture_channel_caches; 238 unsigned max_gprs; 239 unsigned max_gs_threads; 240 unsigned max_hw_contexts; 241 unsigned sc_prim_fifo_size_frontend; 242 unsigned sc_prim_fifo_size_backend; 243 unsigned sc_hiz_tile_fifo_size; 244 unsigned sc_earlyz_tile_fifo_size; 245 246 unsigned num_tile_pipes; 247 unsigned backend_enable_mask; 248 unsigned mem_max_burst_length_bytes; 249 unsigned mem_row_size_in_kb; 250 unsigned shader_engine_tile_size; 251 unsigned num_gpus; 252 unsigned multi_gpu_tile_size; 253 unsigned mc_arb_ramcfg; 254 unsigned num_banks; 255 unsigned num_ranks; 256 unsigned gb_addr_config; 257 unsigned num_rbs; 258 unsigned gs_vgt_table_depth; 259 unsigned gs_prim_buffer_depth; 260 261 uint32_t tile_mode_array[32]; 262 uint32_t macrotile_mode_array[16]; 263 264 struct gb_addr_config gb_addr_config_fields; 265 266 /** 267 * @rb_config: 268 * 269 * Matrix that keeps all the Render Backend (color and depth buffer 270 * handling) configuration on the 3D engine. 271 */ 272 struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE]; 273 274 /* gfx configure feature */ 275 uint32_t double_offchip_lds_buf; 276 /* cached value of DB_DEBUG2 */ 277 uint32_t db_debug2; 278 /* gfx10 specific config */ 279 uint32_t num_sc_per_sh; 280 uint32_t num_packer_per_sc; 281 uint32_t pa_sc_tile_steering_override; 282 /* Whether texture coordinate truncation is conformant. */ 283 bool ta_cntl2_truncate_coord_mode; 284 uint64_t tcc_disabled_mask; 285 uint32_t gc_num_tcp_per_sa; 286 uint32_t gc_num_sdp_interface; 287 uint32_t gc_num_tcps; 288 uint32_t gc_num_tcp_per_wpg; 289 uint32_t gc_tcp_l1_size; 290 uint32_t gc_num_sqc_per_wgp; 291 uint32_t gc_l1_instruction_cache_size_per_sqc; 292 uint32_t gc_l1_data_cache_size_per_sqc; 293 uint32_t gc_gl1c_per_sa; 294 uint32_t gc_gl1c_size_per_instance; 295 uint32_t gc_gl2c_per_gpu; 296 uint32_t gc_tcp_size_per_cu; 297 uint32_t gc_num_cu_per_sqc; 298 uint32_t gc_tcc_size; 299 uint32_t gc_tcp_cache_line_size; 300 uint32_t gc_instruction_cache_size_per_sqc; 301 uint32_t gc_instruction_cache_line_size; 302 uint32_t gc_scalar_data_cache_size_per_sqc; 303 uint32_t gc_scalar_data_cache_line_size; 304 uint32_t gc_tcc_cache_line_size; 305 }; 306 307 struct amdgpu_cu_info { 308 uint32_t simd_per_cu; 309 uint32_t max_waves_per_simd; 310 uint32_t wave_front_size; 311 uint32_t max_scratch_slots_per_cu; 312 uint32_t lds_size; 313 314 /* total active CU number */ 315 uint32_t number; 316 uint32_t ao_cu_mask; 317 uint32_t ao_cu_bitmap[4][4]; 318 uint32_t bitmap[AMDGPU_MAX_GC_INSTANCES][4][4]; 319 }; 320 321 struct amdgpu_gfx_ras { 322 struct amdgpu_ras_block_object ras_block; 323 void (*enable_watchdog_timer)(struct amdgpu_device *adev); 324 int (*rlc_gc_fed_irq)(struct amdgpu_device *adev, 325 struct amdgpu_irq_src *source, 326 struct amdgpu_iv_entry *entry); 327 int (*poison_consumption_handler)(struct amdgpu_device *adev, 328 struct amdgpu_iv_entry *entry); 329 }; 330 331 struct amdgpu_gfx_shadow_info { 332 u32 shadow_size; 333 u32 shadow_alignment; 334 u32 csa_size; 335 u32 csa_alignment; 336 u32 eop_size; 337 u32 eop_alignment; 338 }; 339 340 struct amdgpu_gfx_funcs { 341 /* get the gpu clock counter */ 342 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev); 343 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, 344 u32 sh_num, u32 instance, int xcc_id); 345 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 346 uint32_t wave, uint32_t *dst, int *no_fields); 347 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 348 uint32_t wave, uint32_t thread, uint32_t start, 349 uint32_t size, uint32_t *dst); 350 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 351 uint32_t wave, uint32_t start, uint32_t size, 352 uint32_t *dst); 353 void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe, 354 u32 queue, u32 vmid, u32 xcc_id); 355 void (*init_spm_golden)(struct amdgpu_device *adev); 356 void (*update_perfmon_mgcg)(struct amdgpu_device *adev, bool enable); 357 int (*get_gfx_shadow_info)(struct amdgpu_device *adev, 358 struct amdgpu_gfx_shadow_info *shadow_info, 359 bool skip_check); 360 enum amdgpu_gfx_partition 361 (*query_partition_mode)(struct amdgpu_device *adev); 362 int (*switch_partition_mode)(struct amdgpu_device *adev, 363 int num_xccs_per_xcp); 364 int (*ih_node_to_logical_xcc)(struct amdgpu_device *adev, int ih_node); 365 int (*get_xccs_per_xcp)(struct amdgpu_device *adev); 366 void (*get_hdp_flush_mask)(struct amdgpu_ring *ring, 367 uint32_t *ref_and_mask, uint32_t *reg_mem_engine); 368 }; 369 370 struct sq_work { 371 struct work_struct work; 372 unsigned ih_data; 373 }; 374 375 struct amdgpu_pfp { 376 struct amdgpu_bo *pfp_fw_obj; 377 uint64_t pfp_fw_gpu_addr; 378 uint32_t *pfp_fw_ptr; 379 380 struct amdgpu_bo *pfp_fw_data_obj; 381 uint64_t pfp_fw_data_gpu_addr; 382 uint32_t *pfp_fw_data_ptr; 383 }; 384 385 struct amdgpu_ce { 386 struct amdgpu_bo *ce_fw_obj; 387 uint64_t ce_fw_gpu_addr; 388 uint32_t *ce_fw_ptr; 389 }; 390 391 struct amdgpu_me { 392 struct amdgpu_bo *me_fw_obj; 393 uint64_t me_fw_gpu_addr; 394 uint32_t *me_fw_ptr; 395 396 struct amdgpu_bo *me_fw_data_obj; 397 uint64_t me_fw_data_gpu_addr; 398 uint32_t *me_fw_data_ptr; 399 400 uint32_t num_me; 401 uint32_t num_pipe_per_me; 402 uint32_t num_queue_per_pipe; 403 void *mqd_backup[AMDGPU_MAX_GFX_RINGS]; 404 405 /* These are the resources for which amdgpu takes ownership */ 406 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 407 }; 408 409 struct amdgpu_isolation_work { 410 struct amdgpu_device *adev; 411 u32 xcp_id; 412 struct delayed_work work; 413 }; 414 415 struct amdgpu_gfx { 416 struct mutex gpu_clock_mutex; 417 struct amdgpu_gfx_config config; 418 struct amdgpu_rlc rlc; 419 struct amdgpu_pfp pfp; 420 struct amdgpu_ce ce; 421 struct amdgpu_me me; 422 struct amdgpu_mec mec; 423 struct amdgpu_mec_bitmap mec_bitmap[AMDGPU_MAX_GC_INSTANCES]; 424 struct amdgpu_kiq kiq[AMDGPU_MAX_GC_INSTANCES]; 425 struct amdgpu_imu imu; 426 bool rs64_enable; /* firmware format */ 427 const struct firmware *me_fw; /* ME firmware */ 428 uint32_t me_fw_version; 429 const struct firmware *pfp_fw; /* PFP firmware */ 430 uint32_t pfp_fw_version; 431 const struct firmware *ce_fw; /* CE firmware */ 432 uint32_t ce_fw_version; 433 const struct firmware *rlc_fw; /* RLC firmware */ 434 uint32_t rlc_fw_version; 435 const struct firmware *mec_fw; /* MEC firmware */ 436 uint32_t mec_fw_version; 437 const struct firmware *mec2_fw; /* MEC2 firmware */ 438 uint32_t mec2_fw_version; 439 const struct firmware *imu_fw; /* IMU firmware */ 440 uint32_t imu_fw_version; 441 uint32_t me_feature_version; 442 uint32_t ce_feature_version; 443 uint32_t pfp_feature_version; 444 uint32_t rlc_feature_version; 445 uint32_t rlc_srlc_fw_version; 446 uint32_t rlc_srlc_feature_version; 447 uint32_t rlc_srlg_fw_version; 448 uint32_t rlc_srlg_feature_version; 449 uint32_t rlc_srls_fw_version; 450 uint32_t rlc_srls_feature_version; 451 uint32_t rlcp_ucode_version; 452 uint32_t rlcp_ucode_feature_version; 453 uint32_t rlcv_ucode_version; 454 uint32_t rlcv_ucode_feature_version; 455 uint32_t mec_feature_version; 456 uint32_t mec2_feature_version; 457 bool mec_fw_write_wait; 458 bool me_fw_write_wait; 459 bool cp_fw_write_wait; 460 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS]; 461 unsigned num_gfx_rings; 462 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS * AMDGPU_MAX_GC_INSTANCES]; 463 unsigned num_compute_rings; 464 struct amdgpu_irq_src eop_irq; 465 struct amdgpu_irq_src priv_reg_irq; 466 struct amdgpu_irq_src priv_inst_irq; 467 struct amdgpu_irq_src bad_op_irq; 468 struct amdgpu_irq_src cp_ecc_error_irq; 469 struct amdgpu_irq_src sq_irq; 470 struct amdgpu_irq_src rlc_gc_fed_irq; 471 struct amdgpu_irq_src rlc_poison_irq; 472 struct sq_work sq_work; 473 474 /* gfx status */ 475 uint32_t gfx_current_status; 476 /* ce ram size*/ 477 unsigned ce_ram_size; 478 struct amdgpu_cu_info cu_info; 479 const struct amdgpu_gfx_funcs *funcs; 480 481 /* reset mask */ 482 uint32_t grbm_soft_reset; 483 uint32_t srbm_soft_reset; 484 uint32_t gfx_supported_reset; 485 uint32_t compute_supported_reset; 486 487 /* gfx off */ 488 bool gfx_off_state; /* true: enabled, false: disabled */ 489 struct mutex gfx_off_mutex; /* mutex to change gfxoff state */ 490 uint32_t gfx_off_req_count; /* default 1, enable gfx off: dec 1, disable gfx off: add 1 */ 491 struct delayed_work gfx_off_delay_work; /* async work to set gfx block off */ 492 uint32_t gfx_off_residency; /* last logged residency */ 493 uint64_t gfx_off_entrycount; /* count of times GPU has get into GFXOFF state */ 494 495 /* pipe reservation */ 496 struct mutex pipe_reserve_mutex; 497 DECLARE_BITMAP (pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 498 499 /*ras */ 500 struct ras_common_if *ras_if; 501 struct amdgpu_gfx_ras *ras; 502 503 bool is_poweron; 504 505 struct amdgpu_ring sw_gfx_ring[AMDGPU_MAX_SW_GFX_RINGS]; 506 struct amdgpu_ring_mux muxer; 507 508 bool cp_gfx_shadow; /* for gfx11 */ 509 510 uint16_t xcc_mask; 511 uint32_t num_xcc_per_xcp; 512 struct mutex partition_mutex; 513 bool mcbp; /* mid command buffer preemption */ 514 515 /* IP reg dump */ 516 uint32_t *ip_dump_core; 517 uint32_t *ip_dump_compute_queues; 518 uint32_t *ip_dump_gfx_queues; 519 520 struct mutex reset_sem_mutex; 521 522 /* cleaner shader */ 523 struct amdgpu_bo *cleaner_shader_obj; 524 unsigned int cleaner_shader_size; 525 u64 cleaner_shader_gpu_addr; 526 void *cleaner_shader_cpu_ptr; 527 const void *cleaner_shader_ptr; 528 bool enable_cleaner_shader; 529 struct amdgpu_isolation_work enforce_isolation[MAX_XCP]; 530 /* Mutex for synchronizing KFD scheduler operations */ 531 struct mutex userq_sch_mutex; 532 u64 userq_sch_req_count[MAX_XCP]; 533 bool userq_sch_inactive[MAX_XCP]; 534 unsigned long enforce_isolation_jiffies[MAX_XCP]; 535 unsigned long enforce_isolation_time[MAX_XCP]; 536 537 atomic_t total_submission_cnt; 538 struct delayed_work idle_work; 539 bool workload_profile_active; 540 struct mutex workload_profile_mutex; 541 542 bool disable_kq; 543 bool disable_uq; 544 }; 545 546 struct amdgpu_gfx_ras_reg_entry { 547 struct amdgpu_ras_err_status_reg_entry reg_entry; 548 enum amdgpu_gfx_ras_mem_id_type mem_id_type; 549 uint32_t se_num; 550 }; 551 552 struct amdgpu_gfx_ras_mem_id_entry { 553 const struct amdgpu_ras_memory_id_entry *mem_id_ent; 554 uint32_t size; 555 }; 556 557 #define AMDGPU_GFX_MEMID_ENT(x) {(x), ARRAY_SIZE(x)}, 558 559 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev)) 560 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance, xcc_id) ((adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance), (xcc_id))) 561 #define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid, xcc_id) ((adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q), (vmid), (xcc_id))) 562 #define amdgpu_gfx_init_spm_golden(adev) (adev)->gfx.funcs->init_spm_golden((adev)) 563 #define amdgpu_gfx_get_gfx_shadow_info(adev, si) ((adev)->gfx.funcs->get_gfx_shadow_info((adev), (si), false)) 564 565 /** 566 * amdgpu_gfx_create_bitmask - create a bitmask 567 * 568 * @bit_width: length of the mask 569 * 570 * create a variable length bit mask. 571 * Returns the bitmask. 572 */ 573 static inline u32 amdgpu_gfx_create_bitmask(u32 bit_width) 574 { 575 return (u32)((1ULL << bit_width) - 1); 576 } 577 578 void amdgpu_gfx_parse_disable_cu(struct amdgpu_device *adev, unsigned int *mask, 579 unsigned int max_se, unsigned int max_sh); 580 581 int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev, int xcc_id); 582 583 void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring); 584 585 void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev, int xcc_id); 586 int amdgpu_gfx_kiq_init(struct amdgpu_device *adev, 587 unsigned hpd_size, int xcc_id); 588 589 int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev, 590 unsigned mqd_size, int xcc_id); 591 void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev, int xcc_id); 592 void amdgpu_gfx_mqd_symmetrically_map_cu_mask(struct amdgpu_device *adev, const uint32_t *cu_mask, 593 uint32_t cu_mask_count, uint32_t *se_mask); 594 int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev, int xcc_id); 595 int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev, int xcc_id); 596 int amdgpu_gfx_disable_kgq(struct amdgpu_device *adev, int xcc_id); 597 int amdgpu_gfx_enable_kgq(struct amdgpu_device *adev, int xcc_id); 598 599 void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev); 600 void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev); 601 602 int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec, 603 int pipe, int queue); 604 void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit, 605 int *mec, int *pipe, int *queue); 606 bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int xcc_id, 607 int mec, int pipe, int queue); 608 bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev, 609 struct amdgpu_ring *ring); 610 bool amdgpu_gfx_is_high_priority_graphics_queue(struct amdgpu_device *adev, 611 struct amdgpu_ring *ring); 612 bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me, 613 int pipe, int queue); 614 void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable); 615 void amdgpu_gfx_off_ctrl_immediate(struct amdgpu_device *adev, bool enable); 616 int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value); 617 int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block); 618 void amdgpu_gfx_ras_fini(struct amdgpu_device *adev); 619 int amdgpu_get_gfx_off_entrycount(struct amdgpu_device *adev, u64 *value); 620 int amdgpu_get_gfx_off_residency(struct amdgpu_device *adev, u32 *residency); 621 int amdgpu_set_gfx_off_residency(struct amdgpu_device *adev, bool value); 622 int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev, 623 void *err_data, 624 struct amdgpu_iv_entry *entry); 625 int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev, 626 struct amdgpu_irq_src *source, 627 struct amdgpu_iv_entry *entry); 628 uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg, uint32_t xcc_id); 629 void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, uint32_t xcc_id); 630 void amdgpu_gfx_get_hdp_flush_mask(struct amdgpu_ring *ring, 631 uint32_t *ref_and_mask, uint32_t *reg_mem_engine); 632 int amdgpu_kiq_hdp_flush(struct amdgpu_device *adev); 633 int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev); 634 void amdgpu_gfx_cp_init_microcode(struct amdgpu_device *adev, uint32_t ucode_id); 635 636 int amdgpu_gfx_ras_sw_init(struct amdgpu_device *adev); 637 int amdgpu_gfx_poison_consumption_handler(struct amdgpu_device *adev, 638 struct amdgpu_iv_entry *entry); 639 640 bool amdgpu_gfx_is_master_xcc(struct amdgpu_device *adev, int xcc_id); 641 int amdgpu_gfx_sysfs_init(struct amdgpu_device *adev); 642 void amdgpu_gfx_sysfs_fini(struct amdgpu_device *adev); 643 void amdgpu_gfx_ras_error_func(struct amdgpu_device *adev, 644 void *ras_error_status, 645 void (*func)(struct amdgpu_device *adev, void *ras_error_status, 646 int xcc_id)); 647 int amdgpu_gfx_cleaner_shader_sw_init(struct amdgpu_device *adev, 648 unsigned int cleaner_shader_size); 649 void amdgpu_gfx_cleaner_shader_sw_fini(struct amdgpu_device *adev); 650 void amdgpu_gfx_cleaner_shader_init(struct amdgpu_device *adev, 651 unsigned int cleaner_shader_size, 652 const void *cleaner_shader_ptr); 653 void amdgpu_gfx_enforce_isolation_handler(struct work_struct *work); 654 void amdgpu_gfx_enforce_isolation_ring_begin_use(struct amdgpu_ring *ring); 655 void amdgpu_gfx_enforce_isolation_ring_end_use(struct amdgpu_ring *ring); 656 657 void amdgpu_gfx_profile_idle_work_handler(struct work_struct *work); 658 void amdgpu_gfx_profile_ring_begin_use(struct amdgpu_ring *ring); 659 void amdgpu_gfx_profile_ring_end_use(struct amdgpu_ring *ring); 660 u32 amdgpu_gfx_csb_preamble_start(u32 *buffer); 661 u32 amdgpu_gfx_csb_data_parser(struct amdgpu_device *adev, u32 *buffer, u32 count); 662 void amdgpu_gfx_csb_preamble_end(u32 *buffer, u32 count); 663 664 void amdgpu_debugfs_gfx_sched_mask_init(struct amdgpu_device *adev); 665 void amdgpu_debugfs_compute_sched_mask_init(struct amdgpu_device *adev); 666 667 static inline const char *amdgpu_gfx_compute_mode_desc(int mode) 668 { 669 switch (mode) { 670 case AMDGPU_SPX_PARTITION_MODE: 671 return "SPX"; 672 case AMDGPU_DPX_PARTITION_MODE: 673 return "DPX"; 674 case AMDGPU_TPX_PARTITION_MODE: 675 return "TPX"; 676 case AMDGPU_QPX_PARTITION_MODE: 677 return "QPX"; 678 case AMDGPU_CPX_PARTITION_MODE: 679 return "CPX"; 680 default: 681 return "UNKNOWN"; 682 } 683 } 684 685 static inline const char *amdgpu_gfx_compute_mem_alloc_mode_desc(int mode) 686 { 687 switch (mode) { 688 case AMDGPU_PARTITION_MEM_CAPPING_EVEN: 689 return "CAPPING"; 690 case AMDGPU_PARTITION_MEM_ALLOC_ALL: 691 return "ALL"; 692 default: 693 return "UNKNOWN"; 694 } 695 } 696 697 #endif 698