1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_GFX_H__ 25 #define __AMDGPU_GFX_H__ 26 27 /* 28 * GFX stuff 29 */ 30 #include "clearstate_defs.h" 31 #include "amdgpu_ring.h" 32 #include "amdgpu_rlc.h" 33 #include "amdgpu_imu.h" 34 #include "soc15.h" 35 #include "amdgpu_ras.h" 36 #include "amdgpu_ring_mux.h" 37 #include "amdgpu_xcp.h" 38 39 /* GFX current status */ 40 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L 41 #define AMDGPU_GFX_SAFE_MODE 0x00000001L 42 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L 43 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L 44 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L 45 46 #define AMDGPU_MAX_GC_INSTANCES 8 47 #define AMDGPU_MAX_QUEUES 128 48 49 #define AMDGPU_MAX_GFX_QUEUES AMDGPU_MAX_QUEUES 50 #define AMDGPU_MAX_COMPUTE_QUEUES AMDGPU_MAX_QUEUES 51 52 enum amdgpu_gfx_pipe_priority { 53 AMDGPU_GFX_PIPE_PRIO_NORMAL = AMDGPU_RING_PRIO_1, 54 AMDGPU_GFX_PIPE_PRIO_HIGH = AMDGPU_RING_PRIO_2 55 }; 56 57 #define AMDGPU_GFX_QUEUE_PRIORITY_MINIMUM 0 58 #define AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM 15 59 60 /* 1 second timeout */ 61 #define GFX_PROFILE_IDLE_TIMEOUT msecs_to_jiffies(1000) 62 63 enum amdgpu_gfx_partition { 64 AMDGPU_SPX_PARTITION_MODE = 0, 65 AMDGPU_DPX_PARTITION_MODE = 1, 66 AMDGPU_TPX_PARTITION_MODE = 2, 67 AMDGPU_QPX_PARTITION_MODE = 3, 68 AMDGPU_CPX_PARTITION_MODE = 4, 69 AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE = -1, 70 /* Automatically choose the right mode */ 71 AMDGPU_AUTO_COMPUTE_PARTITION_MODE = -2, 72 }; 73 74 #define NUM_XCC(x) hweight16(x) 75 76 enum amdgpu_gfx_ras_mem_id_type { 77 AMDGPU_GFX_CP_MEM = 0, 78 AMDGPU_GFX_GCEA_MEM, 79 AMDGPU_GFX_GC_CANE_MEM, 80 AMDGPU_GFX_GCUTCL2_MEM, 81 AMDGPU_GFX_GDS_MEM, 82 AMDGPU_GFX_LDS_MEM, 83 AMDGPU_GFX_RLC_MEM, 84 AMDGPU_GFX_SP_MEM, 85 AMDGPU_GFX_SPI_MEM, 86 AMDGPU_GFX_SQC_MEM, 87 AMDGPU_GFX_SQ_MEM, 88 AMDGPU_GFX_TA_MEM, 89 AMDGPU_GFX_TCC_MEM, 90 AMDGPU_GFX_TCA_MEM, 91 AMDGPU_GFX_TCI_MEM, 92 AMDGPU_GFX_TCP_MEM, 93 AMDGPU_GFX_TD_MEM, 94 AMDGPU_GFX_TCX_MEM, 95 AMDGPU_GFX_ATC_L2_MEM, 96 AMDGPU_GFX_UTCL2_MEM, 97 AMDGPU_GFX_VML2_MEM, 98 AMDGPU_GFX_VML2_WALKER_MEM, 99 AMDGPU_GFX_MEM_TYPE_NUM 100 }; 101 102 struct amdgpu_mec { 103 struct amdgpu_bo *hpd_eop_obj; 104 u64 hpd_eop_gpu_addr; 105 struct amdgpu_bo *mec_fw_obj; 106 u64 mec_fw_gpu_addr; 107 struct amdgpu_bo *mec_fw_data_obj; 108 u64 mec_fw_data_gpu_addr; 109 110 u32 num_mec; 111 u32 num_pipe_per_mec; 112 u32 num_queue_per_pipe; 113 void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS * AMDGPU_MAX_GC_INSTANCES]; 114 }; 115 116 struct amdgpu_mec_bitmap { 117 /* These are the resources for which amdgpu takes ownership */ 118 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 119 }; 120 121 enum amdgpu_unmap_queues_action { 122 PREEMPT_QUEUES = 0, 123 RESET_QUEUES, 124 DISABLE_PROCESS_QUEUES, 125 PREEMPT_QUEUES_NO_UNMAP, 126 }; 127 128 struct kiq_pm4_funcs { 129 /* Support ASIC-specific kiq pm4 packets*/ 130 void (*kiq_set_resources)(struct amdgpu_ring *kiq_ring, 131 uint64_t queue_mask); 132 void (*kiq_map_queues)(struct amdgpu_ring *kiq_ring, 133 struct amdgpu_ring *ring); 134 void (*kiq_unmap_queues)(struct amdgpu_ring *kiq_ring, 135 struct amdgpu_ring *ring, 136 enum amdgpu_unmap_queues_action action, 137 u64 gpu_addr, u64 seq); 138 void (*kiq_query_status)(struct amdgpu_ring *kiq_ring, 139 struct amdgpu_ring *ring, 140 u64 addr, 141 u64 seq); 142 void (*kiq_invalidate_tlbs)(struct amdgpu_ring *kiq_ring, 143 uint16_t pasid, uint32_t flush_type, 144 bool all_hub); 145 void (*kiq_reset_hw_queue)(struct amdgpu_ring *kiq_ring, 146 uint32_t queue_type, uint32_t me_id, 147 uint32_t pipe_id, uint32_t queue_id, 148 uint32_t xcc_id, uint32_t vmid); 149 /* Packet sizes */ 150 int set_resources_size; 151 int map_queues_size; 152 int unmap_queues_size; 153 int query_status_size; 154 int invalidate_tlbs_size; 155 }; 156 157 struct amdgpu_kiq { 158 u64 eop_gpu_addr; 159 struct amdgpu_bo *eop_obj; 160 spinlock_t ring_lock; 161 struct amdgpu_ring ring; 162 struct amdgpu_irq_src irq; 163 const struct kiq_pm4_funcs *pmf; 164 void *mqd_backup; 165 }; 166 167 /* 168 * GFX configurations 169 */ 170 #define AMDGPU_GFX_MAX_SE 4 171 #define AMDGPU_GFX_MAX_SH_PER_SE 2 172 173 struct amdgpu_rb_config { 174 uint32_t rb_backend_disable; 175 uint32_t user_rb_backend_disable; 176 uint32_t raster_config; 177 uint32_t raster_config_1; 178 }; 179 180 struct gb_addr_config { 181 uint16_t pipe_interleave_size; 182 uint8_t num_pipes; 183 uint8_t max_compress_frags; 184 uint8_t num_banks; 185 uint8_t num_se; 186 uint8_t num_rb_per_se; 187 uint8_t num_pkrs; 188 }; 189 190 struct amdgpu_gfx_config { 191 unsigned max_shader_engines; 192 unsigned max_tile_pipes; 193 unsigned max_cu_per_sh; 194 unsigned max_sh_per_se; 195 unsigned max_backends_per_se; 196 unsigned max_texture_channel_caches; 197 unsigned max_gprs; 198 unsigned max_gs_threads; 199 unsigned max_hw_contexts; 200 unsigned sc_prim_fifo_size_frontend; 201 unsigned sc_prim_fifo_size_backend; 202 unsigned sc_hiz_tile_fifo_size; 203 unsigned sc_earlyz_tile_fifo_size; 204 205 unsigned num_tile_pipes; 206 unsigned backend_enable_mask; 207 unsigned mem_max_burst_length_bytes; 208 unsigned mem_row_size_in_kb; 209 unsigned shader_engine_tile_size; 210 unsigned num_gpus; 211 unsigned multi_gpu_tile_size; 212 unsigned mc_arb_ramcfg; 213 unsigned num_banks; 214 unsigned num_ranks; 215 unsigned gb_addr_config; 216 unsigned num_rbs; 217 unsigned gs_vgt_table_depth; 218 unsigned gs_prim_buffer_depth; 219 220 uint32_t tile_mode_array[32]; 221 uint32_t macrotile_mode_array[16]; 222 223 struct gb_addr_config gb_addr_config_fields; 224 struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE]; 225 226 /* gfx configure feature */ 227 uint32_t double_offchip_lds_buf; 228 /* cached value of DB_DEBUG2 */ 229 uint32_t db_debug2; 230 /* gfx10 specific config */ 231 uint32_t num_sc_per_sh; 232 uint32_t num_packer_per_sc; 233 uint32_t pa_sc_tile_steering_override; 234 /* Whether texture coordinate truncation is conformant. */ 235 bool ta_cntl2_truncate_coord_mode; 236 uint64_t tcc_disabled_mask; 237 uint32_t gc_num_tcp_per_sa; 238 uint32_t gc_num_sdp_interface; 239 uint32_t gc_num_tcps; 240 uint32_t gc_num_tcp_per_wpg; 241 uint32_t gc_tcp_l1_size; 242 uint32_t gc_num_sqc_per_wgp; 243 uint32_t gc_l1_instruction_cache_size_per_sqc; 244 uint32_t gc_l1_data_cache_size_per_sqc; 245 uint32_t gc_gl1c_per_sa; 246 uint32_t gc_gl1c_size_per_instance; 247 uint32_t gc_gl2c_per_gpu; 248 uint32_t gc_tcp_size_per_cu; 249 uint32_t gc_num_cu_per_sqc; 250 uint32_t gc_tcc_size; 251 uint32_t gc_tcp_cache_line_size; 252 uint32_t gc_instruction_cache_size_per_sqc; 253 uint32_t gc_instruction_cache_line_size; 254 uint32_t gc_scalar_data_cache_size_per_sqc; 255 uint32_t gc_scalar_data_cache_line_size; 256 uint32_t gc_tcc_cache_line_size; 257 }; 258 259 struct amdgpu_cu_info { 260 uint32_t simd_per_cu; 261 uint32_t max_waves_per_simd; 262 uint32_t wave_front_size; 263 uint32_t max_scratch_slots_per_cu; 264 uint32_t lds_size; 265 266 /* total active CU number */ 267 uint32_t number; 268 uint32_t ao_cu_mask; 269 uint32_t ao_cu_bitmap[4][4]; 270 uint32_t bitmap[AMDGPU_MAX_GC_INSTANCES][4][4]; 271 }; 272 273 struct amdgpu_gfx_ras { 274 struct amdgpu_ras_block_object ras_block; 275 void (*enable_watchdog_timer)(struct amdgpu_device *adev); 276 int (*rlc_gc_fed_irq)(struct amdgpu_device *adev, 277 struct amdgpu_irq_src *source, 278 struct amdgpu_iv_entry *entry); 279 int (*poison_consumption_handler)(struct amdgpu_device *adev, 280 struct amdgpu_iv_entry *entry); 281 }; 282 283 struct amdgpu_gfx_shadow_info { 284 u32 shadow_size; 285 u32 shadow_alignment; 286 u32 csa_size; 287 u32 csa_alignment; 288 }; 289 290 struct amdgpu_gfx_funcs { 291 /* get the gpu clock counter */ 292 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev); 293 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, 294 u32 sh_num, u32 instance, int xcc_id); 295 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 296 uint32_t wave, uint32_t *dst, int *no_fields); 297 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 298 uint32_t wave, uint32_t thread, uint32_t start, 299 uint32_t size, uint32_t *dst); 300 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 301 uint32_t wave, uint32_t start, uint32_t size, 302 uint32_t *dst); 303 void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe, 304 u32 queue, u32 vmid, u32 xcc_id); 305 void (*init_spm_golden)(struct amdgpu_device *adev); 306 void (*update_perfmon_mgcg)(struct amdgpu_device *adev, bool enable); 307 int (*get_gfx_shadow_info)(struct amdgpu_device *adev, 308 struct amdgpu_gfx_shadow_info *shadow_info, 309 bool skip_check); 310 enum amdgpu_gfx_partition 311 (*query_partition_mode)(struct amdgpu_device *adev); 312 int (*switch_partition_mode)(struct amdgpu_device *adev, 313 int num_xccs_per_xcp); 314 int (*ih_node_to_logical_xcc)(struct amdgpu_device *adev, int ih_node); 315 int (*get_xccs_per_xcp)(struct amdgpu_device *adev); 316 }; 317 318 struct sq_work { 319 struct work_struct work; 320 unsigned ih_data; 321 }; 322 323 struct amdgpu_pfp { 324 struct amdgpu_bo *pfp_fw_obj; 325 uint64_t pfp_fw_gpu_addr; 326 uint32_t *pfp_fw_ptr; 327 328 struct amdgpu_bo *pfp_fw_data_obj; 329 uint64_t pfp_fw_data_gpu_addr; 330 uint32_t *pfp_fw_data_ptr; 331 }; 332 333 struct amdgpu_ce { 334 struct amdgpu_bo *ce_fw_obj; 335 uint64_t ce_fw_gpu_addr; 336 uint32_t *ce_fw_ptr; 337 }; 338 339 struct amdgpu_me { 340 struct amdgpu_bo *me_fw_obj; 341 uint64_t me_fw_gpu_addr; 342 uint32_t *me_fw_ptr; 343 344 struct amdgpu_bo *me_fw_data_obj; 345 uint64_t me_fw_data_gpu_addr; 346 uint32_t *me_fw_data_ptr; 347 348 uint32_t num_me; 349 uint32_t num_pipe_per_me; 350 uint32_t num_queue_per_pipe; 351 void *mqd_backup[AMDGPU_MAX_GFX_RINGS]; 352 353 /* These are the resources for which amdgpu takes ownership */ 354 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 355 }; 356 357 struct amdgpu_isolation_work { 358 struct amdgpu_device *adev; 359 u32 xcp_id; 360 struct delayed_work work; 361 }; 362 363 struct amdgpu_gfx { 364 struct mutex gpu_clock_mutex; 365 struct amdgpu_gfx_config config; 366 struct amdgpu_rlc rlc; 367 struct amdgpu_pfp pfp; 368 struct amdgpu_ce ce; 369 struct amdgpu_me me; 370 struct amdgpu_mec mec; 371 struct amdgpu_mec_bitmap mec_bitmap[AMDGPU_MAX_GC_INSTANCES]; 372 struct amdgpu_kiq kiq[AMDGPU_MAX_GC_INSTANCES]; 373 struct amdgpu_imu imu; 374 bool rs64_enable; /* firmware format */ 375 const struct firmware *me_fw; /* ME firmware */ 376 uint32_t me_fw_version; 377 const struct firmware *pfp_fw; /* PFP firmware */ 378 uint32_t pfp_fw_version; 379 const struct firmware *ce_fw; /* CE firmware */ 380 uint32_t ce_fw_version; 381 const struct firmware *rlc_fw; /* RLC firmware */ 382 uint32_t rlc_fw_version; 383 const struct firmware *mec_fw; /* MEC firmware */ 384 uint32_t mec_fw_version; 385 const struct firmware *mec2_fw; /* MEC2 firmware */ 386 uint32_t mec2_fw_version; 387 const struct firmware *imu_fw; /* IMU firmware */ 388 uint32_t imu_fw_version; 389 uint32_t me_feature_version; 390 uint32_t ce_feature_version; 391 uint32_t pfp_feature_version; 392 uint32_t rlc_feature_version; 393 uint32_t rlc_srlc_fw_version; 394 uint32_t rlc_srlc_feature_version; 395 uint32_t rlc_srlg_fw_version; 396 uint32_t rlc_srlg_feature_version; 397 uint32_t rlc_srls_fw_version; 398 uint32_t rlc_srls_feature_version; 399 uint32_t rlcp_ucode_version; 400 uint32_t rlcp_ucode_feature_version; 401 uint32_t rlcv_ucode_version; 402 uint32_t rlcv_ucode_feature_version; 403 uint32_t mec_feature_version; 404 uint32_t mec2_feature_version; 405 bool mec_fw_write_wait; 406 bool me_fw_write_wait; 407 bool cp_fw_write_wait; 408 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS]; 409 unsigned num_gfx_rings; 410 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS * AMDGPU_MAX_GC_INSTANCES]; 411 unsigned num_compute_rings; 412 struct amdgpu_irq_src eop_irq; 413 struct amdgpu_irq_src priv_reg_irq; 414 struct amdgpu_irq_src priv_inst_irq; 415 struct amdgpu_irq_src bad_op_irq; 416 struct amdgpu_irq_src cp_ecc_error_irq; 417 struct amdgpu_irq_src sq_irq; 418 struct amdgpu_irq_src rlc_gc_fed_irq; 419 struct sq_work sq_work; 420 421 /* gfx status */ 422 uint32_t gfx_current_status; 423 /* ce ram size*/ 424 unsigned ce_ram_size; 425 struct amdgpu_cu_info cu_info; 426 const struct amdgpu_gfx_funcs *funcs; 427 428 /* reset mask */ 429 uint32_t grbm_soft_reset; 430 uint32_t srbm_soft_reset; 431 uint32_t gfx_supported_reset; 432 uint32_t compute_supported_reset; 433 434 /* gfx off */ 435 bool gfx_off_state; /* true: enabled, false: disabled */ 436 struct mutex gfx_off_mutex; /* mutex to change gfxoff state */ 437 uint32_t gfx_off_req_count; /* default 1, enable gfx off: dec 1, disable gfx off: add 1 */ 438 struct delayed_work gfx_off_delay_work; /* async work to set gfx block off */ 439 uint32_t gfx_off_residency; /* last logged residency */ 440 uint64_t gfx_off_entrycount; /* count of times GPU has get into GFXOFF state */ 441 442 /* pipe reservation */ 443 struct mutex pipe_reserve_mutex; 444 DECLARE_BITMAP (pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 445 446 /*ras */ 447 struct ras_common_if *ras_if; 448 struct amdgpu_gfx_ras *ras; 449 450 bool is_poweron; 451 452 struct amdgpu_ring sw_gfx_ring[AMDGPU_MAX_SW_GFX_RINGS]; 453 struct amdgpu_ring_mux muxer; 454 455 bool cp_gfx_shadow; /* for gfx11 */ 456 457 uint16_t xcc_mask; 458 uint32_t num_xcc_per_xcp; 459 struct mutex partition_mutex; 460 bool mcbp; /* mid command buffer preemption */ 461 462 /* IP reg dump */ 463 uint32_t *ip_dump_core; 464 uint32_t *ip_dump_compute_queues; 465 uint32_t *ip_dump_gfx_queues; 466 467 struct mutex reset_sem_mutex; 468 469 /* cleaner shader */ 470 struct amdgpu_bo *cleaner_shader_obj; 471 unsigned int cleaner_shader_size; 472 u64 cleaner_shader_gpu_addr; 473 void *cleaner_shader_cpu_ptr; 474 const void *cleaner_shader_ptr; 475 bool enable_cleaner_shader; 476 struct amdgpu_isolation_work enforce_isolation[MAX_XCP]; 477 /* Mutex for synchronizing KFD scheduler operations */ 478 struct mutex userq_sch_mutex; 479 u64 userq_sch_req_count[MAX_XCP]; 480 bool userq_sch_inactive[MAX_XCP]; 481 unsigned long enforce_isolation_jiffies[MAX_XCP]; 482 unsigned long enforce_isolation_time[MAX_XCP]; 483 484 atomic_t total_submission_cnt; 485 struct delayed_work idle_work; 486 bool workload_profile_active; 487 struct mutex workload_profile_mutex; 488 489 bool disable_kq; 490 bool disable_uq; 491 }; 492 493 struct amdgpu_gfx_ras_reg_entry { 494 struct amdgpu_ras_err_status_reg_entry reg_entry; 495 enum amdgpu_gfx_ras_mem_id_type mem_id_type; 496 uint32_t se_num; 497 }; 498 499 struct amdgpu_gfx_ras_mem_id_entry { 500 const struct amdgpu_ras_memory_id_entry *mem_id_ent; 501 uint32_t size; 502 }; 503 504 #define AMDGPU_GFX_MEMID_ENT(x) {(x), ARRAY_SIZE(x)}, 505 506 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev)) 507 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance, xcc_id) ((adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance), (xcc_id))) 508 #define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid, xcc_id) ((adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q), (vmid), (xcc_id))) 509 #define amdgpu_gfx_init_spm_golden(adev) (adev)->gfx.funcs->init_spm_golden((adev)) 510 #define amdgpu_gfx_get_gfx_shadow_info(adev, si) ((adev)->gfx.funcs->get_gfx_shadow_info((adev), (si), false)) 511 512 /** 513 * amdgpu_gfx_create_bitmask - create a bitmask 514 * 515 * @bit_width: length of the mask 516 * 517 * create a variable length bit mask. 518 * Returns the bitmask. 519 */ 520 static inline u32 amdgpu_gfx_create_bitmask(u32 bit_width) 521 { 522 return (u32)((1ULL << bit_width) - 1); 523 } 524 525 void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se, 526 unsigned max_sh); 527 528 int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev, int xcc_id); 529 530 void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring); 531 532 void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev, int xcc_id); 533 int amdgpu_gfx_kiq_init(struct amdgpu_device *adev, 534 unsigned hpd_size, int xcc_id); 535 536 int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev, 537 unsigned mqd_size, int xcc_id); 538 void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev, int xcc_id); 539 int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev, int xcc_id); 540 int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev, int xcc_id); 541 int amdgpu_gfx_disable_kgq(struct amdgpu_device *adev, int xcc_id); 542 int amdgpu_gfx_enable_kgq(struct amdgpu_device *adev, int xcc_id); 543 544 void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev); 545 void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev); 546 547 int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec, 548 int pipe, int queue); 549 void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit, 550 int *mec, int *pipe, int *queue); 551 bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int xcc_id, 552 int mec, int pipe, int queue); 553 bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev, 554 struct amdgpu_ring *ring); 555 bool amdgpu_gfx_is_high_priority_graphics_queue(struct amdgpu_device *adev, 556 struct amdgpu_ring *ring); 557 bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me, 558 int pipe, int queue); 559 void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable); 560 void amdgpu_gfx_off_ctrl_immediate(struct amdgpu_device *adev, bool enable); 561 int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value); 562 int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block); 563 void amdgpu_gfx_ras_fini(struct amdgpu_device *adev); 564 int amdgpu_get_gfx_off_entrycount(struct amdgpu_device *adev, u64 *value); 565 int amdgpu_get_gfx_off_residency(struct amdgpu_device *adev, u32 *residency); 566 int amdgpu_set_gfx_off_residency(struct amdgpu_device *adev, bool value); 567 int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev, 568 void *err_data, 569 struct amdgpu_iv_entry *entry); 570 int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev, 571 struct amdgpu_irq_src *source, 572 struct amdgpu_iv_entry *entry); 573 uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg, uint32_t xcc_id); 574 void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, uint32_t xcc_id); 575 int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev); 576 void amdgpu_gfx_cp_init_microcode(struct amdgpu_device *adev, uint32_t ucode_id); 577 578 int amdgpu_gfx_ras_sw_init(struct amdgpu_device *adev); 579 int amdgpu_gfx_poison_consumption_handler(struct amdgpu_device *adev, 580 struct amdgpu_iv_entry *entry); 581 582 bool amdgpu_gfx_is_master_xcc(struct amdgpu_device *adev, int xcc_id); 583 int amdgpu_gfx_sysfs_init(struct amdgpu_device *adev); 584 void amdgpu_gfx_sysfs_fini(struct amdgpu_device *adev); 585 void amdgpu_gfx_ras_error_func(struct amdgpu_device *adev, 586 void *ras_error_status, 587 void (*func)(struct amdgpu_device *adev, void *ras_error_status, 588 int xcc_id)); 589 int amdgpu_gfx_cleaner_shader_sw_init(struct amdgpu_device *adev, 590 unsigned int cleaner_shader_size); 591 void amdgpu_gfx_cleaner_shader_sw_fini(struct amdgpu_device *adev); 592 void amdgpu_gfx_cleaner_shader_init(struct amdgpu_device *adev, 593 unsigned int cleaner_shader_size, 594 const void *cleaner_shader_ptr); 595 void amdgpu_gfx_enforce_isolation_handler(struct work_struct *work); 596 void amdgpu_gfx_enforce_isolation_ring_begin_use(struct amdgpu_ring *ring); 597 void amdgpu_gfx_enforce_isolation_ring_end_use(struct amdgpu_ring *ring); 598 599 void amdgpu_gfx_profile_idle_work_handler(struct work_struct *work); 600 void amdgpu_gfx_profile_ring_begin_use(struct amdgpu_ring *ring); 601 void amdgpu_gfx_profile_ring_end_use(struct amdgpu_ring *ring); 602 u32 amdgpu_gfx_csb_preamble_start(volatile u32 *buffer); 603 u32 amdgpu_gfx_csb_data_parser(struct amdgpu_device *adev, volatile u32 *buffer, u32 count); 604 void amdgpu_gfx_csb_preamble_end(volatile u32 *buffer, u32 count); 605 606 void amdgpu_debugfs_gfx_sched_mask_init(struct amdgpu_device *adev); 607 void amdgpu_debugfs_compute_sched_mask_init(struct amdgpu_device *adev); 608 609 static inline const char *amdgpu_gfx_compute_mode_desc(int mode) 610 { 611 switch (mode) { 612 case AMDGPU_SPX_PARTITION_MODE: 613 return "SPX"; 614 case AMDGPU_DPX_PARTITION_MODE: 615 return "DPX"; 616 case AMDGPU_TPX_PARTITION_MODE: 617 return "TPX"; 618 case AMDGPU_QPX_PARTITION_MODE: 619 return "QPX"; 620 case AMDGPU_CPX_PARTITION_MODE: 621 return "CPX"; 622 default: 623 return "UNKNOWN"; 624 } 625 } 626 627 #endif 628