1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_GFX_H__ 25 #define __AMDGPU_GFX_H__ 26 27 /* 28 * GFX stuff 29 */ 30 #include "clearstate_defs.h" 31 #include "amdgpu_ring.h" 32 #include "amdgpu_rlc.h" 33 #include "amdgpu_imu.h" 34 #include "soc15.h" 35 #include "amdgpu_ras.h" 36 #include "amdgpu_ring_mux.h" 37 #include "amdgpu_xcp.h" 38 39 struct amdgpu_usermode_queue; 40 41 /* GFX current status */ 42 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L 43 #define AMDGPU_GFX_SAFE_MODE 0x00000001L 44 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L 45 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L 46 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L 47 48 #define AMDGPU_MAX_GC_INSTANCES 8 49 #define AMDGPU_MAX_QUEUES 128 50 51 #define AMDGPU_MAX_GFX_QUEUES AMDGPU_MAX_QUEUES 52 #define AMDGPU_MAX_COMPUTE_QUEUES AMDGPU_MAX_QUEUES 53 54 enum amdgpu_gfx_pipe_priority { 55 AMDGPU_GFX_PIPE_PRIO_NORMAL = AMDGPU_RING_PRIO_1, 56 AMDGPU_GFX_PIPE_PRIO_HIGH = AMDGPU_RING_PRIO_2 57 }; 58 59 #define AMDGPU_GFX_QUEUE_PRIORITY_MINIMUM 0 60 #define AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM 15 61 62 /* 1 second timeout */ 63 #define GFX_PROFILE_IDLE_TIMEOUT msecs_to_jiffies(1000) 64 65 enum amdgpu_gfx_partition { 66 AMDGPU_SPX_PARTITION_MODE = 0, 67 AMDGPU_DPX_PARTITION_MODE = 1, 68 AMDGPU_TPX_PARTITION_MODE = 2, 69 AMDGPU_QPX_PARTITION_MODE = 3, 70 AMDGPU_CPX_PARTITION_MODE = 4, 71 AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE = -1, 72 /* Automatically choose the right mode */ 73 AMDGPU_AUTO_COMPUTE_PARTITION_MODE = -2, 74 }; 75 76 enum amdgpu_gfx_partition_mem_alloc_mode { 77 AMDGPU_PARTITION_MEM_CAPPING_EVEN = 0, 78 AMDGPU_PARTITION_MEM_ALLOC_ALL = 1, 79 }; 80 81 #define NUM_XCC(x) hweight16(x) 82 83 enum amdgpu_gfx_ras_mem_id_type { 84 AMDGPU_GFX_CP_MEM = 0, 85 AMDGPU_GFX_GCEA_MEM, 86 AMDGPU_GFX_GC_CANE_MEM, 87 AMDGPU_GFX_GCUTCL2_MEM, 88 AMDGPU_GFX_GDS_MEM, 89 AMDGPU_GFX_LDS_MEM, 90 AMDGPU_GFX_RLC_MEM, 91 AMDGPU_GFX_SP_MEM, 92 AMDGPU_GFX_SPI_MEM, 93 AMDGPU_GFX_SQC_MEM, 94 AMDGPU_GFX_SQ_MEM, 95 AMDGPU_GFX_TA_MEM, 96 AMDGPU_GFX_TCC_MEM, 97 AMDGPU_GFX_TCA_MEM, 98 AMDGPU_GFX_TCI_MEM, 99 AMDGPU_GFX_TCP_MEM, 100 AMDGPU_GFX_TD_MEM, 101 AMDGPU_GFX_TCX_MEM, 102 AMDGPU_GFX_ATC_L2_MEM, 103 AMDGPU_GFX_UTCL2_MEM, 104 AMDGPU_GFX_VML2_MEM, 105 AMDGPU_GFX_VML2_WALKER_MEM, 106 AMDGPU_GFX_MEM_TYPE_NUM 107 }; 108 109 struct amdgpu_mec { 110 struct amdgpu_bo *hpd_eop_obj; 111 u64 hpd_eop_gpu_addr; 112 struct amdgpu_bo *mec_fw_obj; 113 u64 mec_fw_gpu_addr; 114 struct amdgpu_bo *mec_fw_data_obj; 115 u64 mec_fw_data_gpu_addr; 116 117 u32 num_mec; 118 u32 num_pipe_per_mec; 119 u32 num_queue_per_pipe; 120 void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS * AMDGPU_MAX_GC_INSTANCES]; 121 bool use_mmio_for_reset; 122 u32 *mes_hung_db_array; 123 struct mutex reset_mutex; 124 }; 125 126 struct amdgpu_mec_bitmap { 127 /* These are the resources for which amdgpu takes ownership */ 128 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 129 }; 130 131 enum amdgpu_unmap_queues_action { 132 PREEMPT_QUEUES = 0, 133 RESET_QUEUES, 134 DISABLE_PROCESS_QUEUES, 135 PREEMPT_QUEUES_NO_UNMAP, 136 }; 137 138 struct kiq_pm4_funcs { 139 /* Support ASIC-specific kiq pm4 packets*/ 140 void (*kiq_set_resources)(struct amdgpu_ring *kiq_ring, 141 uint64_t queue_mask); 142 void (*kiq_map_queues)(struct amdgpu_ring *kiq_ring, 143 struct amdgpu_ring *ring); 144 void (*kiq_unmap_queues)(struct amdgpu_ring *kiq_ring, 145 struct amdgpu_ring *ring, 146 enum amdgpu_unmap_queues_action action, 147 u64 gpu_addr, u64 seq); 148 void (*kiq_query_status)(struct amdgpu_ring *kiq_ring, 149 struct amdgpu_ring *ring, 150 u64 addr, 151 u64 seq); 152 void (*kiq_invalidate_tlbs)(struct amdgpu_ring *kiq_ring, 153 uint16_t pasid, uint32_t flush_type, 154 bool all_hub); 155 void (*kiq_reset_hw_queue)(struct amdgpu_ring *kiq_ring, 156 uint32_t queue_type, uint32_t me_id, 157 uint32_t pipe_id, uint32_t queue_id, 158 uint32_t xcc_id, uint32_t vmid); 159 /* Packet sizes */ 160 int set_resources_size; 161 int map_queues_size; 162 int unmap_queues_size; 163 int query_status_size; 164 int invalidate_tlbs_size; 165 }; 166 167 struct amdgpu_kiq { 168 u64 eop_gpu_addr; 169 struct amdgpu_bo *eop_obj; 170 spinlock_t ring_lock; 171 struct amdgpu_ring ring; 172 struct amdgpu_irq_src irq; 173 const struct kiq_pm4_funcs *pmf; 174 void *mqd_backup; 175 }; 176 177 /* 178 * GFX configurations 179 */ 180 #define AMDGPU_GFX_MAX_SE 4 181 #define AMDGPU_GFX_MAX_SH_PER_SE 2 182 183 /** 184 * amdgpu_rb_config - Configure a single Render Backend (RB) 185 * 186 * Bad RBs are fused off and there is a harvest register the driver reads to 187 * determine which RB(s) are fused off so that the driver can configure the 188 * hardware state so that nothing gets sent to them. There are also user 189 * harvest registers that the driver can program to disable additional RBs, 190 * etc., for testing purposes. 191 */ 192 struct amdgpu_rb_config { 193 /** 194 * @rb_backend_disable: 195 * 196 * The value captured from register RB_BACKEND_DISABLE indicates if the 197 * RB backend is disabled or not. 198 */ 199 uint32_t rb_backend_disable; 200 201 /** 202 * @user_rb_backend_disable: 203 * 204 * The value captured from register USER_RB_BACKEND_DISABLE indicates 205 * if the User RB backend is disabled or not. 206 */ 207 uint32_t user_rb_backend_disable; 208 209 /** 210 * @raster_config: 211 * 212 * To set up all of the states, it is necessary to have two registers 213 * to keep all of the states. This field holds the first register. 214 */ 215 uint32_t raster_config; 216 217 /** 218 * @raster_config_1: 219 * 220 * To set up all of the states, it is necessary to have two registers 221 * to keep all of the states. This field holds the second register. 222 */ 223 uint32_t raster_config_1; 224 }; 225 226 struct gb_addr_config { 227 uint16_t pipe_interleave_size; 228 uint8_t num_pipes; 229 uint8_t max_compress_frags; 230 uint8_t num_banks; 231 uint8_t num_se; 232 uint8_t num_rb_per_se; 233 uint8_t num_pkrs; 234 }; 235 236 struct amdgpu_gfx_config { 237 unsigned max_shader_engines; 238 unsigned max_tile_pipes; 239 unsigned max_cu_per_sh; 240 unsigned max_sh_per_se; 241 unsigned max_backends_per_se; 242 unsigned max_texture_channel_caches; 243 unsigned max_gprs; 244 unsigned max_gs_threads; 245 unsigned max_hw_contexts; 246 unsigned sc_prim_fifo_size_frontend; 247 unsigned sc_prim_fifo_size_backend; 248 unsigned sc_hiz_tile_fifo_size; 249 unsigned sc_earlyz_tile_fifo_size; 250 251 unsigned num_tile_pipes; 252 unsigned backend_enable_mask; 253 unsigned mem_max_burst_length_bytes; 254 unsigned mem_row_size_in_kb; 255 unsigned shader_engine_tile_size; 256 unsigned num_gpus; 257 unsigned multi_gpu_tile_size; 258 unsigned mc_arb_ramcfg; 259 unsigned num_banks; 260 unsigned num_ranks; 261 unsigned gb_addr_config; 262 unsigned num_rbs; 263 unsigned gs_vgt_table_depth; 264 unsigned gs_prim_buffer_depth; 265 266 uint32_t tile_mode_array[32]; 267 uint32_t macrotile_mode_array[16]; 268 269 struct gb_addr_config gb_addr_config_fields; 270 271 /** 272 * @rb_config: 273 * 274 * Matrix that keeps all the Render Backend (color and depth buffer 275 * handling) configuration on the 3D engine. 276 */ 277 struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE]; 278 279 /* gfx configure feature */ 280 uint32_t double_offchip_lds_buf; 281 /* cached value of DB_DEBUG2 */ 282 uint32_t db_debug2; 283 /* gfx10 specific config */ 284 uint32_t num_sc_per_sh; 285 uint32_t num_packer_per_sc; 286 uint32_t pa_sc_tile_steering_override; 287 /* Whether texture coordinate truncation is conformant. */ 288 bool ta_cntl2_truncate_coord_mode; 289 uint64_t tcc_disabled_mask; 290 uint32_t gc_num_tcp_per_sa; 291 uint32_t gc_num_sdp_interface; 292 uint32_t gc_num_tcps; 293 uint32_t gc_num_tcp_per_wpg; 294 uint32_t gc_tcp_l1_size; 295 uint32_t gc_num_sqc_per_wgp; 296 uint32_t gc_l1_instruction_cache_size_per_sqc; 297 uint32_t gc_l1_data_cache_size_per_sqc; 298 uint32_t gc_gl1c_per_sa; 299 uint32_t gc_gl1c_size_per_instance; 300 uint32_t gc_gl2c_per_gpu; 301 uint32_t gc_tcp_size_per_cu; 302 uint32_t gc_num_cu_per_sqc; 303 uint32_t gc_tcc_size; 304 uint32_t gc_tcp_cache_line_size; 305 uint32_t gc_instruction_cache_size_per_sqc; 306 uint32_t gc_instruction_cache_line_size; 307 uint32_t gc_scalar_data_cache_size_per_sqc; 308 uint32_t gc_scalar_data_cache_line_size; 309 uint32_t gc_tcc_cache_line_size; 310 uint32_t gc_max_num_residency_ways; 311 uint32_t gc_cache_ways_size_in_bytes; 312 uint32_t gc_reserved; 313 }; 314 315 struct amdgpu_cu_info { 316 uint32_t simd_per_cu; 317 uint32_t max_waves_per_simd; 318 uint32_t wave_front_size; 319 uint32_t max_scratch_slots_per_cu; 320 uint32_t lds_size; 321 322 /* total active CU number */ 323 uint32_t number; 324 uint32_t ao_cu_mask; 325 uint32_t ao_cu_bitmap[4][4]; 326 uint32_t bitmap[AMDGPU_MAX_GC_INSTANCES][4][4]; 327 }; 328 329 struct amdgpu_gfx_ras { 330 struct amdgpu_ras_block_object ras_block; 331 void (*enable_watchdog_timer)(struct amdgpu_device *adev); 332 int (*rlc_gc_fed_irq)(struct amdgpu_device *adev, 333 struct amdgpu_irq_src *source, 334 struct amdgpu_iv_entry *entry); 335 int (*poison_consumption_handler)(struct amdgpu_device *adev, 336 struct amdgpu_iv_entry *entry); 337 }; 338 339 struct amdgpu_gfx_shadow_info { 340 u32 shadow_size; 341 u32 shadow_alignment; 342 u32 csa_size; 343 u32 csa_alignment; 344 u32 eop_size; 345 u32 eop_alignment; 346 }; 347 348 struct amdgpu_gfx_funcs { 349 /* get the gpu clock counter */ 350 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev); 351 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, 352 u32 sh_num, u32 instance, int xcc_id); 353 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 354 uint32_t wave, uint32_t *dst, int *no_fields); 355 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 356 uint32_t wave, uint32_t thread, uint32_t start, 357 uint32_t size, uint32_t *dst); 358 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 359 uint32_t wave, uint32_t start, uint32_t size, 360 uint32_t *dst); 361 void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe, 362 u32 queue, u32 vmid, u32 xcc_id); 363 void (*init_spm_golden)(struct amdgpu_device *adev); 364 void (*update_perfmon_mgcg)(struct amdgpu_device *adev, bool enable); 365 int (*get_gfx_shadow_info)(struct amdgpu_device *adev, 366 struct amdgpu_gfx_shadow_info *shadow_info, 367 bool skip_check); 368 enum amdgpu_gfx_partition 369 (*query_partition_mode)(struct amdgpu_device *adev); 370 int (*switch_partition_mode)(struct amdgpu_device *adev, 371 int num_xccs_per_xcp); 372 int (*ih_node_to_logical_xcc)(struct amdgpu_device *adev, int ih_node); 373 int (*get_xccs_per_xcp)(struct amdgpu_device *adev); 374 void (*get_hdp_flush_mask)(struct amdgpu_ring *ring, 375 uint32_t *ref_and_mask, uint32_t *reg_mem_engine); 376 /* find the gfx HQD slot (me/pipe/queue) for a doorbell */ 377 bool (*detect_hung_queue)(struct amdgpu_device *adev, u32 doorbell_index, 378 u32 *me, u32 *pipe, u32 *queue); 379 }; 380 381 struct sq_work { 382 struct work_struct work; 383 unsigned ih_data; 384 }; 385 386 struct amdgpu_pfp { 387 struct amdgpu_bo *pfp_fw_obj; 388 uint64_t pfp_fw_gpu_addr; 389 uint32_t *pfp_fw_ptr; 390 391 struct amdgpu_bo *pfp_fw_data_obj; 392 uint64_t pfp_fw_data_gpu_addr; 393 uint32_t *pfp_fw_data_ptr; 394 }; 395 396 struct amdgpu_ce { 397 struct amdgpu_bo *ce_fw_obj; 398 uint64_t ce_fw_gpu_addr; 399 uint32_t *ce_fw_ptr; 400 }; 401 402 struct amdgpu_me { 403 struct amdgpu_bo *me_fw_obj; 404 uint64_t me_fw_gpu_addr; 405 uint32_t *me_fw_ptr; 406 407 struct amdgpu_bo *me_fw_data_obj; 408 uint64_t me_fw_data_gpu_addr; 409 uint32_t *me_fw_data_ptr; 410 411 uint32_t num_me; 412 uint32_t num_pipe_per_me; 413 uint32_t num_queue_per_pipe; 414 void *mqd_backup[AMDGPU_MAX_GFX_RINGS]; 415 bool use_mmio_for_reset; 416 417 /* These are the resources for which amdgpu takes ownership */ 418 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 419 }; 420 421 struct amdgpu_isolation_work { 422 struct amdgpu_device *adev; 423 u32 xcp_id; 424 struct delayed_work work; 425 }; 426 427 struct amdgpu_gfx { 428 struct mutex gpu_clock_mutex; 429 struct amdgpu_gfx_config config; 430 struct amdgpu_rlc rlc; 431 struct amdgpu_pfp pfp; 432 struct amdgpu_ce ce; 433 struct amdgpu_me me; 434 struct amdgpu_mec mec; 435 struct amdgpu_mec_bitmap mec_bitmap[AMDGPU_MAX_GC_INSTANCES]; 436 struct amdgpu_kiq kiq[AMDGPU_MAX_GC_INSTANCES]; 437 struct amdgpu_imu imu; 438 bool rs64_enable; /* firmware format */ 439 const struct firmware *me_fw; /* ME firmware */ 440 uint32_t me_fw_version; 441 const struct firmware *pfp_fw; /* PFP firmware */ 442 uint32_t pfp_fw_version; 443 const struct firmware *ce_fw; /* CE firmware */ 444 uint32_t ce_fw_version; 445 const struct firmware *rlc_fw; /* RLC firmware */ 446 uint32_t rlc_fw_version; 447 const struct firmware *mec_fw; /* MEC firmware */ 448 uint32_t mec_fw_version; 449 const struct firmware *mec2_fw; /* MEC2 firmware */ 450 uint32_t mec2_fw_version; 451 const struct firmware *imu_fw; /* IMU firmware */ 452 uint32_t imu_fw_version; 453 uint32_t me_feature_version; 454 uint32_t ce_feature_version; 455 uint32_t pfp_feature_version; 456 uint32_t rlc_feature_version; 457 uint32_t rlc_srlc_fw_version; 458 uint32_t rlc_srlc_feature_version; 459 uint32_t rlc_srlg_fw_version; 460 uint32_t rlc_srlg_feature_version; 461 uint32_t rlc_srls_fw_version; 462 uint32_t rlc_srls_feature_version; 463 uint32_t rlcp_ucode_version; 464 uint32_t rlcp_ucode_feature_version; 465 uint32_t rlcv_ucode_version; 466 uint32_t rlcv_ucode_feature_version; 467 uint32_t mec_feature_version; 468 uint32_t mec2_feature_version; 469 bool mec_fw_write_wait; 470 bool me_fw_write_wait; 471 bool cp_fw_write_wait; 472 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS]; 473 unsigned num_gfx_rings; 474 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS * AMDGPU_MAX_GC_INSTANCES]; 475 unsigned num_compute_rings; 476 struct amdgpu_irq_src eop_irq; 477 struct amdgpu_irq_src priv_reg_irq; 478 struct amdgpu_irq_src priv_inst_irq; 479 struct amdgpu_irq_src bad_op_irq; 480 struct amdgpu_irq_src cp_ecc_error_irq; 481 struct amdgpu_irq_src sq_irq; 482 struct amdgpu_irq_src rlc_gc_fed_irq; 483 struct amdgpu_irq_src rlc_poison_irq; 484 struct amdgpu_irq_src pmr_ea_irq; 485 struct sq_work sq_work; 486 487 /* gfx status */ 488 uint32_t gfx_current_status; 489 /* ce ram size*/ 490 unsigned ce_ram_size; 491 struct amdgpu_cu_info cu_info; 492 const struct amdgpu_gfx_funcs *funcs; 493 494 /* reset mask */ 495 uint32_t gfx_supported_reset; 496 uint32_t compute_supported_reset; 497 498 /* gfx off */ 499 bool gfx_off_state; /* true: enabled, false: disabled */ 500 struct mutex gfx_off_mutex; /* mutex to change gfxoff state */ 501 uint32_t gfx_off_req_count; /* default 1, enable gfx off: dec 1, disable gfx off: add 1 */ 502 struct delayed_work gfx_off_delay_work; /* async work to set gfx block off */ 503 uint32_t gfx_off_residency; /* last logged residency */ 504 uint64_t gfx_off_entrycount; /* count of times GPU has get into GFXOFF state */ 505 506 /* pipe reservation */ 507 struct mutex pipe_reserve_mutex; 508 DECLARE_BITMAP (pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 509 510 /*ras */ 511 struct ras_common_if *ras_if; 512 struct amdgpu_gfx_ras *ras; 513 514 bool is_poweron; 515 516 struct amdgpu_ring sw_gfx_ring[AMDGPU_MAX_SW_GFX_RINGS]; 517 struct amdgpu_ring_mux muxer; 518 519 bool cp_gfx_shadow; /* for gfx11 */ 520 521 uint16_t xcc_mask; 522 uint32_t num_xcc_per_xcp; 523 struct mutex partition_mutex; 524 bool mcbp; /* mid command buffer preemption */ 525 526 /* IP reg dump */ 527 uint32_t *ip_dump_core; 528 uint32_t *ip_dump_compute_queues; 529 uint32_t *ip_dump_gfx_queues; 530 531 struct mutex reset_sem_mutex; 532 533 /* cleaner shader */ 534 struct amdgpu_bo *cleaner_shader_obj; 535 unsigned int cleaner_shader_size; 536 u64 cleaner_shader_gpu_addr; 537 void *cleaner_shader_cpu_ptr; 538 const void *cleaner_shader_ptr; 539 bool enable_cleaner_shader; 540 struct amdgpu_isolation_work enforce_isolation[MAX_XCP]; 541 /* Mutex for synchronizing KFD scheduler operations */ 542 struct mutex userq_sch_mutex; 543 u64 userq_sch_req_count[MAX_XCP]; 544 bool userq_sch_inactive[MAX_XCP]; 545 /* atomic bitmap of faulted gfx UQ slots (index = pipe | queue << 2) */ 546 unsigned long userq_priv_fault_slots; 547 struct work_struct userq_priv_fault_work; 548 unsigned long enforce_isolation_jiffies[MAX_XCP]; 549 unsigned long enforce_isolation_time[MAX_XCP]; 550 551 atomic_t total_submission_cnt; 552 struct delayed_work idle_work; 553 bool workload_profile_active; 554 struct mutex workload_profile_mutex; 555 556 bool disable_kq; 557 bool disable_uq; 558 }; 559 560 struct amdgpu_gfx_deferred_entry { 561 struct amdgpu_ring *ring; 562 struct amdgpu_fence *fence; 563 }; 564 565 struct amdgpu_gfx_ras_reg_entry { 566 struct amdgpu_ras_err_status_reg_entry reg_entry; 567 enum amdgpu_gfx_ras_mem_id_type mem_id_type; 568 uint32_t se_num; 569 }; 570 571 struct amdgpu_gfx_ras_mem_id_entry { 572 const struct amdgpu_ras_memory_id_entry *mem_id_ent; 573 uint32_t size; 574 }; 575 576 #define AMDGPU_GFX_MEMID_ENT(x) {(x), ARRAY_SIZE(x)}, 577 578 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev)) 579 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance, xcc_id) ((adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance), (xcc_id))) 580 #define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid, xcc_id) ((adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q), (vmid), (xcc_id))) 581 #define amdgpu_gfx_init_spm_golden(adev) (adev)->gfx.funcs->init_spm_golden((adev)) 582 #define amdgpu_gfx_get_gfx_shadow_info(adev, si) ((adev)->gfx.funcs->get_gfx_shadow_info((adev), (si), false)) 583 584 /** 585 * amdgpu_gfx_create_bitmask - create a bitmask 586 * 587 * @bit_width: length of the mask 588 * 589 * create a variable length bit mask. 590 * Returns the bitmask. 591 */ 592 static inline u32 amdgpu_gfx_create_bitmask(u32 bit_width) 593 { 594 return (u32)((1ULL << bit_width) - 1); 595 } 596 597 void amdgpu_gfx_parse_disable_cu(struct amdgpu_device *adev, unsigned int *mask, 598 unsigned int max_se, unsigned int max_sh); 599 600 int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev, int xcc_id); 601 602 void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring); 603 604 void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev, int xcc_id); 605 int amdgpu_gfx_kiq_init(struct amdgpu_device *adev, 606 unsigned hpd_size, int xcc_id); 607 608 int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev, 609 unsigned mqd_size, int xcc_id); 610 void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev, int xcc_id); 611 void amdgpu_gfx_mqd_symmetrically_map_cu_mask(struct amdgpu_device *adev, const uint32_t *cu_mask, 612 uint32_t cu_mask_count, uint32_t *se_mask); 613 int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev, int xcc_id); 614 int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev, int xcc_id); 615 int amdgpu_gfx_disable_kgq(struct amdgpu_device *adev, int xcc_id); 616 int amdgpu_gfx_enable_kgq(struct amdgpu_device *adev, int xcc_id); 617 618 void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev); 619 void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev); 620 621 int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec, 622 int pipe, int queue); 623 void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit, 624 int *mec, int *pipe, int *queue); 625 bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int xcc_id, 626 int mec, int pipe, int queue); 627 bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev, 628 struct amdgpu_ring *ring); 629 bool amdgpu_gfx_is_high_priority_graphics_queue(struct amdgpu_device *adev, 630 struct amdgpu_ring *ring); 631 bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me, 632 int pipe, int queue); 633 void amdgpu_gfx_handle_priv_fault(struct amdgpu_device *adev, 634 struct amdgpu_iv_entry *entry, 635 u8 me_id, u8 pipe_id, u8 queue_id); 636 void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable); 637 void amdgpu_gfx_off_ctrl_immediate(struct amdgpu_device *adev, bool enable); 638 int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value); 639 int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block); 640 void amdgpu_gfx_ras_suspend(struct amdgpu_device *adev, struct ras_common_if *ras_block); 641 void amdgpu_gfx_ras_fini(struct amdgpu_device *adev, struct ras_common_if *ras_block); 642 int amdgpu_get_gfx_off_entrycount(struct amdgpu_device *adev, u64 *value); 643 int amdgpu_get_gfx_off_residency(struct amdgpu_device *adev, u32 *residency); 644 int amdgpu_set_gfx_off_residency(struct amdgpu_device *adev, bool value); 645 int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev, 646 void *err_data, 647 struct amdgpu_iv_entry *entry); 648 int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev, 649 struct amdgpu_irq_src *source, 650 struct amdgpu_iv_entry *entry); 651 uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg, uint32_t xcc_id); 652 void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, uint32_t xcc_id); 653 void amdgpu_gfx_get_hdp_flush_mask(struct amdgpu_ring *ring, 654 uint32_t *ref_and_mask, uint32_t *reg_mem_engine); 655 int amdgpu_kiq_hdp_flush(struct amdgpu_device *adev); 656 int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev); 657 void amdgpu_gfx_cp_init_microcode(struct amdgpu_device *adev, uint32_t ucode_id); 658 659 int amdgpu_gfx_ras_sw_init(struct amdgpu_device *adev); 660 int amdgpu_gfx_poison_consumption_handler(struct amdgpu_device *adev, 661 struct amdgpu_iv_entry *entry); 662 663 bool amdgpu_gfx_is_master_xcc(struct amdgpu_device *adev, int xcc_id); 664 int amdgpu_gfx_sysfs_init(struct amdgpu_device *adev); 665 void amdgpu_gfx_sysfs_fini(struct amdgpu_device *adev); 666 int amdgpu_gfx_reset_mes_compute(struct amdgpu_device *adev, 667 struct amdgpu_ring *ring, 668 struct amdgpu_fence *guilty_fence, 669 struct amdgpu_usermode_queue *uq, 670 unsigned int *hung_queue_count, 671 void *faulty_queue_input); 672 void amdgpu_gfx_ras_error_func(struct amdgpu_device *adev, 673 void *ras_error_status, 674 void (*func)(struct amdgpu_device *adev, void *ras_error_status, 675 int xcc_id)); 676 int amdgpu_gfx_cleaner_shader_sw_init(struct amdgpu_device *adev, 677 unsigned int cleaner_shader_size); 678 void amdgpu_gfx_cleaner_shader_sw_fini(struct amdgpu_device *adev); 679 void amdgpu_gfx_cleaner_shader_init(struct amdgpu_device *adev, 680 unsigned int cleaner_shader_size, 681 const void *cleaner_shader_ptr); 682 void amdgpu_gfx_enforce_isolation_handler(struct work_struct *work); 683 void amdgpu_gfx_enforce_isolation_ring_begin_use(struct amdgpu_ring *ring); 684 void amdgpu_gfx_enforce_isolation_ring_end_use(struct amdgpu_ring *ring); 685 686 void amdgpu_gfx_profile_idle_work_handler(struct work_struct *work); 687 void amdgpu_gfx_profile_ring_begin_use(struct amdgpu_ring *ring); 688 void amdgpu_gfx_profile_ring_end_use(struct amdgpu_ring *ring); 689 u32 amdgpu_gfx_csb_preamble_start(u32 *buffer); 690 u32 amdgpu_gfx_csb_data_parser(struct amdgpu_device *adev, u32 *buffer, u32 count); 691 void amdgpu_gfx_csb_preamble_end(u32 *buffer, u32 count); 692 693 void amdgpu_debugfs_gfx_sched_mask_init(struct amdgpu_device *adev); 694 void amdgpu_debugfs_compute_sched_mask_init(struct amdgpu_device *adev); 695 696 int amdgpu_gfx_ring_preempt_ib(struct amdgpu_ring *ring); 697 698 int amdgpu_gfx_mes_reset_queue(struct amdgpu_ring *ring, 699 unsigned int vmid, 700 struct amdgpu_fence *timedout_fence, 701 bool use_mmio); 702 void amdgpu_gfx_mqd_reset_restore(struct amdgpu_ring *ring); 703 struct amdgpu_gfx_pipe_reset_ctx { 704 /* Schedulers stopped by this reset. */ 705 unsigned long sched_mask; 706 /* Rings with backed-up commands. */ 707 unsigned long replay_mask; 708 }; 709 710 bool amdgpu_gfx_me_pipe_reset_supported(struct amdgpu_device *adev); 711 void amdgpu_gfx_pipe_reset_prepare(struct amdgpu_device *adev, 712 struct amdgpu_ring *guilty_ring, 713 u32 me, u32 pipe, 714 struct amdgpu_gfx_pipe_reset_ctx *ctx); 715 int amdgpu_gfx_reset_mes_gfx(struct amdgpu_device *adev, 716 struct amdgpu_ring *ring, 717 struct amdgpu_fence *guilty_fence, 718 struct amdgpu_usermode_queue *queue, 719 unsigned int vmid, bool use_mmio); 720 721 static inline const char *amdgpu_gfx_compute_mode_desc(int mode) 722 { 723 switch (mode) { 724 case AMDGPU_SPX_PARTITION_MODE: 725 return "SPX"; 726 case AMDGPU_DPX_PARTITION_MODE: 727 return "DPX"; 728 case AMDGPU_TPX_PARTITION_MODE: 729 return "TPX"; 730 case AMDGPU_QPX_PARTITION_MODE: 731 return "QPX"; 732 case AMDGPU_CPX_PARTITION_MODE: 733 return "CPX"; 734 default: 735 return "UNKNOWN"; 736 } 737 } 738 739 static inline const char *amdgpu_gfx_compute_mem_alloc_mode_desc(int mode) 740 { 741 switch (mode) { 742 case AMDGPU_PARTITION_MEM_CAPPING_EVEN: 743 return "CAPPING"; 744 case AMDGPU_PARTITION_MEM_ALLOC_ALL: 745 return "ALL"; 746 default: 747 return "UNKNOWN"; 748 } 749 } 750 751 #endif 752