1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_GFX_H__ 25 #define __AMDGPU_GFX_H__ 26 27 /* 28 * GFX stuff 29 */ 30 #include "clearstate_defs.h" 31 #include "amdgpu_ring.h" 32 #include "amdgpu_rlc.h" 33 #include "amdgpu_imu.h" 34 #include "soc15.h" 35 #include "amdgpu_ras.h" 36 #include "amdgpu_ring_mux.h" 37 #include "amdgpu_xcp.h" 38 39 struct amdgpu_usermode_queue; 40 41 /* GFX current status */ 42 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L 43 #define AMDGPU_GFX_SAFE_MODE 0x00000001L 44 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L 45 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L 46 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L 47 48 #define AMDGPU_MAX_GC_INSTANCES 8 49 #define AMDGPU_MAX_QUEUES 128 50 51 #define AMDGPU_MAX_GFX_QUEUES AMDGPU_MAX_QUEUES 52 #define AMDGPU_MAX_COMPUTE_QUEUES AMDGPU_MAX_QUEUES 53 54 enum amdgpu_gfx_pipe_priority { 55 AMDGPU_GFX_PIPE_PRIO_NORMAL = AMDGPU_RING_PRIO_1, 56 AMDGPU_GFX_PIPE_PRIO_HIGH = AMDGPU_RING_PRIO_2 57 }; 58 59 #define AMDGPU_GFX_QUEUE_PRIORITY_MINIMUM 0 60 #define AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM 15 61 62 /* 1 second timeout */ 63 #define GFX_PROFILE_IDLE_TIMEOUT msecs_to_jiffies(1000) 64 65 enum amdgpu_gfx_partition { 66 AMDGPU_SPX_PARTITION_MODE = 0, 67 AMDGPU_DPX_PARTITION_MODE = 1, 68 AMDGPU_TPX_PARTITION_MODE = 2, 69 AMDGPU_QPX_PARTITION_MODE = 3, 70 AMDGPU_CPX_PARTITION_MODE = 4, 71 AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE = -1, 72 /* Automatically choose the right mode */ 73 AMDGPU_AUTO_COMPUTE_PARTITION_MODE = -2, 74 }; 75 76 enum amdgpu_gfx_partition_mem_alloc_mode { 77 AMDGPU_PARTITION_MEM_CAPPING_EVEN = 0, 78 AMDGPU_PARTITION_MEM_ALLOC_ALL = 1, 79 }; 80 81 #define NUM_XCC(x) hweight16(x) 82 83 enum amdgpu_gfx_ras_mem_id_type { 84 AMDGPU_GFX_CP_MEM = 0, 85 AMDGPU_GFX_GCEA_MEM, 86 AMDGPU_GFX_GC_CANE_MEM, 87 AMDGPU_GFX_GCUTCL2_MEM, 88 AMDGPU_GFX_GDS_MEM, 89 AMDGPU_GFX_LDS_MEM, 90 AMDGPU_GFX_RLC_MEM, 91 AMDGPU_GFX_SP_MEM, 92 AMDGPU_GFX_SPI_MEM, 93 AMDGPU_GFX_SQC_MEM, 94 AMDGPU_GFX_SQ_MEM, 95 AMDGPU_GFX_TA_MEM, 96 AMDGPU_GFX_TCC_MEM, 97 AMDGPU_GFX_TCA_MEM, 98 AMDGPU_GFX_TCI_MEM, 99 AMDGPU_GFX_TCP_MEM, 100 AMDGPU_GFX_TD_MEM, 101 AMDGPU_GFX_TCX_MEM, 102 AMDGPU_GFX_ATC_L2_MEM, 103 AMDGPU_GFX_UTCL2_MEM, 104 AMDGPU_GFX_VML2_MEM, 105 AMDGPU_GFX_VML2_WALKER_MEM, 106 AMDGPU_GFX_MEM_TYPE_NUM 107 }; 108 109 struct amdgpu_mec { 110 struct amdgpu_bo *hpd_eop_obj; 111 u64 hpd_eop_gpu_addr; 112 struct amdgpu_bo *mec_fw_obj; 113 u64 mec_fw_gpu_addr; 114 struct amdgpu_bo *mec_fw_data_obj; 115 u64 mec_fw_data_gpu_addr; 116 117 u32 num_mec; 118 u32 num_pipe_per_mec; 119 u32 num_queue_per_pipe; 120 void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS * AMDGPU_MAX_GC_INSTANCES]; 121 bool use_mmio_for_reset; 122 u32 *mes_hung_db_array; 123 struct mutex reset_mutex; 124 }; 125 126 struct amdgpu_mec_bitmap { 127 /* These are the resources for which amdgpu takes ownership */ 128 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 129 }; 130 131 enum amdgpu_unmap_queues_action { 132 PREEMPT_QUEUES = 0, 133 RESET_QUEUES, 134 DISABLE_PROCESS_QUEUES, 135 PREEMPT_QUEUES_NO_UNMAP, 136 }; 137 138 struct kiq_pm4_funcs { 139 /* Support ASIC-specific kiq pm4 packets*/ 140 void (*kiq_set_resources)(struct amdgpu_ring *kiq_ring, 141 uint64_t queue_mask); 142 void (*kiq_map_queues)(struct amdgpu_ring *kiq_ring, 143 struct amdgpu_ring *ring); 144 void (*kiq_unmap_queues)(struct amdgpu_ring *kiq_ring, 145 struct amdgpu_ring *ring, 146 enum amdgpu_unmap_queues_action action, 147 u64 gpu_addr, u64 seq); 148 void (*kiq_query_status)(struct amdgpu_ring *kiq_ring, 149 struct amdgpu_ring *ring, 150 u64 addr, 151 u64 seq); 152 void (*kiq_invalidate_tlbs)(struct amdgpu_ring *kiq_ring, 153 uint16_t pasid, uint32_t flush_type, 154 bool all_hub); 155 void (*kiq_reset_hw_queue)(struct amdgpu_ring *kiq_ring, 156 uint32_t queue_type, uint32_t me_id, 157 uint32_t pipe_id, uint32_t queue_id, 158 uint32_t xcc_id, uint32_t vmid); 159 /* Packet sizes */ 160 int set_resources_size; 161 int map_queues_size; 162 int unmap_queues_size; 163 int query_status_size; 164 int invalidate_tlbs_size; 165 }; 166 167 struct amdgpu_kiq { 168 u64 eop_gpu_addr; 169 struct amdgpu_bo *eop_obj; 170 spinlock_t ring_lock; 171 struct amdgpu_ring ring; 172 struct amdgpu_irq_src irq; 173 const struct kiq_pm4_funcs *pmf; 174 void *mqd_backup; 175 }; 176 177 /* 178 * GFX configurations 179 */ 180 #define AMDGPU_GFX_MAX_SE 4 181 #define AMDGPU_GFX_MAX_SH_PER_SE 2 182 183 /** 184 * amdgpu_rb_config - Configure a single Render Backend (RB) 185 * 186 * Bad RBs are fused off and there is a harvest register the driver reads to 187 * determine which RB(s) are fused off so that the driver can configure the 188 * hardware state so that nothing gets sent to them. There are also user 189 * harvest registers that the driver can program to disable additional RBs, 190 * etc., for testing purposes. 191 */ 192 struct amdgpu_rb_config { 193 /** 194 * @rb_backend_disable: 195 * 196 * The value captured from register RB_BACKEND_DISABLE indicates if the 197 * RB backend is disabled or not. 198 */ 199 uint32_t rb_backend_disable; 200 201 /** 202 * @user_rb_backend_disable: 203 * 204 * The value captured from register USER_RB_BACKEND_DISABLE indicates 205 * if the User RB backend is disabled or not. 206 */ 207 uint32_t user_rb_backend_disable; 208 209 /** 210 * @raster_config: 211 * 212 * To set up all of the states, it is necessary to have two registers 213 * to keep all of the states. This field holds the first register. 214 */ 215 uint32_t raster_config; 216 217 /** 218 * @raster_config_1: 219 * 220 * To set up all of the states, it is necessary to have two registers 221 * to keep all of the states. This field holds the second register. 222 */ 223 uint32_t raster_config_1; 224 }; 225 226 struct gb_addr_config { 227 uint16_t pipe_interleave_size; 228 uint8_t num_pipes; 229 uint8_t max_compress_frags; 230 uint8_t num_banks; 231 uint8_t num_se; 232 uint8_t num_rb_per_se; 233 uint8_t num_pkrs; 234 }; 235 236 struct amdgpu_gfx_config { 237 unsigned max_shader_engines; 238 unsigned max_tile_pipes; 239 unsigned max_cu_per_sh; 240 unsigned max_sh_per_se; 241 unsigned max_backends_per_se; 242 unsigned max_texture_channel_caches; 243 unsigned max_gprs; 244 unsigned max_gs_threads; 245 unsigned max_hw_contexts; 246 unsigned sc_prim_fifo_size_frontend; 247 unsigned sc_prim_fifo_size_backend; 248 unsigned sc_hiz_tile_fifo_size; 249 unsigned sc_earlyz_tile_fifo_size; 250 251 unsigned num_tile_pipes; 252 unsigned backend_enable_mask; 253 unsigned mem_max_burst_length_bytes; 254 unsigned mem_row_size_in_kb; 255 unsigned shader_engine_tile_size; 256 unsigned num_gpus; 257 unsigned multi_gpu_tile_size; 258 unsigned mc_arb_ramcfg; 259 unsigned num_banks; 260 unsigned num_ranks; 261 unsigned gb_addr_config; 262 unsigned num_rbs; 263 unsigned gs_vgt_table_depth; 264 unsigned gs_prim_buffer_depth; 265 266 uint32_t tile_mode_array[32]; 267 uint32_t macrotile_mode_array[16]; 268 269 struct gb_addr_config gb_addr_config_fields; 270 271 /** 272 * @rb_config: 273 * 274 * Matrix that keeps all the Render Backend (color and depth buffer 275 * handling) configuration on the 3D engine. 276 */ 277 struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE]; 278 279 /* gfx configure feature */ 280 uint32_t double_offchip_lds_buf; 281 /* cached value of DB_DEBUG2 */ 282 uint32_t db_debug2; 283 /* gfx10 specific config */ 284 uint32_t num_sc_per_sh; 285 uint32_t num_packer_per_sc; 286 uint32_t pa_sc_tile_steering_override; 287 /* Whether texture coordinate truncation is conformant. */ 288 bool ta_cntl2_truncate_coord_mode; 289 uint64_t tcc_disabled_mask; 290 uint32_t gc_num_tcp_per_sa; 291 uint32_t gc_num_sdp_interface; 292 uint32_t gc_num_tcps; 293 uint32_t gc_num_tcp_per_wpg; 294 uint32_t gc_tcp_l1_size; 295 uint32_t gc_num_sqc_per_wgp; 296 uint32_t gc_l1_instruction_cache_size_per_sqc; 297 uint32_t gc_l1_data_cache_size_per_sqc; 298 uint32_t gc_gl1c_per_sa; 299 uint32_t gc_gl1c_size_per_instance; 300 uint32_t gc_gl2c_per_gpu; 301 uint32_t gc_tcp_size_per_cu; 302 uint32_t gc_num_cu_per_sqc; 303 uint32_t gc_tcc_size; 304 uint32_t gc_tcp_cache_line_size; 305 uint32_t gc_instruction_cache_size_per_sqc; 306 uint32_t gc_instruction_cache_line_size; 307 uint32_t gc_scalar_data_cache_size_per_sqc; 308 uint32_t gc_scalar_data_cache_line_size; 309 uint32_t gc_tcc_cache_line_size; 310 }; 311 312 struct amdgpu_cu_info { 313 uint32_t simd_per_cu; 314 uint32_t max_waves_per_simd; 315 uint32_t wave_front_size; 316 uint32_t max_scratch_slots_per_cu; 317 uint32_t lds_size; 318 319 /* total active CU number */ 320 uint32_t number; 321 uint32_t ao_cu_mask; 322 uint32_t ao_cu_bitmap[4][4]; 323 uint32_t bitmap[AMDGPU_MAX_GC_INSTANCES][4][4]; 324 }; 325 326 struct amdgpu_gfx_ras { 327 struct amdgpu_ras_block_object ras_block; 328 void (*enable_watchdog_timer)(struct amdgpu_device *adev); 329 int (*rlc_gc_fed_irq)(struct amdgpu_device *adev, 330 struct amdgpu_irq_src *source, 331 struct amdgpu_iv_entry *entry); 332 int (*poison_consumption_handler)(struct amdgpu_device *adev, 333 struct amdgpu_iv_entry *entry); 334 }; 335 336 struct amdgpu_gfx_shadow_info { 337 u32 shadow_size; 338 u32 shadow_alignment; 339 u32 csa_size; 340 u32 csa_alignment; 341 u32 eop_size; 342 u32 eop_alignment; 343 }; 344 345 struct amdgpu_gfx_funcs { 346 /* get the gpu clock counter */ 347 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev); 348 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, 349 u32 sh_num, u32 instance, int xcc_id); 350 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 351 uint32_t wave, uint32_t *dst, int *no_fields); 352 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 353 uint32_t wave, uint32_t thread, uint32_t start, 354 uint32_t size, uint32_t *dst); 355 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 356 uint32_t wave, uint32_t start, uint32_t size, 357 uint32_t *dst); 358 void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe, 359 u32 queue, u32 vmid, u32 xcc_id); 360 void (*init_spm_golden)(struct amdgpu_device *adev); 361 void (*update_perfmon_mgcg)(struct amdgpu_device *adev, bool enable); 362 int (*get_gfx_shadow_info)(struct amdgpu_device *adev, 363 struct amdgpu_gfx_shadow_info *shadow_info, 364 bool skip_check); 365 enum amdgpu_gfx_partition 366 (*query_partition_mode)(struct amdgpu_device *adev); 367 int (*switch_partition_mode)(struct amdgpu_device *adev, 368 int num_xccs_per_xcp); 369 int (*ih_node_to_logical_xcc)(struct amdgpu_device *adev, int ih_node); 370 int (*get_xccs_per_xcp)(struct amdgpu_device *adev); 371 void (*get_hdp_flush_mask)(struct amdgpu_ring *ring, 372 uint32_t *ref_and_mask, uint32_t *reg_mem_engine); 373 }; 374 375 struct sq_work { 376 struct work_struct work; 377 unsigned ih_data; 378 }; 379 380 struct amdgpu_pfp { 381 struct amdgpu_bo *pfp_fw_obj; 382 uint64_t pfp_fw_gpu_addr; 383 uint32_t *pfp_fw_ptr; 384 385 struct amdgpu_bo *pfp_fw_data_obj; 386 uint64_t pfp_fw_data_gpu_addr; 387 uint32_t *pfp_fw_data_ptr; 388 }; 389 390 struct amdgpu_ce { 391 struct amdgpu_bo *ce_fw_obj; 392 uint64_t ce_fw_gpu_addr; 393 uint32_t *ce_fw_ptr; 394 }; 395 396 struct amdgpu_me { 397 struct amdgpu_bo *me_fw_obj; 398 uint64_t me_fw_gpu_addr; 399 uint32_t *me_fw_ptr; 400 401 struct amdgpu_bo *me_fw_data_obj; 402 uint64_t me_fw_data_gpu_addr; 403 uint32_t *me_fw_data_ptr; 404 405 uint32_t num_me; 406 uint32_t num_pipe_per_me; 407 uint32_t num_queue_per_pipe; 408 void *mqd_backup[AMDGPU_MAX_GFX_RINGS]; 409 bool use_mmio_for_reset; 410 411 /* These are the resources for which amdgpu takes ownership */ 412 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 413 }; 414 415 struct amdgpu_isolation_work { 416 struct amdgpu_device *adev; 417 u32 xcp_id; 418 struct delayed_work work; 419 }; 420 421 struct amdgpu_gfx { 422 struct mutex gpu_clock_mutex; 423 struct amdgpu_gfx_config config; 424 struct amdgpu_rlc rlc; 425 struct amdgpu_pfp pfp; 426 struct amdgpu_ce ce; 427 struct amdgpu_me me; 428 struct amdgpu_mec mec; 429 struct amdgpu_mec_bitmap mec_bitmap[AMDGPU_MAX_GC_INSTANCES]; 430 struct amdgpu_kiq kiq[AMDGPU_MAX_GC_INSTANCES]; 431 struct amdgpu_imu imu; 432 bool rs64_enable; /* firmware format */ 433 const struct firmware *me_fw; /* ME firmware */ 434 uint32_t me_fw_version; 435 const struct firmware *pfp_fw; /* PFP firmware */ 436 uint32_t pfp_fw_version; 437 const struct firmware *ce_fw; /* CE firmware */ 438 uint32_t ce_fw_version; 439 const struct firmware *rlc_fw; /* RLC firmware */ 440 uint32_t rlc_fw_version; 441 const struct firmware *mec_fw; /* MEC firmware */ 442 uint32_t mec_fw_version; 443 const struct firmware *mec2_fw; /* MEC2 firmware */ 444 uint32_t mec2_fw_version; 445 const struct firmware *imu_fw; /* IMU firmware */ 446 uint32_t imu_fw_version; 447 uint32_t me_feature_version; 448 uint32_t ce_feature_version; 449 uint32_t pfp_feature_version; 450 uint32_t rlc_feature_version; 451 uint32_t rlc_srlc_fw_version; 452 uint32_t rlc_srlc_feature_version; 453 uint32_t rlc_srlg_fw_version; 454 uint32_t rlc_srlg_feature_version; 455 uint32_t rlc_srls_fw_version; 456 uint32_t rlc_srls_feature_version; 457 uint32_t rlcp_ucode_version; 458 uint32_t rlcp_ucode_feature_version; 459 uint32_t rlcv_ucode_version; 460 uint32_t rlcv_ucode_feature_version; 461 uint32_t mec_feature_version; 462 uint32_t mec2_feature_version; 463 bool mec_fw_write_wait; 464 bool me_fw_write_wait; 465 bool cp_fw_write_wait; 466 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS]; 467 unsigned num_gfx_rings; 468 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS * AMDGPU_MAX_GC_INSTANCES]; 469 unsigned num_compute_rings; 470 struct amdgpu_irq_src eop_irq; 471 struct amdgpu_irq_src priv_reg_irq; 472 struct amdgpu_irq_src priv_inst_irq; 473 struct amdgpu_irq_src bad_op_irq; 474 struct amdgpu_irq_src cp_ecc_error_irq; 475 struct amdgpu_irq_src sq_irq; 476 struct amdgpu_irq_src rlc_gc_fed_irq; 477 struct amdgpu_irq_src rlc_poison_irq; 478 struct sq_work sq_work; 479 480 /* gfx status */ 481 uint32_t gfx_current_status; 482 /* ce ram size*/ 483 unsigned ce_ram_size; 484 struct amdgpu_cu_info cu_info; 485 const struct amdgpu_gfx_funcs *funcs; 486 487 /* reset mask */ 488 uint32_t gfx_supported_reset; 489 uint32_t compute_supported_reset; 490 491 /* gfx off */ 492 bool gfx_off_state; /* true: enabled, false: disabled */ 493 struct mutex gfx_off_mutex; /* mutex to change gfxoff state */ 494 uint32_t gfx_off_req_count; /* default 1, enable gfx off: dec 1, disable gfx off: add 1 */ 495 struct delayed_work gfx_off_delay_work; /* async work to set gfx block off */ 496 uint32_t gfx_off_residency; /* last logged residency */ 497 uint64_t gfx_off_entrycount; /* count of times GPU has get into GFXOFF state */ 498 499 /* pipe reservation */ 500 struct mutex pipe_reserve_mutex; 501 DECLARE_BITMAP (pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 502 503 /*ras */ 504 struct ras_common_if *ras_if; 505 struct amdgpu_gfx_ras *ras; 506 507 bool is_poweron; 508 509 struct amdgpu_ring sw_gfx_ring[AMDGPU_MAX_SW_GFX_RINGS]; 510 struct amdgpu_ring_mux muxer; 511 512 bool cp_gfx_shadow; /* for gfx11 */ 513 514 uint16_t xcc_mask; 515 uint32_t num_xcc_per_xcp; 516 struct mutex partition_mutex; 517 bool mcbp; /* mid command buffer preemption */ 518 519 /* IP reg dump */ 520 uint32_t *ip_dump_core; 521 uint32_t *ip_dump_compute_queues; 522 uint32_t *ip_dump_gfx_queues; 523 524 struct mutex reset_sem_mutex; 525 526 /* cleaner shader */ 527 struct amdgpu_bo *cleaner_shader_obj; 528 unsigned int cleaner_shader_size; 529 u64 cleaner_shader_gpu_addr; 530 void *cleaner_shader_cpu_ptr; 531 const void *cleaner_shader_ptr; 532 bool enable_cleaner_shader; 533 struct amdgpu_isolation_work enforce_isolation[MAX_XCP]; 534 /* Mutex for synchronizing KFD scheduler operations */ 535 struct mutex userq_sch_mutex; 536 u64 userq_sch_req_count[MAX_XCP]; 537 bool userq_sch_inactive[MAX_XCP]; 538 /* atomic bitmap of faulted gfx UQ slots (index = pipe | queue << 2) */ 539 unsigned long userq_priv_fault_slots; 540 struct work_struct userq_priv_fault_work; 541 unsigned long enforce_isolation_jiffies[MAX_XCP]; 542 unsigned long enforce_isolation_time[MAX_XCP]; 543 544 atomic_t total_submission_cnt; 545 struct delayed_work idle_work; 546 bool workload_profile_active; 547 struct mutex workload_profile_mutex; 548 549 bool disable_kq; 550 bool disable_uq; 551 }; 552 553 struct amdgpu_gfx_deferred_entry { 554 struct amdgpu_ring *ring; 555 struct amdgpu_fence *fence; 556 }; 557 558 struct amdgpu_gfx_ras_reg_entry { 559 struct amdgpu_ras_err_status_reg_entry reg_entry; 560 enum amdgpu_gfx_ras_mem_id_type mem_id_type; 561 uint32_t se_num; 562 }; 563 564 struct amdgpu_gfx_ras_mem_id_entry { 565 const struct amdgpu_ras_memory_id_entry *mem_id_ent; 566 uint32_t size; 567 }; 568 569 #define AMDGPU_GFX_MEMID_ENT(x) {(x), ARRAY_SIZE(x)}, 570 571 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev)) 572 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance, xcc_id) ((adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance), (xcc_id))) 573 #define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid, xcc_id) ((adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q), (vmid), (xcc_id))) 574 #define amdgpu_gfx_init_spm_golden(adev) (adev)->gfx.funcs->init_spm_golden((adev)) 575 #define amdgpu_gfx_get_gfx_shadow_info(adev, si) ((adev)->gfx.funcs->get_gfx_shadow_info((adev), (si), false)) 576 577 /** 578 * amdgpu_gfx_create_bitmask - create a bitmask 579 * 580 * @bit_width: length of the mask 581 * 582 * create a variable length bit mask. 583 * Returns the bitmask. 584 */ 585 static inline u32 amdgpu_gfx_create_bitmask(u32 bit_width) 586 { 587 return (u32)((1ULL << bit_width) - 1); 588 } 589 590 void amdgpu_gfx_parse_disable_cu(struct amdgpu_device *adev, unsigned int *mask, 591 unsigned int max_se, unsigned int max_sh); 592 593 int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev, int xcc_id); 594 595 void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring); 596 597 void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev, int xcc_id); 598 int amdgpu_gfx_kiq_init(struct amdgpu_device *adev, 599 unsigned hpd_size, int xcc_id); 600 601 int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev, 602 unsigned mqd_size, int xcc_id); 603 void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev, int xcc_id); 604 void amdgpu_gfx_mqd_symmetrically_map_cu_mask(struct amdgpu_device *adev, const uint32_t *cu_mask, 605 uint32_t cu_mask_count, uint32_t *se_mask); 606 int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev, int xcc_id); 607 int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev, int xcc_id); 608 int amdgpu_gfx_disable_kgq(struct amdgpu_device *adev, int xcc_id); 609 int amdgpu_gfx_enable_kgq(struct amdgpu_device *adev, int xcc_id); 610 611 void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev); 612 void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev); 613 614 int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec, 615 int pipe, int queue); 616 void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit, 617 int *mec, int *pipe, int *queue); 618 bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int xcc_id, 619 int mec, int pipe, int queue); 620 bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev, 621 struct amdgpu_ring *ring); 622 bool amdgpu_gfx_is_high_priority_graphics_queue(struct amdgpu_device *adev, 623 struct amdgpu_ring *ring); 624 bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me, 625 int pipe, int queue); 626 void amdgpu_gfx_handle_priv_fault(struct amdgpu_device *adev, 627 struct amdgpu_iv_entry *entry, 628 u8 me_id, u8 pipe_id, u8 queue_id); 629 void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable); 630 void amdgpu_gfx_off_ctrl_immediate(struct amdgpu_device *adev, bool enable); 631 int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value); 632 int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block); 633 void amdgpu_gfx_ras_suspend(struct amdgpu_device *adev, struct ras_common_if *ras_block); 634 void amdgpu_gfx_ras_fini(struct amdgpu_device *adev, struct ras_common_if *ras_block); 635 int amdgpu_get_gfx_off_entrycount(struct amdgpu_device *adev, u64 *value); 636 int amdgpu_get_gfx_off_residency(struct amdgpu_device *adev, u32 *residency); 637 int amdgpu_set_gfx_off_residency(struct amdgpu_device *adev, bool value); 638 int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev, 639 void *err_data, 640 struct amdgpu_iv_entry *entry); 641 int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev, 642 struct amdgpu_irq_src *source, 643 struct amdgpu_iv_entry *entry); 644 uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg, uint32_t xcc_id); 645 void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, uint32_t xcc_id); 646 void amdgpu_gfx_get_hdp_flush_mask(struct amdgpu_ring *ring, 647 uint32_t *ref_and_mask, uint32_t *reg_mem_engine); 648 int amdgpu_kiq_hdp_flush(struct amdgpu_device *adev); 649 int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev); 650 void amdgpu_gfx_cp_init_microcode(struct amdgpu_device *adev, uint32_t ucode_id); 651 652 int amdgpu_gfx_ras_sw_init(struct amdgpu_device *adev); 653 int amdgpu_gfx_poison_consumption_handler(struct amdgpu_device *adev, 654 struct amdgpu_iv_entry *entry); 655 656 bool amdgpu_gfx_is_master_xcc(struct amdgpu_device *adev, int xcc_id); 657 int amdgpu_gfx_sysfs_init(struct amdgpu_device *adev); 658 void amdgpu_gfx_sysfs_fini(struct amdgpu_device *adev); 659 int amdgpu_gfx_reset_mes_compute(struct amdgpu_device *adev, 660 struct amdgpu_ring *ring, 661 struct amdgpu_fence *guilty_fence, 662 struct amdgpu_usermode_queue *uq, 663 unsigned int *hung_queue_count, 664 void *faulty_queue_input); 665 void amdgpu_gfx_ras_error_func(struct amdgpu_device *adev, 666 void *ras_error_status, 667 void (*func)(struct amdgpu_device *adev, void *ras_error_status, 668 int xcc_id)); 669 int amdgpu_gfx_cleaner_shader_sw_init(struct amdgpu_device *adev, 670 unsigned int cleaner_shader_size); 671 void amdgpu_gfx_cleaner_shader_sw_fini(struct amdgpu_device *adev); 672 void amdgpu_gfx_cleaner_shader_init(struct amdgpu_device *adev, 673 unsigned int cleaner_shader_size, 674 const void *cleaner_shader_ptr); 675 void amdgpu_gfx_enforce_isolation_handler(struct work_struct *work); 676 void amdgpu_gfx_enforce_isolation_ring_begin_use(struct amdgpu_ring *ring); 677 void amdgpu_gfx_enforce_isolation_ring_end_use(struct amdgpu_ring *ring); 678 679 void amdgpu_gfx_profile_idle_work_handler(struct work_struct *work); 680 void amdgpu_gfx_profile_ring_begin_use(struct amdgpu_ring *ring); 681 void amdgpu_gfx_profile_ring_end_use(struct amdgpu_ring *ring); 682 u32 amdgpu_gfx_csb_preamble_start(u32 *buffer); 683 u32 amdgpu_gfx_csb_data_parser(struct amdgpu_device *adev, u32 *buffer, u32 count); 684 void amdgpu_gfx_csb_preamble_end(u32 *buffer, u32 count); 685 686 void amdgpu_debugfs_gfx_sched_mask_init(struct amdgpu_device *adev); 687 void amdgpu_debugfs_compute_sched_mask_init(struct amdgpu_device *adev); 688 689 int amdgpu_gfx_ring_preempt_ib(struct amdgpu_ring *ring); 690 691 int amdgpu_gfx_mes_reset_queue(struct amdgpu_ring *ring, 692 unsigned int vmid, 693 struct amdgpu_fence *timedout_fence, 694 bool use_mmio); 695 696 static inline const char *amdgpu_gfx_compute_mode_desc(int mode) 697 { 698 switch (mode) { 699 case AMDGPU_SPX_PARTITION_MODE: 700 return "SPX"; 701 case AMDGPU_DPX_PARTITION_MODE: 702 return "DPX"; 703 case AMDGPU_TPX_PARTITION_MODE: 704 return "TPX"; 705 case AMDGPU_QPX_PARTITION_MODE: 706 return "QPX"; 707 case AMDGPU_CPX_PARTITION_MODE: 708 return "CPX"; 709 default: 710 return "UNKNOWN"; 711 } 712 } 713 714 static inline const char *amdgpu_gfx_compute_mem_alloc_mode_desc(int mode) 715 { 716 switch (mode) { 717 case AMDGPU_PARTITION_MEM_CAPPING_EVEN: 718 return "CAPPING"; 719 case AMDGPU_PARTITION_MEM_ALLOC_ALL: 720 return "ALL"; 721 default: 722 return "UNKNOWN"; 723 } 724 } 725 726 #endif 727