12cddc50eSHuang Rui /* 22cddc50eSHuang Rui * Copyright 2018 Advanced Micro Devices, Inc. 32cddc50eSHuang Rui * 42cddc50eSHuang Rui * Permission is hereby granted, free of charge, to any person obtaining a 52cddc50eSHuang Rui * copy of this software and associated documentation files (the "Software"), 62cddc50eSHuang Rui * to deal in the Software without restriction, including without limitation 72cddc50eSHuang Rui * the rights to use, copy, modify, merge, publish, distribute, sublicense, 82cddc50eSHuang Rui * and/or sell copies of the Software, and to permit persons to whom the 92cddc50eSHuang Rui * Software is furnished to do so, subject to the following conditions: 102cddc50eSHuang Rui * 112cddc50eSHuang Rui * The above copyright notice and this permission notice shall be included in 122cddc50eSHuang Rui * all copies or substantial portions of the Software. 132cddc50eSHuang Rui * 142cddc50eSHuang Rui * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 152cddc50eSHuang Rui * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 162cddc50eSHuang Rui * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 172cddc50eSHuang Rui * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 182cddc50eSHuang Rui * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 192cddc50eSHuang Rui * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 202cddc50eSHuang Rui * OTHER DEALINGS IN THE SOFTWARE. 212cddc50eSHuang Rui * 222cddc50eSHuang Rui */ 232cddc50eSHuang Rui #ifndef __AMDGPU_GEM_H__ 242cddc50eSHuang Rui #define __AMDGPU_GEM_H__ 252cddc50eSHuang Rui 262cddc50eSHuang Rui #include <drm/amdgpu_drm.h> 272cddc50eSHuang Rui #include <drm/drm_gem.h> 282cddc50eSHuang Rui 292cddc50eSHuang Rui /* 302cddc50eSHuang Rui * GEM. 312cddc50eSHuang Rui */ 322cddc50eSHuang Rui 332cddc50eSHuang Rui #define AMDGPU_GEM_DOMAIN_MAX 0x3 34c105de28SGerd Hoffmann #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, tbo.base) 352cddc50eSHuang Rui 362cddc50eSHuang Rui unsigned long amdgpu_gem_timeout(uint64_t timeout_ns); 371dde0ea9SFelix Kuehling 382cddc50eSHuang Rui /* 392cddc50eSHuang Rui * GEM objects. 402cddc50eSHuang Rui */ 412cddc50eSHuang Rui void amdgpu_gem_force_release(struct amdgpu_device *adev); 422cddc50eSHuang Rui int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, 432cddc50eSHuang Rui int alignment, u32 initial_domain, 442cddc50eSHuang Rui u64 flags, enum ttm_bo_type type, 4552791eeeSChristian König struct dma_resv *resv, 46*3ebfd221SPhilip Yang struct drm_gem_object **obj, int8_t xcp_id_plus1); 472cddc50eSHuang Rui int amdgpu_mode_dumb_create(struct drm_file *file_priv, 482cddc50eSHuang Rui struct drm_device *dev, 492cddc50eSHuang Rui struct drm_mode_create_dumb *args); 502cddc50eSHuang Rui int amdgpu_mode_dumb_mmap(struct drm_file *filp, 512cddc50eSHuang Rui struct drm_device *dev, 522cddc50eSHuang Rui uint32_t handle, uint64_t *offset_p); 532cddc50eSHuang Rui 542cddc50eSHuang Rui int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 552cddc50eSHuang Rui struct drm_file *filp); 562cddc50eSHuang Rui int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data, 572cddc50eSHuang Rui struct drm_file *filp); 582cddc50eSHuang Rui int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, 592cddc50eSHuang Rui struct drm_file *filp); 602cddc50eSHuang Rui int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, 612cddc50eSHuang Rui struct drm_file *filp); 622cddc50eSHuang Rui int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 632cddc50eSHuang Rui struct drm_file *filp); 6471776b6dSChristian König uint64_t amdgpu_gem_va_map_flags(struct amdgpu_device *adev, uint32_t flags); 652cddc50eSHuang Rui int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 662cddc50eSHuang Rui struct drm_file *filp); 672cddc50eSHuang Rui int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, 682cddc50eSHuang Rui struct drm_file *filp); 692cddc50eSHuang Rui 702cddc50eSHuang Rui int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, 712cddc50eSHuang Rui struct drm_file *filp); 722cddc50eSHuang Rui 732cddc50eSHuang Rui #endif 74